CN107241163A - A kind of interleaving treatment method and device - Google Patents
A kind of interleaving treatment method and device Download PDFInfo
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- CN107241163A CN107241163A CN201710295108.1A CN201710295108A CN107241163A CN 107241163 A CN107241163 A CN 107241163A CN 201710295108 A CN201710295108 A CN 201710295108A CN 107241163 A CN107241163 A CN 107241163A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
Abstract
Pending intertexture task is obtained in a kind of interleaving treatment method and device, this method, and determines the memory space that interleaver is interleaved to the pending intertexture task needed for processing.According to pending intertexture required by task memory space and the maximum piecemeal memory space of interleaver, the memory space of the interleaver is divided into N number of piecemeal memory space, the N is positive integer, wherein, the size of each piecemeal memory space is respectively less than the size for being equal to maximum piecemeal memory space in N number of piecemeal memory space.The pending intertexture task is divided at least one interleaving block, and in units of interleaving block, interleaving block is write in N number of piecemeal memory space, to solve the problem of big storage overhead, processing delay length and frequent size specification task switching.
Description
Technical field
The application is related to communication technical field, more particularly to a kind of interleaving treatment method and device.
Background technology
Physical layer is the bottom of radio interface layer, directly affects wireless link capacity and systematic function quality.Bit
Information processing is a complex process step in physical layer, but in this variable-parameter channel of land mobile, bit error
Often bunchiness occurs, and if meeting with bursty interference, some important bit informations are destroyed.
Wherein, intertexture is a kind of effective technology for overcoming bursty interference.By upsetting intersymbol correlation, by burst
Interference randomization, reduces the influence that channel fading and interference fringe come.At present, it can be handed in transmitting terminal using the channel of " row write row are read "
Knit mode.Accordingly, the deinterleaving mode of " row write capable reading " is then used in receiving terminal.For example, initial data is pressed row by transmitting terminal
Interleaver matrix is inserted, interleaving data is obtained after reading in column form, interleaving data is sent to receiving terminal, receiving terminal will interweave
Interleaver matrix is written in column in data, then the deinterleaving for realizing interleaving data is read by row.
Wherein, intertexture can be realized by interleaver, it is assumed that CmuxFor the columns of interleaver matrix, RmuxFor the line number of interleaver matrix,
LmuxFor the interleaving data granularity of interleaver matrix, then interleaver realizes that intertexture needs Cmux*Rmux*LmuxStorage overhead.By handing over
Knit device and realize that first by " OK " order, each clock cycle fills a position of interleaver, and L is deposited in each position when interweavingmux
Individual data, whole " OK " is write after expiring, then sequentially sequential reads out data by " row ", completes interleaving process.Wherein, during the processing of intertexture
Between be Cmux*Rmux, and need that intertexture could be started after all " OK " write-ins, startup time delay is Cmux*Rmux.Similar, pass through solution
When interleaver realizes deinterleaving, it is also desirable to Cmux*Rmux*LmuxStorage overhead, by " row " order, the filling of each clock cycle is handed over
A position of device is knitted, L is deposited in each positionmuxIndividual data, after all " row " are write completely, then are completed by data " OK " are read successively
Deinterleaving process.
The above-mentioned process for being interleaved/deinterleaving, completing " row write row reading/row write capable reading " needs Cmux*Rmux*LmuxDeposit
Reservoir expense, storage overhead is big, and cost is high, and needs Cmux*RmuxThe individual clock cycle is filled up after all row/columns, could be started
Interleaving/deinterleaving, it is slow that interleaving/deinterleaving starts the time.Further, each clock cycle is only capable of inserting a data, all
Filling up needs Cmux*RmuxThe individual clock cycle, the efficiency of interleaving/deinterleaving is also than relatively low.And due to agreement evolution, the line number of intertexture
Also become big with columns size heterogeneity, under many concurrent scenes of scene, the switching of size specification task is frequent, and handover delay is larger.
The content of the invention
The embodiment of the present application provides a kind of interleaving treatment method and device, to solve that storage overhead is big, processing delay length with
And size specification task switching it is frequent the problem of.
First aspect is there is provided a kind of interleaving treatment method, in the interleaving treatment method, gets pending intertexture and appoints
Business, is divided into multiple piecemeals by the memory space of interleaver according to pending intertexture required by task storage size and stores empty
Between, the pending intertexture task is divided at least one interleaving block, and in units of interleaving block, deposited in the multiple piecemeal
Store up in space, realize multiple piecemeal memory space parallel processing intertexture tasks.
Maximum piecemeal memory space can be set in the embodiment of the present application, the size of each piecemeal memory space, which is respectively less than, to be equal to
The memory space of the intertexture required by task of the size of maximum piecemeal memory space, i.e. each piecemeal memory space processing without departing from
The maximum piecemeal memory space, and then can limit at the size of the intertexture task of each piecemeal memory space processing, equiblibrium mass distribution
Manage time delay.Wherein, it can be deposited according to the pending intertexture required by task memory space of acquisition and the maximum piecemeal of interleaver memory
Space is stored up, the memory space of interleaver is divided into N number of piecemeal memory space.Wherein, the N is positive integer.
Wherein, if pending intertexture required by task memory space is less than or equal to maximum piecemeal memory space B, it can not treat
Processing intertexture task is divided, and writes N number of piecemeal memory space using pending intertexture task as an interleaving block
The storage size included is the first piecemeal memory space of the pending intertexture required by task storage size.And
And if exist it is multiple needed for memory spaces be less than maximum piecemeal memory space B intertexture tasks, in interleaver memory space not
In the case of change, it can be less than maximum piecemeal memory space B's in the multiple required memory spaces of memory space memory storage of interleaver
Intertexture task.
Wherein, if pending intertexture required by task memory space is more than maximum piecemeal memory space B, intertexture can be treated and appointed
Business carries out piecemeal processing, and pending intertexture task is divided into multiple interleaving blocks, and will divide obtained multiple interleaving blocks, to hand over
It is the size that unit writes that storage size in N number of piecemeal memory space is the maximum piecemeal memory space to knit block
In at least one second piecemeal memory space, realize and parallel processing is carried out to multiple interleaving blocks.
In a kind of possible design, it is more than maximum piecemeal memory space situation in pending intertexture required by task memory space
Under, pending intertexture task piecemeal can be handled, can be B and intertexture task according to maximum piecemeal memory space during specific piecemeal
Matrix column number CmuxBlock granularity R is determined, then treating intertexture task according to intertexture granularity R carries out piecemeal processing.For example, can
By R=B/CmuxBlock granularity, to Cmux*RmuxInterleaver matrix carry out piecemeal processing, obtain several Cmux* R interleaving block,
Piecemeal is carried out to the pending intertexture task and handles the line number of the interleaver matrix obtained in interleaving block for the maximum piecemeal
The business of memory space interleaver matrix columns corresponding with the pending intertexture task；Piecemeal is carried out to the pending intertexture task
It is the pending intertexture task correspondence interleaver matrix columns that processing, which obtains the columns of the interleaver matrix in interleaving block,.To divide
The interleaving block arrived is in unit, the maximum piecemeal memory space that interleaving block is write to interleaver, you can complete in an interleaving block
Intertexture into " row write row reading/row write capable reading " is operated.
In another possible design, each interleaving block can be stored using circular buffer mechanism, for example, carrying out different interleaving block
Although the data of address space left space not enough one complete interleaving block of storage when task switches, can be according to dynamic waterline, will be surplus
Complementary space is filled up, and the data not inputted are inputted by back-pressure when space allows.In the case of above-mentioned circular buffer mechanism,
The memory space of interleaver, which divides obtained N number of piecemeal memory space, includes the 3rd piecemeal memory space, and the 3rd piecemeal is deposited
Store up space size be less than the interleaving block in maximum piecemeal storage size, and write-in the 3rd piecemeal memory space for pair
Part interleaving block in the interleaving block obtained after the pending intertexture task progress piecemeal processing.Using above-mentioned circular buffer machine
System can be avoided because after piecemeal, the interspersed dispatching efficiency brought of size interleaving block loses.
In another possible design, when needing to carry out layered mapping for multilayer code word, layer can be equivalent to intertexture square
The columns of battle array, i.e., be equivalent to the pending intertexture task correspondence interleaver matrix columns with handing over described by the columns of interleaver matrix
The product that matrix carries out the number of plies of layer mapping is knitted, and processing is interleaved using the above-mentioned interleaving treatment mode being related to, is realized complete
Embark on journey column interleaving while complete layered mapping process.
In another possible design, for the scene for the bypass that interweaves, each row after the bypass that interweaves can be equivalent to one
Individual LmuxThe small task of row, then it is equivalent after interleaver matrix midrange Ceq=Lmux, number of tasks T=Cmux, block count is Cmux*Mmux,
Then the interleaving treatment mode being related to according to above-mentioned first aspect is interleaved processing procedure, while may be implemented in intertexture bypass
Complete layered mapping.
Second aspect is there is provided a kind of interleaving treatment device, and the interleaving treatment device, which possesses, realizes above-mentioned interleaving treatment method
The repertoire of middle interleaver.The function can be realized by hardware, and corresponding software can also be performed by hardware and is realized.
The hardware or software include one or more modules corresponding with above-mentioned functions.The module can be software and/or hard
Part.
In a kind of possible design, the interleaving treatment device includes acquiring unit, processing unit and interleave unit.Obtain single
Member, processing unit can be corresponding with various method steps with the function of interleave unit, will not be described here.
The third aspect includes mapping circuit, read/write circuit and interleaver memory there is provided a kind of interleaver, the interleaver.
Wherein, mapping circuit and read/write circuit are used to perform the interleaving treatment in any possible design of first aspect or first aspect
Method, and by the data storage in interleaving procedure to interleaver memory.
Fourth aspect is there is provided a kind of calculation machine readable storage medium storing program for executing or computer program product, for storing computer journey
Sequence, the computer program is used to perform the method in first aspect and any possible design of first aspect.
Brief description of the drawings
Fig. 1 realizes the structural representation of device for a kind of bit-level that the embodiment of the present application is provided；
Fig. 2 realizes the structural representation of device for another bit-level that the embodiment of the present application is provided；
A kind of interleaving treatment method flow diagram that Fig. 3 provides for the embodiment of the present application
Fig. 4 divides schematic diagram for interleaver memory space one kind that the embodiment of the present application is provided；
Fig. 5 is another division schematic diagram of interleaver memory space that the embodiment of the present application is provided；
The intertexture task processes schematic diagram that Fig. 6 provides for the embodiment of the present application；
The intertexture task processes schematic diagram that Fig. 7 provides for the embodiment of the present application；
The TP-RAM for 4 pieces of twoports of use that Fig. 8 provides for the embodiment of the present application storage data format；
The process schematic for the write-in data that Fig. 9 provides for the embodiment of the present application；
The process schematic for the reading data that Figure 10 provides for the embodiment of the present application；
The circulation storing process schematic diagram that Figure 11 provides for the embodiment of the present application；
The interleaving process schematic diagram that Figure 12 provides for the embodiment of the present application；
Figure 13 is mapped for the intertexture that the embodiment of the present application is provided with layer while the process schematic completed；
Figure 14 is mapped for the intertexture that the embodiment of the present application is provided with layer while the data completed deposit process schematic；
Figure 15 completes the processing procedure of layered mapping while interweaving and bypass for the realization that the embodiment of the present application is provided；
A kind of structural representation for interleaving treatment device that Figure 16 provides for the embodiment of the present application；
Another structural representation for the interleaving treatment device that Figure 17 provides for the embodiment of the present application.
Embodiment
Below in conjunction with accompanying drawing, the technical scheme in the embodiment of the present application is described.
In order to tackle the change of agreement during bit-level is handled respectively, the problem of flexible expansion supports several scenes sends
End can realize device using the bit-level of the high flexible expansion towards 5G shown in Fig. 1, and receiving terminal can be using the face shown in Fig. 2
Device is realized to the bit-level of 5G high flexible expansion, various frame formats are flexibly supported, and each module can flexible carry out group
Close.
In Fig. 1, subtask controller is used for the scheduling for controlling subtask.Modulation module is used to calculate time domain/frequency domain modulation
Symbol average.Scrambling module is used to calculate data scrambling.Ascending control information (Uplink Control Information,
UCI) Multiplexing module is used to carry out channel quality instruction (Channel Quality Indicator, CQI), resource identification
(Resource Identifier, RI) and response instruction (ACKnowledge, ACK) coding, and CQI, RI, ACK and pilot tone
With the multiplexing of data.Interleaver is used to carry out piecemeal processing to data, to random access memory (random access
Memory, RAM) it is written and read the out of order read-write in address.Double Data Rate synchronous DRAM (Dual Data Rate 0,
DDR0) it is used to store the data before interweaving.DDR1 is used to store the data after interweaving.Wherein, in physics realization, above-mentioned DDR0 and
Different address section during DDR1 can also be cached with same is replaced.
In Fig. 2, subtask controller can control subtask scheduling, and demodulation module is used to calculate the soft of each data
Information, the data that descrambling module is used for before calculating scrambling, ascending control information (Uplink Control Information,
UCI) detection module is used to carry out RI and ACK mappings and decoded.Deinterleaver is used to carry out piecemeal processing to data, to RAM
It is written and read the out of order read-write in address.UCI is demultiplexed and detection module is used for RI, ACK, pilot tone and data separating, and calculates RI/
ACK testing results.DDR0：The DDR of data before external storage interweaves.DDR1：The DDR of external storage interleaved data.Wherein, thing
On reason is realized, the different address section during above-mentioned DDR0 and DDR1 can also be cached with same is replaced
Bit-level shown in Fig. 1 and Fig. 2 realizes that each processing module of device is carried out in bit-level data handling procedure, subtask
The startup of each module of controller flexibly configurable and handling process, to adapt to various scenes.For example can be by the groups of various switches
Close, realize under 5G various changes, only bypass the module of the change, remaining function can be with normal operation.Or pass through various switches
Combination, can develop and tens hundreds of scenes, cover most of possible extended scene.By the various data contents of output and
Form carries out flexible configuration by switching, and realizes under 5G various changes, can bypass some data of output for software or other are hard
Part module is handled.For example, being deinterleaved in 5G with layer mapping process, frame format and interleaving mode are handed over by level solution
Knit, bit-level is deinterleaved and symbol level deinterleaves three kinds of complex scenes, real for the bit-level shown in the complex scene application drawing 2
Existing device, the configuration mode that subtask controller can be respectively adopted shown in table 1 below is realized.
Table 1
Wherein, in order to save scheduling delay, complicated frame format can split into multiple subtasks and be handled.Fig. 1 and Fig. 2
Shown bit-level realizes that device neutron task controller can realize the mode of many subtask single scheduling, and complex task is split
Only need scheduling once afterwards, device automatically continuously performs multiple subtasks, finally sends completion message.For example：It is not inconsistent with some
Close exemplified by LTE frame formats, scheduling delay reduced using subtask, by splitting task, the processing under complex scene is realized in combination,
There is low overhead low time delay.
Wherein, the bit-level shown in Fig. 1 and Fig. 2 realizes that device can support a variety of bitmap modes to carry out RI/ACK mappings.Example
Such as support the RI/ACK bitmaps of column distribution, can also support resource particle (Resource Element, RE) level be distributed RI, ACK,
Pilot tone bitmap, to realize under various frame format scenes, can normally complete the demodulation of data path, descramble, deinterleave, demultiplexing
With, it is ensured that rear class being capable of pre-cooling.And RI/ACK can be demodulated according to specified format, descrambled, separating, deinterleaving, solving layer and reflect
Penetrate, farthest the expense of reduction software, reduces processing delay.
Wherein, the bit-level shown in Fig. 1 realizes that device can be supported flexibly under plurality of specifications, and the intertexture and layer of data are reflected
Penetrate, the bit-level shown in Fig. 2 realizes that device can be supported flexibly under plurality of specifications, layer mapping is conciliate in the deinterleaving of data, to solve
Storage overhead is big, processing delay length and the problem of frequent size specification task switching.
Realize that device realizes the process of interleaving treatment mainly for the bit-level shown in application drawing 1 below the embodiment of the present application
Illustrate, due to deinterleaving the inverse process to interweave, therefore process the embodiment of the present application for deinterleaving is no longer described in detail.
Fig. 3 show a kind of interleaving treatment method flow diagram of the embodiment of the present application offer, the interleaving treatment side shown in Fig. 3
Method executive agent can be interleaver, be referred to as interleaver memory, as shown in fig.3, including：
S101：Pending intertexture task is obtained, and determines that interleaver is interleaved processing to the pending intertexture task
Required memory space.
Pending intertexture task in the embodiment of the present application can be understood as with interleaver matrix form present respectively wait hand over
Organization data.Interleaver refers to the part that data are interleaved with processing.Interleaver is interleaved in processing procedure, it is necessary to distribute and deposited
Store up space storage interleaving data, wherein, the size of the memory space of the distribution can by the line number of interleaver matrix, columns and
Interleaving data granularity is represented, for example, interleaver is to Cmux*RmuxInterleaver matrix be interleaved processing, the intertexture number of interleaver matrix
It is L according to granularitymux, then it is C that interleaver, which is interleaved to interleaver matrix and handles distributed storage size,mux*Rmux*Lmux。
S102：According to pending intertexture required by task memory space and the maximum piecemeal memory space of interleaver memory,
The memory space of the interleaver is divided into N number of piecemeal memory space.Wherein, the N is positive integer.
In the embodiment of the present application for increase processing degree of parallelism, and reduce processing delay and storage overhead, can be according to waiting to locate
The memory space of interleaver is divided into multiple piecemeal memory spaces by reason intertexture required by task storage size, and multiple piecemeals are deposited
Store up spatial parallelism processing intertexture task.Maximum piecemeal memory space, each piecemeal memory space can be set in the embodiment of the present application
Size be respectively less than the size for being equal to maximum piecemeal memory space, i.e., the intertexture required by task of each piecemeal memory space processing
Memory space can limit the intertexture task that each piecemeal memory space is handled without departing from the maximum piecemeal memory space
Size, equiblibrium mass distribution processing delay.
It can be deposited in the following way according to pending intertexture required by task memory space and intertexture in the embodiment of the present application
The maximum piecemeal memory space of reservoir, N number of piecemeal memory space is divided into by the memory space of the interleaver：
Assuming that the size of maximum piecemeal memory space is B, if pending intertexture required by task memory space is less than or equal to institute
Maximum piecemeal memory space B is stated, then it is the pending friendship that a storage size is divided in the memory space of interleaver
The first piecemeal memory space of required by task storage size is knitted, the required storage is write in the first piecemeal memory space
Space is less than or equal to the pending intertexture task of the maximum piecemeal memory space B.If pending intertexture required by task storage
Space is more than the maximum piecemeal memory space B, then at least one storage size is divided in the memory space of interleaver
For the second piecemeal memory space of the maximum piecemeal memory space B sizes, the quantity foundation of the second piecemeal memory space is waited to hand over
Knit required by task memory space to determine, that is, multiple second memory spaces divided disclosure satisfy that the pending intertexture task
All write-ins.The part intertexture task of pending intertexture task is write in the second piecemeal memory space, the part interweaves
Storage size shared by task is the size of the maximum piecemeal memory space B, or is deposited less than the maximum piecemeal
Store up the size of space B.Wherein, the part intertexture task can be understood as depositing required memory space more than the maximum piecemeal
Storage space B carries out the interleaving block obtained after piecemeal processing.
Remaining memory space after the first piecemeal memory space or the second piecemeal memory space has been divided for memory space,
It can continue to be divided according to the memory space of other pending intertexture required by task in the manner described above, and divide what is obtained
The interleaving block obtained after intertexture task or after carrying out piecemeal processing to the pending intertexture task is write in memory space.
In the embodiment of the present application for convenience of description, the piecemeal storage obtained after the memory space to interleaver is divided
Amount of space be set as it is N number of, the N be positive integer, specific value is according to pending intertexture task quantity and required memory space
Size is determined.
S103：The pending intertexture task is divided at least one interleaving block, and in units of interleaving block, described
Write-in interleaving block in N number of piecemeal memory space.
Interleaver is divided into N number of piecemeal memory space in the embodiment of the present application, then can be in N number of piecemeal memory space
Intertexture task is inside respectively written into, the parallel processing of multiple intertexture tasks is realized., can will be pending applied in the embodiment of the present application
Intertexture task is divided at least one interleaving block, and in units of interleaving block, writes and interweave in N number of piecemeal memory space
Block.Wherein, can not be to pending if pending intertexture required by task memory space is less than or equal to maximum piecemeal memory space B
Intertexture task is divided, and pending intertexture task is write in N number of piecemeal memory space as an interleaving block and wrapped
The storage size included is the first piecemeal memory space of the pending intertexture required by task storage size.And if
There is the intertexture task that multiple required memory spaces are less than maximum piecemeal memory space B, then it is constant in interleaver memory space
In the case of, maximum piecemeal memory space B intertexture can be less than in the multiple required memory spaces of memory space memory storage of interleaver
Task.As shown in figure 4, the memory space internal memory in interleaver contains Bs0、Bs1、Bs2、Bs3、Bs4And Bs5One six intertexture is appointed
Business, the storage size of six intertexture required by task is respectively less than maximum piecemeal memory space B, interleaver can parallel processing this six
Individual intertexture task.
Wherein, if pending intertexture required by task memory space is more than maximum piecemeal memory space B, intertexture can be treated and appointed
Business carries out piecemeal processing, and pending intertexture task is divided into multiple interleaving blocks, and will divide obtained multiple interleaving blocks, to hand over
It is the size that unit writes that storage size in N number of piecemeal memory space is the maximum piecemeal memory space to knit block
In at least one second piecemeal memory space.For example, pending intertexture task Bb0Required memory space is 2B, then will be pending
Intertexture task is divided into two interleaving blocks, respectively Bb0SLC0And Bb0SLC1, Bb0SLC0And Bb0SLC1Required memory space is big
Small is maximum piecemeal memory space B, by Bb0SLC0And Bb0SLC1It is respectively written into storage size in N number of piecemeal memory space
In two piecemeal memory spaces for the size of the maximum piecemeal memory space, as shown in Figure 5.Interleaver in shown in Fig. 5
Two interleaving blocks of the pending intertexture task of write-in in memory space, the interleaver can parallel be located to the two interleaving blocks
Reason.
Interleaver memory space is divided into according to intertexture task size using the embodiment of the present application above-mentioned offer multiple
Piecemeal memory space, the process of the multiple intertexture tasks of parallel processing realizes a kind of variable interleaving mode of Block granularity, realizes
Process schematic can be as shown in Figure 6.In Fig. 6, interleaving block 0, interleaving block 1, interleaving block 2 and interleaving block 3 are interleaved treated
Cheng Zhong, can write interleaving block 0, interleaving block 1, interleaving block 2 and interleaving block 3 successively in units of interleaving block, and complete interleaving block
It is subsequently similar to be interleaved the reading of block 1, interleaving block 2 and interleaving block 3 after 0 write-in, you can be interleaved the read operation of block 0
Operation, refering to shown in Fig. 6.
If pending intertexture required by task memory space is less than or equal to maximum piecemeal memory space in the embodiment of the present application,
Without carrying out piecemeal processing to pending intertexture task, write division according to original intertexture task interleaving treatment mode and obtain pair
Answer piecemeal memory space.It is more than maximum piecemeal memory space feelings to pending intertexture required by task memory space emphatically below
Under condition, the processing of pending intertexture task piecemeal and the process for writing progress interleaving treatment after interleaving block are illustrated.
It is that columns is C that pending intertexture task is assumed in the embodiment of the present applicationmux, line number is RmuxInterleaver matrix, it is maximum
Piecemeal memory space is B, then can be by R=B/CmuxBlock granularity, to Cmux*RmuxInterleaver matrix carry out piecemeal processing, obtain
Several Cmux* R interleaving block, i.e., carry out piecemeal to the pending intertexture task and handle the interleaver matrix obtained in interleaving block
Line number for maximum piecemeal memory space interleaver matrix columns corresponding with the pending intertexture task business；Treated to described
It is the pending intertexture task correspondence that processing intertexture task, which carries out piecemeal and handles the columns of the interleaver matrix obtained in interleaving block,
Interleaver matrix columns.In units of dividing obtained interleaving block, in the maximum piecemeal memory space that interleaving block is write to interleaver,
The intertexture operation of " row write row reading/row write capable reading " can be completed in an interleaving block, as shown in Figure 7.Divide what is obtained in Fig. 7
Interleaving block is expressed as Cmux*R0、Cmux*R1……Cmux*Rn.Data are sequentially written in interleaver by " row/column ", write full Cmux*R0
Data volume after all data in this interleaving block can be sequentially read by " column/row ", reserved address when " row " are exported during intertexture
Skew, it is ensured that the final continuous arrangement in DDR of data of each interleaving block output.Jump, which is read, when " row " are inputted during deinterleaving interweaves
Continuous interleaving data in data in block, final equivalent reading DDR.Same continuation is sequentially written in interleaver by " row/column ", writes full
Cmux*R1Data volume after all data in this interleaving block can be sequentially read by " column/row ".Follow-up interleaving block is handled successively,
Until completing to all interleaving treatments for dividing obtained interleaving block.Using such a interleaving treatment mode, the startup time delay of intertexture
It is reduced to Cmux* R, and no longer it is Cmux*Rmux, processing delay can be reduced.
Below the embodiment of the present application by taking the channel interleaving processing procedure of a numeral in LTE protocol as an example, it is related to above-mentioned
Interleaving procedure illustrate.According to agreement, sequential resource single-carrier frequency division multiple access (Single-carrier
Frequency-Division Multiple Access, SC-FDMA) symbol order correspond to interleaver matrix in row sequence number
Cmux, the row sequence number R that frequency domain resource RE orders correspond in interleaver matrixmux.Assuming that data block size is Cmux*Rmux=16*
300, B=2048, then R=2048/16=128, i.e., carry out piecemeal intertexture by R=128, and whole data block is divided into 3 interleaving blocks
Processing.R0=128, R1=128, R0=44.The first two piecemeal is with 16 data of a line, and 128 traveling row writes enter, after the completion of write-in,
Successively by row output 128 data of each column.In order that external data is continuous, OPADD is offset, row 0 export 0~127
Put, row 1 offset 300 Data Positions relative to row 0, write 300~327 positions, the like.When second piecemeal output,
Row 0 write 128~255 positions, and row 1 write 328~555 positions ... when the 3rd piecemeal is exported, the write-in of row 0 256~299
Position, row 1 write 556~599 positions ....If data block size is Cmux*Rmux=64*300, B=2048, then R=2048/
64=32, i.e., carry out piecemeal intertexture by R=32, and whole data block is divided into 10 interleaving block processing.R0=32, R1=32 ... R9=
12。
The above-mentioned interleaving treatment mode of the embodiment of the present application, can be realized and pending interweave for different by setting B size
Task sets variable partitioned blocks granularity R, and Block granularity and block count are determined according to R, in the case of fixed storage space size,
The interleaving block of any specification can be supported to handle.And under the less scene of columns in intertexture task, can piecemeal R compared with
Greatly, be conducive to improving bus efficiency.
In the embodiment of the present application for improve " row write row reading/row write capable reading " disposal ability, make per clock cycle " writing " or
Two positions of person's " reading ", can set the TP-RAM of 4 pieces of twoports in interleaver.It is true in the case of TP-RAM using 4 pieces of twoports
Protect during intertexture read/write, TP-RAM reading-writing port will not be clashed, and the data in TP-RAM are needed by particular bin
Formula is deposited, for example, data can be deposited in the way of shown in Fig. 8.This array format can be prevented effectively from read/write conflict.
Wherein, it is interleaved using the TP-RAM of 4 pieces of twoports during the write operation of processing, each clock cycle is writable
2 data, example are respectively written into RAM0, RAM1 address 0 as shown in figure 9, first clock cycle writes x0, x1；At second
The clock cycle writes x2, x3, is respectively written into RAM0, RAM1 address 1.By that analogy, until the write-in of all data is finished.For reading
Operation is similar with write operation, and first clock cycle reads RAM0, RAM2 address 0；Second clock cycle read RAM0,
RAM2 address 6.By that analogy, until all digital independents are finished.
Wherein, the process of write operation and read operation is implemented, can be in the following way：
Note x (k)->X (r, c), wherein r=0,1,2 ... ..., Rmax-1；C=0,1,2 ... ..., Cmax-1.Wherein Rmax
For total line number of interleaver matrix, Cmax is total columns of interleaver matrix, then has following relation：
K=r*Cmax+c.
R=floor (k/Cmax) floor () represent to round downwards
C=k%Cmax % represent mould
It is assumed that wr0, wr1, wr2, wr3 represent the write enable signal of INTL RAM0~3 respectively.Waddr0~waddr3 points
Not Biao Shi INTL RAM0~3 write address.Then：
Wr0=~(r%2) ＆~(c%2)；
Wr1=~(r%2) ＆ (c%2)；
Wr2=(r%2) ＆~(c%2)；
Wr3=(r%2) ＆ (c%2)；
Wherein, MaxAddr is physics RAM actual grade.
Assuming that rd0, rd1, rd2, rd3 represent that the reading of INTL RAM0~3 enables signal respectively.Raddr0~raddr3 points
Not Biao Shi INTL RAM0~3 reading address.Then：
Rd0=~(r%2) ＆~(c%2)；
Rd1=~(r%2) ＆ (c%2)；
Rd2=(r%2) ＆~(c%2)；
Rd3=(r%2) ＆ (c%2)；
It is understood that read-write is enabled, the calculation formula of read/write address is identical.Differ only in order different, write behaviour
Make first to increase c sequence number, be further added by r sequence number；Read operation first increases r sequence number, is further added by c sequence number.
In the embodiment of the present application in a kind of possible implementation, in order to improve piecemeal efficiency, interleaver can be using circulation
Caching mechanism, reserves spatial cache, you can meet any C by B*2 data volume for waiting taskmux*RmuxRanks interweave.
Circular buffer mechanism can be understood as following implementation process：Although it is empty to carry out address space left during the switching of different interleaving block task
Between inadequate one complete interleaving block of storage data, but remaining space can be filled up according to dynamic waterline, the data not inputted by
To back-pressure, inputted when space allows, interleaving block B has been stored as shown in figure 11, in RAM2b0SLC2、Bs1、Bs2And Bs3Remain afterwards
Remaining memory space inadequate is with by interleaving block Bb1SLC0Full storage, in such cases can be by interleaving block Bb1SLC0Part interweave
Block is first stored, and then writes B again when space allows inputb1SLC0Remainder, as shown in figure 11.Likewise, in RAM3
By the way of circulation storage, by Bb2SLC0The write-in of part interleaving block.The embodiment of the present application uses above-mentioned circular buffer mechanism
In the case of, it can be understood as it is to divide obtained N number of piecemeal memory space in the memory space of interleaver and include the 3rd piecemeal
Memory space, the size of the 3rd piecemeal memory space is less than maximum piecemeal storage size, and writes the 3rd piecemeal
Interleaving block in memory space is to the part friendship in the interleaving block obtained after the pending intertexture task progress piecemeal processing
Knit block.It can be avoided using above-mentioned circular buffer mechanism because after piecemeal, the interspersed dispatching efficiency brought of size interleaving block loses.
The implementation of circular buffer mechanism is used in the embodiment of the present application, the logical address calculated is to MaxAddr
Physics RAM actual write address is can obtain after modulus.
Bit-level shown in Fig. 1 and Fig. 2 realizes above-mentioned interleaving treatment method in device application the embodiment of the present application, interweaves
Journey schematic diagram, as shown in figure 12.In Figure 12, for interweave " row write row are read ", after two-dimensional matrix mapping, by x0、x1、
x2、……、x15... order write interleaver memory successively.Then according to x0、x12、x24、x36、……、x1、x13、……
Order from interleaver memory read.For deinterleaving " row write capable reading ", after two-dimensional matrix mapping, according to x0、x12、x24、
x36、……、x1、x13... order write deinterleaving memory successively.Then x is pressed0、x1、x2、……、x15... it is suitable
Sequence is read from memory is deinterleaved.
In another embodiment of the application, when needing to carry out layered mapping for multilayer code word, layer can be equivalent to interweave
Matrix column number, i.e., by the columns of interleaver matrix be equivalent to the pending intertexture task correspondence interleaver matrix columns with to described
Interleaver matrix carries out the product of the number of plies of layer mapping, and is interleaved processing using the above-mentioned interleaving treatment mode being related to, and realizes
Complete to complete layered mapping process while ranks interweave.The same of ranks intertexture is completed for example, can realize in the following way
When complete layered mapping process：
Assuming that the number of plies is Lmux, the columns of interleaver matrix is Cmux, then it is equivalent after the columns of interleaver matrix be expressed as Ceq=
Lmux*Cmux.When being sequentially written in by " OK ", 0 layer 0 of row, 0 layer 1 of row, 0 layer 2 of row, 0 layer 3 of row, 1 layer 0 of row, 1 layer 1 of row, 1 layer 2 of row and row
1 layer 3 ... of data are equivalent to row 0,1,2,3,5,6,7,8 ... and write together.When being sequentially read by " row ", first by interleaving block
The interior all data read-outs of row 0, then by the data read-out of row 1, then by the data read-out of row 2, then by the data read-out of row 3, then read row 4
Layered mapping is completed while interweaving.Implementation process is as shown in figure 13.
When the circular buffer mechanism being related to using above-described embodiment is interleaved processing, the data array of caching is adapted to
Property change, such as exemplified by two layers, the arrangement mode of data is as shown in figure 14.Also, calculate OPADD skew when, it is necessary to
Increase the cheap of interlayer, implement process as follows：
1) initial address cw_o_base is exported according to code word, each Sym output initial address can be calculated：
Sym_o_base=cw_o_base+Rmux*sym_idx*data_width*lay_num
2) output offset address is calculated according to the RE sequence numbers of data in current interleaving block：
Sym_o_offset=(re_idx+Rmux*lay_idx)*data_width
3) layer granularity output data is pressed to DDR1 by Sym in each interleaving block, the initial address exported every time is：
Sym_o_addr=sym_o_base+sym_o_offset
4) data length exported every time is R data_width, altogether Cmux* it is in DDR1 after N*lay_num output
Obtain the data after whole codeword interleave (wherein N be interleaving block number, when last interleaving block remaining data amount is less than R,
Exported by actual size).
In another embodiment of the application, for the scene for the bypass that interweaves in LTE protocol, it will can interweave each after bypassing
Row, are equivalent to a LmuxThe small task of row, then it is equivalent after interleaver matrix midrange Ceq=Lmux, number of tasks T=Cmux, piecemeal
Number is Cmux*Mmux, the interleaving treatment mode being then related to according to above-described embodiment is interleaved processing procedure, may be implemented in intertexture
Layered mapping is completed while bypass.Realize that the processing procedure that layered mapping is completed while interweaving bypass is as shown in figure 15, figure
In 15, the data of each column by when " OK " being sequentially written in, 0 layer 0 of row, 0 layer 1 of row, 0 layer 2 of row, the data of 0 layer 3 of row be equivalent to row 0,1,
2nd, 3 write-ins.When being sequentially read by " row ", first by all data read-outs of row 0 in interleaving block, then by the data read-out of row 1, then will
The data read-out of row 2, then by the data read-out of row 3.After the operation for completing a row, next column operation is carried out according to identical process, i.e.,
Layered mapping is completed while bypass is interweaved.
The interleaving treatment method that the embodiment of the present application is provided, according to intertexture required by task storage size by interleaver
Memory space is divided into multiple piecemeal memory spaces, and the multiple interleaving blocks of parallel processing are corresponding in multiple piecemeal memory spaces hands over
Task is knitted, independent mutually between each interleaving block during read-write is interleaved, realization is read in units of interleaving block
Operation or write operation, with the prior art, it is necessary to by whole interleaver matrix be unit be written and read operation, can reduce shared by
The size of Laden Balance, reduces intertexture cost.And the size flexibly configurable of interleaving block, in the feelings of fixed storage space size
Under condition, the interleaving block of any specification can be supported to handle.
In order to carry out more clearly explaining to the beneficial effect of the application, with the transmission code block of full specification in a LTE
Exemplified by, during 256 phase quadrature amplitude modulations (Quadrature Amplitude Modulation, QAM), code block channel interleaving
Data volume is 3300RE*64Sym*4Lay*64Bit, then uses the above-mentioned interleaving treatment mode being related to of the embodiment of the present application, it is only necessary to
2048RE*64Bit*2Buffer is that stream treatment can be achieved.Memory capacity, processing delay needed for prior art and the application,
Handover delay and startup time delay contrast are as shown in following table table 2：
Table 2
It can be seen from above-mentioned table 2 the application can reduce memory capacity needed for interleaving procedure, processing delay,
Handover delay and startup time delay.
The interleaving treatment method provided based on above-described embodiment, the embodiment of the present application also provides a kind of interleaving treatment device.
It is understood that interleaving treatment device is in order to realize above-mentioned functions, it comprises perform the corresponding hardware configuration of each function
And/or software module.The unit and algorithm steps of each example described with reference to embodiment disclosed herein, the application are real
Applying example can be realized with the combining form of hardware or hardware and computer software.Some function is actually with hardware or computer
The mode of software-driven hardware is performed, depending on the application-specific and design constraint of technical scheme.People in the art
Member can realize described function to each specific application using different methods, but it is this realize it is not considered that
Beyond the scope of the technical scheme of the embodiment of the present application.
The embodiment of the present application can carry out the division of functional unit, example according to above method example to interleaving treatment device
Such as, each function can be corresponded to and divides each functional unit, two or more functions can also be integrated at one
Manage in unit.Above-mentioned integrated unit can both be realized in the form of hardware, it would however also be possible to employ the form of SFU software functional unit
Realize.It should be noted that being schematical to the division of unit in the embodiment of the present application, only a kind of logic function is drawn
Point, there can be other dividing mode when actually realizing.
In the case of using integrated unit, Figure 16 shows a kind of structural representation of interleaving treatment device, refers to
Shown in Figure 16.Interleaving treatment device 100 includes acquiring unit 101, processing unit 102 and interleave unit 103.Acquiring unit 101,
For obtaining pending intertexture task.Processing unit 102, locates for waiting of determining that interleaver obtains to the acquiring unit 101
Reason intertexture task is interleaved the memory space needed for processing, according to the pending intertexture required by task memory space and friendship
The maximum piecemeal memory space of device is knitted, the memory space of the interleaver N number of piecemeal memory space is divided into, the N is just
Integer, wherein, the size of each piecemeal memory space, which is respectively less than, in N number of piecemeal memory space is equal to maximum piecemeal memory space
Size.Interleave unit 103, the pending intertexture task for the acquiring unit 101 to be obtained is divided at least one intertexture
Block, and in units of interleaving block, divided in the processing unit 102 in obtained N number of piecemeal memory space and write interleaving block.
In a kind of possible embodiment, if pending intertexture required by task memory space is less than or equal to the maximum piecemeal
Memory space, then it is that the pending intertexture required by task memory space is big that processing unit 102, which is divided comprising storage size,
N number of piecemeal memory space of the first small piecemeal memory space.The interleave unit 103, is divided in the processing unit 102
The write-in pending intertexture task in the first piecemeal memory space arrived.
In alternatively possible embodiment, if pending intertexture required by task memory space is more than the maximum piecemeal
Memory space, then it is the size of the maximum piecemeal memory space that the division of processing unit 102, which obtains including storage size,
N number of piecemeal memory space of at least one the second piecemeal memory space.The interleave unit 103 is in 102 strokes of the processing unit
The friendship to being obtained after the pending intertexture task progress piecemeal processing is write in the second piecemeal memory space got
Knit block.
In another possible embodiment, the 3rd piecemeal memory space is also included in N number of piecemeal memory space, and
Write after the interleaving block in the 3rd piecemeal memory space carries out piecemeal processing to the pending intertexture task and obtain
Part interleaving block in interleaving block.
In another possible embodiment, if pending intertexture required by task memory space is more than the maximum piecemeal
Memory space, then 103 pairs of the interleave unit pending intertexture task progress piecemeal processing obtains the interleaver matrix in interleaving block
Line number for maximum piecemeal memory space interleaver matrix columns corresponding with the pending intertexture task business；Treated to described
It is the pending intertexture task correspondence that processing intertexture task, which carries out piecemeal and handles the columns of the interleaver matrix obtained in interleaving block,
Interleaver matrix columns.
In another possible embodiment, the interleaver matrix in the interleaving block is carried out to the pending intertexture task
The columns of interleaver matrix in the obtained interleaving block of piecemeal processing for the pending intertexture task correspondence interleaver matrix columns with
The product of the number of plies of layer mapping is carried out to the interleaver matrix.
When being realized using example, in hardware, acquiring unit 101 and processing unit 102 can be mapping circuit, interleave unit
103 can be read/write circuit.When acquiring unit and processing unit are mapping circuits, when interleave unit is read/write circuit, at intertexture
Reason device can be the interleaver shown in Figure 17.
Figure 17 shows another structural representation for the interleaving treatment device that the embodiment of the present application is provided.In Figure 17, interweave
Processing unit can be interleaver 1000, and the interleaver 1000 includes mapping circuit 1001, read/write circuit 1002 and interweaved to deposit
Reservoir 1003.
Wherein, mapping circuit 1001 is used to obtain to treat intertexture task, will treat that interleaving data carries out two to treating in intertexture task
Dimension sequence number mapping obtains interleaver matrix so that treat each data in interleaving data and an element pair in interleaver matrix
Should.And the memory space that interleaver is interleaved to the pending intertexture task needed for processing is determined, interweave according to pending
The maximum piecemeal memory space of required by task memory space and interleaver memory 1003, by depositing for the interleaver memory 1003
Storage space is divided into N number of piecemeal memory space, and the N is positive integer, wherein, each piecemeal storage in N number of piecemeal memory space
The size in space is respectively less than the size for being equal to maximum piecemeal memory space.Read/write circuit, for by the pending intertexture task
At least one interleaving block is divided into, and in units of interleaving block, interleaving block is write in N number of piecemeal memory space.Interweave
Memory 1003 is memory, and for the data storage during intertexture, it generally comprises one or more RAM.
Wherein, mapping circuit 1001 and read/write circuit 1002 possess in the interleaving treatment method that above-described embodiment is related to
Corresponding function, concrete function implementation process see the associated description of above-described embodiment, will not be repeated here.
In the embodiment of the present application, interleaving treatment device 100 and interleaver 1000 possess what is be related in above method embodiment
Interleaver is interleaved the function of processing, not local in detail enough for description of the embodiment of the present invention, see above-described embodiment
Associated description, the embodiment of the present application will not be repeated here.
Based on above-described embodiment, the embodiment of the present application also provides a kind of computer media or computer program product, the meter
Calculation machine medium or computer program product are used to saving as above-mentioned interleaving treatment device and the computer software used in interleaver
Instruction, it includes the program for being used for performing the interleaving treatment method involved by above-described embodiment.
It should be understood by those skilled in the art that, the embodiment of the present application can be provided as method, system or computer program production
Product.Therefore, in terms of the embodiment of the present application can be using complete hardware embodiment, complete software embodiment or combination software and hardware
Embodiment form.Moreover, the embodiment of the present application can be used wherein includes computer available programs generation one or more
The meter implemented in the computer-usable storage medium (including but is not limited to magnetic disk storage, CD-ROM, optical memory etc.) of code
The form of calculation machine program product.
The embodiment of the present application is with reference to the method, equipment (system) and computer program product according to the embodiment of the present application
Flow chart and/or block diagram describe.It should be understood that can be in computer program instructions implementation process figure and/or block diagram
Each flow and/or the flow in square frame and flow chart and/or block diagram and/or the combination of square frame.These calculating can be provided
Processing of the machine programmed instruction to all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing devices
Device is to produce a machine so that the instruction for passing through computer or the computing device of other programmable data processing devices is produced
For realizing the function of being specified in one flow of flow chart or multiple flows and/or one square frame of block diagram or multiple square frames
Device.
These computer program instructions, which may be alternatively stored in, can guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works so that the instruction being stored in the computer-readable memory, which is produced, to be included referring to
Make the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one square frame of block diagram or
The function of being specified in multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing devices so that in meter
Series of operation steps is performed on calculation machine or other programmable devices to produce computer implemented processing, thus in computer or
The instruction performed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in individual square frame or multiple square frames.
Obviously, those skilled in the art can carry out various changes and modification without departing from this Shen to the embodiment of the present application
Spirit and scope please.So, if these modifications and variations of the embodiment of the present application belong to the application claim and its waited
Within the scope of technology, then the application is also intended to comprising including these changes and modification.
Claims (12)
1. a kind of interleaving treatment method, it is characterised in that methods described includes：
Pending intertexture task is obtained, and determines the storage that interleaver is interleaved to the pending intertexture task needed for processing
Space；
According to pending intertexture required by task memory space and the maximum piecemeal memory space of interleaver, by the interleaver
Memory space is divided into N number of piecemeal memory space, and the N is positive integer, wherein, each piecemeal is deposited in N number of piecemeal memory space
The size for storing up space is respectively less than the size for being equal to maximum piecemeal memory space；
The pending intertexture task is divided at least one interleaving block, and in units of interleaving block, deposited in N number of piecemeal
Store up and interleaving block is write in space.
2. the method as described in claim 1, it is characterised in that if pending intertexture required by task memory space is less than or equal to institute
Maximum piecemeal memory space is stated, then it is the pending intertexture times that N number of piecemeal memory space, which includes storage size,
Interleaving block in first piecemeal memory space of storage size needed for business, and write-in the first piecemeal memory space is institute
State pending intertexture task.
3. method as claimed in claim 1 or 2, it is characterised in that if pending intertexture required by task memory space is more than
The maximum piecemeal memory space, then it is that the maximum piecemeal is deposited that N number of piecemeal memory space, which includes storage size,
At least one second piecemeal memory space of the size in space is stored up, and the interleaving block write in the second piecemeal memory space is
The interleaving block for the pending intertexture task obtain after piecemeal processing.
4. the method as described in any one of claims 1 to 3, it is characterised in that also include the in N number of piecemeal memory space
Interleaving block in three piecemeal memory spaces, and write-in the 3rd piecemeal memory space is that the pending intertexture task is carried out
Part interleaving block in the interleaving block obtained after piecemeal processing.
5. the method as described in any one of Claims 1-4, it is characterised in that if pending intertexture required by task storage is empty
Between be more than the maximum piecemeal memory space, then
The line number that the interleaver matrix in the interleaving block that piecemeal processing is obtained is carried out to the pending intertexture task is the maximum
The business of piecemeal memory space interleaver matrix columns corresponding with the pending intertexture task；
The columns that the interleaver matrix in the interleaving block that piecemeal processing is obtained is carried out to the pending intertexture task is waited to locate to be described
Manage intertexture task correspondence interleaver matrix columns.
6. the method as described in any one of claim 1 to 5, it is characterised in that the interleaver matrix in the interleaving block is to described
The columns that pending intertexture task carries out the interleaver matrix in the interleaving block that piecemeal processing is obtained is the pending intertexture task
The product of the number of plies of the correspondence interleaver matrix columns with carrying out layer mapping to the interleaver matrix.
7. a kind of interleaving treatment device, it is characterised in that including：
Acquiring unit, for obtaining pending intertexture task；
Processing unit, for determining that the pending intertexture task that interleaver is obtained to the acquiring unit is interleaved needed for processing
Memory space, will according to the maximum piecemeal memory space of pending the intertexture required by task memory space and interleaver
The memory space of the interleaver is divided into N number of piecemeal memory space, and the N is positive integer, wherein, N number of piecemeal memory space
In the size of each piecemeal memory space be respectively less than the size for being equal to maximum piecemeal memory space；
Interleave unit, the pending intertexture task for the acquiring unit to be obtained is divided at least one interleaving block, and with
Interleaving block is unit, is divided in the processing unit in obtained N number of piecemeal memory space and writes interleaving block.
8. device as claimed in claim 7, it is characterised in that the processing unit is in the following way according to described pending
The maximum piecemeal memory space of intertexture required by task memory space and interleaver, the memory space of the interleaver is divided into
N number of piecemeal memory space：
If pending intertexture required by task memory space is less than or equal to the maximum piecemeal memory space, divide empty comprising storage
Between size it is empty for N number of piecemeal storage of the first piecemeal memory space of the pending intertexture required by task storage size
Between；
The interleave unit, in the following way in units of interleaving block, writes in N number of piecemeal memory space and interweaves
Block：
Divided in the processing unit in obtained the first piecemeal memory space and write the pending intertexture task.
9. device as claimed in claim 7 or 8, it is characterised in that the processing unit is treated according to described in the following way
The maximum piecemeal memory space of intertexture required by task memory space and interleaver is handled, the memory space of the interleaver is drawn
It is divided into N number of piecemeal memory space：
If pending intertexture required by task memory space is more than the maximum piecemeal memory space, division obtains including storage
Space size is empty for N number of piecemeal storage of at least one the second piecemeal memory space of the size of the maximum piecemeal memory space
Between；
In units of interleaving block, interleaving block is write in N number of piecemeal memory space in the following way for the interleave unit：
Divided in the processing unit and write to enter the pending intertexture task in obtained the second piecemeal memory space
The interleaving block obtained after the processing of row piecemeal.
10. the device as described in any one of claim 7 to 9, it is characterised in that also include in N number of piecemeal memory space
Interleaving block in 3rd piecemeal memory space, and write-in the 3rd piecemeal memory space is that the pending intertexture task is entered
Part interleaving block in the interleaving block obtained after the processing of row piecemeal.
11. the device as described in any one of claim 7 to 10, it is characterised in that the interleave unit in the following way will
The pending intertexture task is divided at least one interleaving block：
If pending intertexture required by task memory space is more than the maximum piecemeal memory space,
The line number that the interleaver matrix in the interleaving block that piecemeal processing is obtained is carried out to the pending intertexture task is the maximum
The business of piecemeal memory space interleaver matrix columns corresponding with the pending intertexture task；
The columns that the interleaver matrix in the interleaving block that piecemeal processing is obtained is carried out to the pending intertexture task is waited to locate to be described
Manage intertexture task correspondence interleaver matrix columns.
12. the device as described in any one of claim 7 to 11, it is characterised in that the interleaver matrix in the interleaving block is to institute
The columns for stating the interleaver matrix in the interleaving block that pending intertexture task progress piecemeal processing is obtained is appointed for the pending intertexture
The product of the number of plies of the business correspondence interleaver matrix columns with carrying out layer mapping to the interleaver matrix.
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| CN105490776A (en) * | 2015-11-26 | 2016-04-13 | 华为技术有限公司 | Interleaving method and interleaver |
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| WO2020199798A1 (en) * | 2019-03-29 | 2020-10-08 | 中兴通讯股份有限公司 | Resource scheduling method and apparatus, and computer-readable storage medium |
| CN114741329A (en) * | 2022-06-09 | 2022-07-12 | 芯动微电子科技(珠海)有限公司 | Multi-granularity combined memory data interleaving method and interleaving module |
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