CN101060338A - A convolutional code rate matching method and device - Google Patents
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Abstract
The disclosed convolution code rate matching method comprises: the convolution coder codes the message bit for output, and divides the message bit into some sub-blocks according to code rate and coding polynomial; the interlace device treats the sub block with fixed interlace parameter M; then, equal-interval mixing the interlaced sub-blocks to generate bit group Q, continual taking out (Nc) bits from a special position in the group Q as the output bit for rate matching, and back to the beginning of Q if achieving end of Q. This invention reduces the matching complexity efficiently.
Description
Technical field
The present invention relates to digital communication system, the method and the device of convolutional code rate coupling when particularly relating to the chnnel coding of digital communication system.
Background technology
As shown in Figure 1, the transmitting terminal of digital communication system generally includes parts such as information source, source encoder, channel encoder and modulator, receiving terminal generally includes demodulator, channel decoder, source decoder and the stay of two nights etc., and transmitting terminal is sent to receiving terminal by channel with signal.Described channel encoder is used for introducing redundant information to information bit according to certain rule, so that the channel decoder of receiving terminal can be corrected the error code that information is taken place to a certain extent when channel.
Channel encoder is when encoding, and the encoding block that usually information bit is divided into certain-length is encoded, and the big more error-correcting performance of encoding block is good more usually, but cost is the increase of coding and decoding complexity and deciphers the increase of time of delay.So when the design channel encoder, must do a restriction to the size of maximum encoding block.Usually the output block (be called burst below, normally send into the data block of physical layer from high level in wireless communication protocol stack) of source encoder is bigger, must divide according to maximum coded block size when entering channel encoder.The size of burst satisfies the certain particle requirement usually, and the size of burst that system distributes is the integral multiple of Physical Resource Block beared information bit length normally.
In code block segmentation, will allow the message length of each encoding block all be the integral multiple of Physical Resource Block beared information bit length, each encoding block will be mapped in the integer complete Physical Resource Block at last.But the size of burst is not the integral multiple of maximum coded block size usually.At this moment, we make the minimum code piece of cutting apart generation be unlikely to too little usually to burst segmentation being become encoding block certain rule is set, because too small encoding block performance is poor, will have a strong impact on the performance of whole burst.
In common digital communication system, in the time of the design coded modulation scheme, the modulation system (as QPSK, 16QAM and 64QAM etc.) and different sign indicating numbers (as convolution code, Turbo code etc.) of different rank are set usually, every kind of sign indicating number has different code check (Rate, as 1/2,2/3,3/4 and 5/6 etc.) usually.In the time of system call, a kind of specific code modulation mode is arranged in each burst according to channel quality and business demand.In order to obtain the effect of better link adaptation, every kind of sign indicating number preferably can be accomplished smaller granularity in the conversion code check.If just with the bigger several code checks of spacing, as 1/2,2/3,3/4 and 5/6 etc., the granularity of its link adaptation is more coarse so.
Convolution code and Turbo code are two kinds of error correcting codes commonly used in the digital communication system, and these two kinds of error correcting codes are simultaneously selected in the digital communication system of being everlasting.Convolution code is fairly simple, performance is than Turbo code difference, but the performance advantage of Turbo code just can better embody when code length is long usually, so system uses convolution code in short code long (tens to a hundreds of information bit) usually, when middle long code long (hundreds of is to several thousand information bits), use Turbo code.Described code length is meant the information bit length K.
For convolution code and Turbo code commonly used in the digital communication system, it is by the female sign indicating number that hangs down code check is deleted the coding that surplus (Puncture) obtains higher code check that its code check improves, we also reduce this method rate-matched (Rate Matching, or RM).The purpose of rate-matched be the code check that improves or reduce the female sign indicating number of channel encoder output make rate matchers output bit number can and the Physical Resource Block that distributed of the system bit number that can carry be consistent.Described rate matchers is a standard module of the prior art, is usually located at the back of channel encoder, belongs to the part of chnnel coding chain.
Convolution code commonly used in the digital communication system is (Zero Termination) convolution code that makes zero of stinging tail (Tail-biting) convolution code or constraint length 9 of constraint length 7, code check often is 1/2 or 1/3, wherein the sign indicating number of 1/2 code check is by two generator polynomial definition, the sign indicating number of 1/3 code check is by three generator polynomial definition, because all be nonsystematic code, there is not system bits, the sign indicating number of 1/2 code check has the bit stream of two parity checks after encode, and the bit stream of three parity checks is arranged after yard having encoded of 1/3 code check.Constraint length is that the independent attribute and the message length of convolution code is irrelevant.
Channel encoder described in the communication network schematic diagram shown in Figure 1 is the channel encoder of a broad sense, may also comprise some relevant concrete modules of chnnel coding processing.When specifically chnnel coding being handled, the encoder of the following stated is the encoder of narrow sense among the present invention, only refers to channel or information are carried out apparatus for encoding.In the prior art, adopt convolution code circular buffering speed matching algorithm to carry out the code rate coupling during chnnel coding usually.
The circular buffering speed matching algorithm is a kind of speed matching algorithm very flexibly, can be used for the rate-matched of convolution code usually.But in the circular buffering speed matching algorithm, the performance and the implementation complexity of value and final rate-matched that carries out the interleave parameter M of sub-block interleaving all has relation.The M value influences the uniformity of sub-block interleaving, and the M value is big more usually, and sub-block interleaving is just even more, and the convolution code performance is just good more after the rate-matched.When realizing above-mentioned sub-block interleaver with the hardware circuit high-speed parallel when, the sub-block interleaver that value is M needs 2 usually
MBlock storage (RAM) is so the big more implementation complexity of M is also high more.When in system, existing various bags long, must come the design circuit resource according to the long corresponding maximum M value of all bags during the design hardware circuit, in system's actual motion, come configuration circuit according to the long corresponding M value of actual packet.So not only increased circuit complexity, and be to consume very much hardware resource when the M value is bigger.
If fixedly the M value then can be simplified circuit design and resource consumption greatly.By further discovering, when the value of M during greater than certain thresholding, the value of M to rate-matched after the performance impact of convolution code little, the M value is feasible so use fixedly.
The present invention improves the method for the rate-matched of channel encoder.
Summary of the invention
Technical problem to be solved by this invention is, a kind of method and device of rate-matched efficiently are provided for the communication system of using convolution code, solve existing speed matching method and device because of the high problem of related implementation complexity with code length, realize the convolutional code rate coupling simply efficiently.
The invention provides a kind of method of convolutional code rate coupling, in the communication system of using convolution code, carry out rate-matched, comprise the steps:
(a) convolution coder is input information bits coding back output, is separated into the plurality of sub piece according to the code check information bit of exporting of will encode according to different coding multinomials;
(b) interleaver adopts BRO to interweave algorithm to each different different sub-block interleaving of sub-piece execution;
The equally spaced mixed insertion of sub-piece that (c) will interweave later produces bit group Q together;
(d) certain location begins to take out continuously the output bit of Nc bit as rate-matched from bit group Q, and if in this process, arrived the end of Q rollback to the starting end of Q, Nc is the output bit length.
Interleaver adopts BRO to interweave algorithm when each different sub-piece is carried out different sub-block interleavings in the described step (b), and sub-block interleaving parameter M is a fixed value.Preferably, described M value is fixed as 5.Described M value can also be fixed as any in 4 or 5 or 6 or 7 or 8.
Described step (a) further can be divided into:
Convolution coder with input information bits [A (1), A (2) ..., A (K)] and the output of coding back [B (1), B (2),, B (N*K)], will [B (1), B (2) ... B (N*K)] be separated into a plurality of sub-pieces according to different coding multinomials, for the convolution code of 1/N code check N sub-piece P1 arranged, P2 ..., PN, Pi=[Pi (1) wherein, Pi (2) ..., Pi (K)], i=1 ..., N, wherein, K is an input information bits length, and Nc is the output bit length, and female sign indicating number code check is 1/N, and N is the integer greater than 1.
Described step (b) further can be divided into:
Each different sub-piece is carried out different sub-block interleavings, antithetical phrase piece P1 for the convolution code of 1/N code check, P2 ... PN carries out the sub-piece P1 ' after sub-block interleaving generation interweaves respectively, P2 ' ..., PN ', wherein Pi '=[Pi ' (1), Pi ' (2) ..., Pi ' is (K)], i=1,, N carries out BRO when interweaving, the sub-piece bit that is interleaved writes an array the inside according to the order from 0 to L-1 (for sub-piece bag length), then with i (i=0 ..., L-1) bit after individual interweaving is according to interleaving address AD
iRead from the array the inside,
Wherein, interleaving address AD
iProduce according to following steps:
(b.a) obtain sub-block interleaving parameter M and J, wherein M is a fixed value,
Be last bracket function;
(b.b) variable i and j are initially 0;
(b.c) obtain tentative OPADD:
Wherein, BRO
M(y) expression is carried out an inverted sequence operation to M bit variable y, wherein
Be following bracket function, Δ is the constant relevant with sub-piece, and each sub-piece is got different values usually;
(b.d) if T
j＜L, AD so
i=T
j, then i and j are increased by 1; If do not satisfy T
j＜L then abandons T
j, only j is increased by 1 then;
(b.e) repeating step (b.c) and (b.d) all obtained up to all L interleaving address.
Described step (c) further can be divided into:
The equally spaced mixed insertion of sub-piece that will interweave later produces bit group Q together, promptly produces Q=[P1 ' (1) for the convolution code of 1/N code check, P2 ' (1) ..., PN ' (1), P1 ' (2), P2 ' (2) ..., PN ' (2) ... P1 ' (K), P2 ' (K) ..., PN ' is (K)].
Described step (d) further can be divided into:
From described bit group Q certain location begin to take out continuously Nc bit [C (1), C (2) ..., C (Nc)] as the output bit of rate-matched, if in this process, arrived the end of Q rollback to the starting end of Q.
Based on above-mentioned convolutional code rate matching process, the present invention also provides a kind of device of convolutional code rate coupling, comprise convolution coder, some interleavers, uniformly-spaced bit mixed insertion device, output bit interceptor, described convolution coder links to each other with bit mixed insertion device uniformly-spaced by some interleavers, uniformly-spaced bit mixed insertion device links to each other with output bit interceptor, wherein:
Described convolution coder is used for input information bits coding back output, is separated into the plurality of sub piece according to the code check information bit of exporting of will encode according to different coding multinomials, sends into interleaver;
Described interleaver adopts BRO to interweave algorithm to each different different sub-block interleaving of sub-piece execution, and the sub-block interleaving parameter M when interweaving is a fixed value;
Described uniformly-spaced bit mixed insertion device produces bit group Q with the equally spaced mixed insertion of sub-piece that interweaves later that receives together, delivers to output bit interceptor;
Described output bit interceptor, a certain location begins to take out continuously the output bit of Nc bit as rate-matched from Q, if in this process, arrived the end of Q rollback to the starting end of Q, Nc is the output bit length.
Described M value is fixed as any value in 4 or 5 or 6 or 7 or 8.Preferably, described M value is fixed as 5.
Main improvement of the present invention is that the M in the existing speed matching algorithm is set to and the irrelevant fixed value of code length.Grow (information bit length) for what convolution code was used always from tens to hundreds of bit bag, use fixing M that convolution code circular buffering rate-matched performance and good one of complexity are traded off, can effectively reduce the implementation complexity of convolutional code rate coupling especially.
Description of drawings
Fig. 1 is the digital communication system structural representation;
Fig. 2 is the structure of convolution code circular buffering rate-matched;
Fig. 3 is the structure chart of convolution code circular buffering rate-matched device of the present invention.
Embodiment
For ease of profound understanding technology contents of the present invention, the present invention is described in further detail below in conjunction with accompanying drawing and specific implementation method.
Main improvement of the present invention is that the M in the existing speed matching algorithm is set to and the irrelevant fixed value of code length, and a reasonable preferred value is 5, and simultaneously, M also can be fixed as any in 4,5,6,7 and 8, but irrelevant with code length.Trading off of performance that different M value representatives are different and implementation complexity, when using this rate matchers in a communication system or standard when, M is the fixed value of an appointment.
Serve as that the process that female sign indicating number carries out rate-matched is that example describes with 1/3 rate convolutional code below, as shown in Figure 2.The convolution code structural similarity of other code checks uses this algorithm can generate the convolution code of various code checks flexibly.
Suppose that K is an input information bits length, Nc is the output bit length, and female sign indicating number code check is 1/N, and convolution code circular buffering speed matching algorithm may further comprise the steps:
(A) convolution coder with input information bits [A (1), A (2) ..., A (K)] and coding back output [B (1), B (2) ..., B (N*K)], with [B (1), B (2) ..., B (N*K)] and be separated into a plurality of sub-pieces (Subblock) according to different coding multinomials, for the convolution code of 1/N code check N sub-piece P1 arranged, P2 ..., PN, wherein Pi=[Pi (1), Pi (2) ..., Pi (K)], i=1 ..., N.
For the present embodiment, N=3 then has 3 sub-piece P0, P1 and P2.
(B) each different sub-piece is carried out different sub-block interleavings, antithetical phrase piece P1 for the convolution code of 1/N code check, P2,, PN carries out the sub-piece P1 ' after sub-block interleaving generation interweaves, P2 ' respectively,, PN ', wherein Pi '=[Pi ' (1), Pi ' (2),, Pi ' is (K)], i=1,, N.
For the present embodiment, antithetical phrase piece P0, P1 and P2 carry out sub-block interleaving respectively and produce sub-piece P0 ', P1 ' and P2 '.
The said sub-block interleaving of above-mentioned steps (B) adopts BRO (Bit-Reversal Operaion) algorithm that interweaves, and comprises the steps:
The sub-piece bit that is interleaved writes array the inside according to the order from 0 to L-1 (L is that sub-piece bag is long, in the present embodiment L=K), then with i (i=0 ..., L-1) bit after individual interweaving is according to interleaving address AD
iRead from the array the inside.Interleaving address AD
iProduce according to following steps:
(b.a) obtain sub-block interleaving parameter M and J, M is fixed as in 4,5,6,7 and 8 one in the present embodiment, preferably can get M=5,
Wherein
Be last bracket function;
(b.b) variable i and j are initially 0;
(b.c) obtain tentative OPADD:
0≤Δ≤2
M-1
BRO wherein
M(y) expression is carried out an inverted sequence operation to M bit variable y, wherein
Be following bracket function, Δ is the constant relevant with sub-piece, and each sub-piece is got different values usually.In the present embodiment, for P0, Δ=0; For P1,
For P2,
Wherein
Be last bracket function;
(b.d) if T
j＜L, AD so
i=T
j, then i and j are increased by 1; If do not satisfy T
j＜L then abandons T
j, only j is increased by 1 then;
(b.e) repeating step (b.c) and (b.d) all obtained up to all L interleaving address.
The equally spaced mixed insertion of sub-piece that (C) will interweave later produces bit group Q together, promptly produces Q=[P1 ' (1) for the convolution code of 1/N code check, P2 ' (1) ..., PN ' (1), P1 ' (2), P2 ' (2) ..., PN ' (2) ... P1 ' (K), P2 ' (K) ..., PN ' is (K)].
Q=[P1 ' (1) for the present embodiment, P2 ' (1), P3 ' (1), P1 ' (2), P2 ' (2), P3 ' (2) ..., P1 ' (K), P2 ' (K), P3 ' is (K)].
(D) from bit group Q certain location begin to take out continuously Nc bit [C (1), C (2) ..., C (Nc)] as the output bit of rate-matched, if in this process, arrived the end of Q rollback to the starting end of Q.
In the above-mentioned steps (D), automatically return starting end if arrive end, for the selection of intercepting starting position, under non-H-ARQ (Hybrid-Automatic Repeat Request) and H-ARQ ChaseCombination condition, original position is chosen in the original position of Q usually; Under H-ARQ IR (Incremental Redundancy) condition, the selection of intercepting starting position makes the bit from the Q intercepting of each transmission keep quadrature usually, and as shown in Figure 2, wherein each bit that retransmits is called a redundancy versions.
So just finished the process of circular buffering rate-matched.
Based on the method for above-mentioned a kind of convolutional code rate coupling, as shown in Figure 3, shown a kind of device of realizing the convolutional code rate coupling, the device of this convolutional code rate coupling comprises:
Convolution coder, some interleavers, uniformly-spaced bit mixed insertion device, output bit interceptor, described convolution coder links to each other with bit mixed insertion device uniformly-spaced by some interleavers, uniformly-spaced bit mixed insertion device links to each other with output bit interceptor, setting K is input information bits length, Nc is the output bit length, female sign indicating number code check is 1/N, wherein:
Described convolution coder, be used for input information bits [A (1), A (2) ... A (K)] output of coding back [B (1), B (2) ..., B (N*K)], will [B (1), B (2) ..., B (N*K)] and be separated into a plurality of sub-pieces (Subblock) according to different coding multinomials, convolution code for the 1/N code check has N sub-piece P1, P2 ..., PN, Pi=[Pi (1) wherein, Pi (2) ..., Pi (K)], i=1 ..., N, and the plurality of sub piece that separates of will encoding is sent in the interleaver.
Described some interleavers are carried out different sub-block interleavings, antithetical phrase piece P1 for the convolution code of 1/N code check to each different sub-piece, P2 ..., PN carries out the sub-piece P1 ' after sub-block interleaving generation interweaves respectively, P2 ' ..., PN ', wherein Pi '=[Pi ' (1), Pi ' (2) ... Pi ' (K)], i=1 ..., N;
Interleaver uses BRO algorithm that interweaves to each sub-piece, and the sub-piece bit that be interleaved writes an array the inside according to the order from 0 to L-1 (L is that sub-piece bag is long), then with i (i=0 ..., L-1) bit after individual interweaving is according to interleaving address AD
iRead from the array the inside.Interleaving address AD
iProduce according to following steps:
(b.a) obtain sub-block interleaving parameter M and J, wherein M is a fixed value, and especially, M can be fixed as in 4,5,6,7 and 8, preferably this M fixedly value can be 5,
(b.b) variable i and j are initially 0;
(b.c) obtain tentative OPADD:
BRO wherein
M(y) expression is carried out an inverted sequence operation to M bit variable y, wherein
Be following bracket function, Δ is the constant relevant with sub-piece, and each sub-piece is got different values usually;
(b.d) if T
j＜L, AD so
i=T
j, then i and j are increased by 1; If do not satisfy T
j＜L then abandons T
j, only j is increased by 1 then;
(b.e) repeating step (b.c) and (b.d) all obtained up to all L interleaving address.
Described uniformly-spaced bit mixed insertion device, the equally spaced mixed insertion of sub-piece that will interweave later produces bit group Q together, promptly produces Q=[P1 ' (1) for the convolution code of 1/N code check, P2 ' (1) ..., PN ' (1), P1 ' (2), P2 ' (2) ... PN ' (2),, P1 ' (K), P2 ' is (K),, PN ' is (K)].
Described output bit interceptor, from bit group Q certain location begin to take out continuously Nc bit [C (1), C (2) ..., C (Nc)] as the output bit of rate-matched, if in this process, arrived the end of Q rollback to the starting end of Q.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of method of convolutional code rate coupling is carried out rate-matched in the communication system of using convolution code, comprises the steps:
(a) convolution coder is input information bits coding back output, is separated into the plurality of sub piece according to the code check information bit of exporting of will encode according to different coding multinomials;
(b) interleaver adopts BRO to interweave algorithm to each different different sub-block interleaving of sub-piece execution;
The equally spaced mixed insertion of sub-piece that (c) will interweave later produces bit group Q together;
(d) certain location begins to take out continuously the output bit of Nc bit as rate-matched from bit group Q, and if in this process, arrived the end of Q rollback to the starting end of Q, Nc is the output bit length.
2, convolutional code rate matching process as claimed in claim 1 is characterized in that, interleaver adopts BRO to interweave algorithm when each different sub-piece is carried out different sub-block interleavings in the described step (b), and sub-block interleaving parameter M is a fixed value.
3, convolutional code rate matching process as claimed in claim 1 is characterized in that, described step (a) further can be divided into:
Convolution coder with input information bits [A (1), A (2) ..., A (K)] and the output of coding back [B (1), B (2),, B (N*K)], will [B (1), B (2) ... B (N*K)] be separated into a plurality of sub-pieces according to different coding multinomials, for the convolution code of 1/N code check N sub-piece P1 arranged, P2 ..., PN, Pi=[Pi (1) wherein, Pi (2) ..., Pi (K)], i=1 ..., N, wherein, K is an input information bits length, and Nc is the output bit length, and female sign indicating number code check is 1/N, and N is the integer greater than 1.
4, convolutional code rate matching process as claimed in claim 3 is characterized in that, described step (b) further can be divided into:
Each different sub-piece is carried out different sub-block interleavings, antithetical phrase piece P1 for the convolution code of 1/N code check, P2 ... PN carries out the sub-piece P1 ' after sub-block interleaving generation interweaves respectively, P2 ' ..., PN ', wherein Pi '=[Pi ' (1), Pi ' (2) ..., Pi ' is (K)], i=1,, N carries out BRO when interweaving, the sub-piece bit that is interleaved writes an array the inside according to the order from 0 to L-1 (L is that sub-piece bag is long), then with i (i=0 ..., L-1) bit after individual interweaving is according to interleaving address AD
iRead from the array the inside,
Wherein, interleaving address AD
iProduce according to following steps:
(b.a) obtain sub-block interleaving parameter M and J, wherein M is a fixed value,
Be last bracket function;
(b.b) variable i and j are initially 0;
(b.c) obtain tentative OPADD:
Wherein, BRO
M(y) expression is carried out an inverted sequence operation to M bit variable y, wherein
Be following bracket function, Δ is the constant relevant with sub-piece, and each sub-piece is got different values usually;
(b.d) if T
j＜L, AD so
i=T
j, then i and j are increased by 1; If do not satisfy T
j＜L then abandons T
j, only j is increased by 1 then;
(b.e) repeating step (b.c) and (b.d) all obtained up to all L interleaving address.
5, convolutional code rate matching process as claimed in claim 4 is characterized in that, described step (c) further can be divided into:
The equally spaced mixed insertion of sub-piece that will interweave later produces bit group Q together, promptly produces Q=[P1 ' (1) for the convolution code of 1/N code check, P2 ' (1) ..., PN ' (1), P1 ' (2), P2 ' (2) ..., PN ' (2) ... P1 ' (K), P2 ' (K) ..., PN ' is (K)].
6, convolutional code rate matching process as claimed in claim 5 is characterized in that, described step (d) further can be divided into:
From described bit group Q certain location begin to take out continuously Nc bit [C (1), C (2) ..., C (Nc)] as the output bit of rate-matched, if in this process, arrived the end of Q rollback to the starting end of Q.
7, as claim 2 or 4 described convolutional code rate matching process, it is characterized in that described M value is fixed as 5.
8, as claim 2 or 4 described convolutional code rate matching process, it is characterized in that described M value is fixed as any in 4 or 5 or 6 or 7 or 8.
9, based on the device of a kind of convolutional code rate coupling of claim 1, comprise convolution coder, some interleavers, uniformly-spaced bit mixed insertion device, output bit interceptor, described convolution coder links to each other with bit mixed insertion device uniformly-spaced by some interleavers, uniformly-spaced bit mixed insertion device links to each other with output bit interceptor, it is characterized in that:
Described convolution coder is used for input information bits coding back output, is separated into the plurality of sub piece according to the code check information bit of exporting of will encode according to different coding multinomials, sends into interleaver;
Described interleaver adopts BRO to interweave algorithm to each different different sub-block interleaving of sub-piece execution, and the sub-block interleaving parameter M when interweaving is a fixed value;
Described uniformly-spaced bit mixed insertion device produces bit group Q with the equally spaced mixed insertion of sub-piece that interweaves later that receives together, delivers to output bit interceptor;
Described output bit interceptor, a certain location begins to take out continuously the output bit of Nc bit as rate-matched from Q, if in this process, arrived the end of Q rollback to the starting end of Q, Nc is the output bit length.
10, convolutional code rate matching process as claimed in claim 9 is characterized in that, described M value is fixed as any value in 4 or 5 or 6 or 7 or 8.
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| CN108476550A (en) * | 2015-11-09 | 2018-08-31 | 纽瑞科姆有限公司 | The communication of the specific control information of user in wireless network |
| CN109150420A (en) * | 2017-06-19 | 2019-01-04 | 华为技术有限公司 | Method, apparatus, communication equipment and the communication system of information processing |
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