CN115268246B - Shared array time-to-digital converter based on-chip storage - Google Patents
Shared array time-to-digital converter based on-chip storage Download PDFInfo
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Abstract
The invention discloses a shared array time-to-digital converter based on-chip storage, which comprises a macro pixel circuit with an SRAM unit and a read-write channel, a time sequence control circuit, a synchronous signal circuit and a parallel-serial data interface circuit; wherein: the data transmission start mark and the data transmission end mark generated by the time sequence control circuit are connected with the synchronous signal circuit, the data transmission window signal generated by the time sequence control circuit is connected with the parallel-serial data interface circuit, and the output end of the pixel array system of the macro pixel circuit is connected with the parallel-serial data interface circuit; the global signals comprise an enable signal EN, a RESET signal RESET and TDC high-frequency clock signals HCK1 and HCK2 which are connected into each macro pixel of the whole pixel array system through a symmetrical H-Tree distribution network; on the premise of ensuring that effective data and precision are consistent, the on-chip storage technology can relieve the limit of data reading time on the high frame frequency of a reading circuit, and reduce the area and power consumption of the reading circuit.
Description
Technical Field
The invention relates to a shared array time-to-digital converter based on-chip storage, which is particularly applied to a circuit system with the scale of an array enlarged and the data volume increased rapidly, and belongs to the technical field of time-to-digital converter circuit design.
Background
Time-to-Digital Converter (TDC) is widely applied to modern hot fields such as three-dimensional intelligent sensing, autonomous navigation, industrial detection, laser radar, medical detection and the like by virtue of the characteristics of low complexity, wide dynamic range, strong robustness and the like, and higher requirements are provided for the aspects of data transmission speed, power consumption, area and the like of the TDC in various application scenes.
When a large number of effective photon events are triggered, on one hand, most of the pixel units are in a working state, so that larger power consumption is consumed, and on the other hand, large-scale data throughput is realized, corresponding circuit processing units are required to be added, and the contradiction between high-speed transmission and low-power consumption and low-area consumption is avoided, so that the large-scale expansion of the array TDC is limited. Since Static Random-Access Memory (SRAM) has characteristics of high speed and low power consumption, stored data can be constantly maintained as long as power is kept on. Therefore, the design is based on the advantages of SRAM, and the area and the power consumption are considered to be further reduced, so that the shared array time-digital converter based on-chip storage is proposed to obtain the high-speed data transmission capability; wherein the on-chip storage realizes data latching through six transistors only.
Based on the shared array TDC stored on the chip, the method has better performance when dealing with large-scale data transmission, reduces power consumption and area to a certain extent, and has important significance for further expanding the large pixel scale of the array TDC.
Disclosure of Invention
Technical problems: in order to overcome the limitation of massive effective photon events on the large pixel scale, performance and power consumption of the array TDC, the invention provides a shared array time-to-digital converter based on-chip storage.
The technical scheme is as follows: in order to achieve the above object, the present invention provides a shared array time-to-digital converter based on-chip storage, the array time-to-digital converter includes a macro pixel circuit with an SRAM cell and a read-write path, a timing control circuit, a synchronization signal circuit, and a parallel-serial data interface circuit; wherein:
The data transmission start mark and the data transmission end mark generated by the time sequence control circuit are connected with the synchronous signal circuit, the data transmission window signal generated by the time sequence control circuit is connected with the parallel-serial data interface circuit, and the output end of the pixel array system of the macro pixel circuit is connected with the parallel-serial data interface circuit; the global signals comprise an enable signal EN, a RESET signal RESET and TDC high-frequency clock signals HCK1 and HCK2 which are accessed into each macro pixel of the whole pixel array system through a symmetrical H-Tree type distribution network.
The macro pixel circuit is formed by a static random access memory SRAM, a memory write-in and read-out passage, 4*4 pixel units and two-section TDCs together to form one macro pixel in a pixel array; each pixel unit comprises a quenching circuit and a finite state machine; the memory write path comprises an arbitration circuit, an address coding circuit, a data latch circuit and a delay reset circuit; the memory read path includes an accumulator, a modulo 12 counter; the parallel-serial data interface circuit includes a 12-bit shift register and a multiplexer.
And in the macro pixel circuit, in the on-chip storage data writing stage, when a trigger signal is detected in the effective period of an enable signal EN, the two-stage TDC finishes time interval quantization and latching, the finite state machine photon records the echo times, the first reached photon signal is judged and reserved through a memory writing path, and the data is written into the SRAM after the writing clock arrives.
The macro pixel circuit stores data read-out phases on a chip, and the time sequence control circuit traverses addresses of all storage units in the SRAM through controlling the data ports in different time periods and reads out quantized data according to the address sequence; the synchronous signal circuit generates a sign signal corresponding to the output data, ensures the accuracy of data reading, finally completes parallel-to-serial conversion of the data by the shift register, performs time-division multiplexing on the output port by the multiplexer, and serially reads TDC quantized data according to the sequence.
In the macro pixel circuit, after detecting a first photon event, the finite state machine of each pixel sets an address bus A <0> address to 1 after detecting a DTOF signal, so that the change of the A <0> address does not influence the current data writing address; the DTOF signal is generated after a delay reset circuit in a memory writing path judges and processes photon events reserved in an arbitration circuit; the finite state machine characterizes the number of currently detected echoes through a Q1 signal, an arbitration circuit of a memory write-in path keeps photon event information which arrives first, judges that two photon events smaller than 5ns are photon event conflicts, and discards the photon events which arrive after the two photon events collide.
The arbitration circuit of the memory write-in path detects the REQ signal of each pixel, the two REQ signals are compared by the precision Maker module of the arbitration circuit, finally, the photon time signal which arrives first is arbitrated and is input to the DELAY reset circuit to generate the DTOF and DTOF_DELAY signals, and meanwhile, the address coding circuit in the memory write-in path generates the address of the corresponding pixel, and when the data latched by the two-section TDC detects the DTOF_DELAY signal, the data are uniformly accessed into the SRAM.
In the macro pixel circuit, a memory read-out path realizes an address accumulation function through a 5-bit synchronous counter, traverses addresses of all storage units in the SRAM, and completes parallel reading and serial output of data by multiplexing a 12-bit shift register and a multiplexer in a time-sharing way under the coordination of a time sequence control circuit.
In the macro-pixel circuit, the memory readout is specifically: the time sequence control circuit is composed of a counter driven by a data reading clock LCK and timing control logic, and different control signals are enabled in different time periods, so that data are read out uniformly and orderly according to a preset sequence; when the counter counts to a count value corresponding to the timing logic, the timing logic generates a corresponding narrow pulse signal to drive AND reset a corresponding D trigger to form a corresponding time window interval for corresponding data reading AND processing, AND the final result is that the LCK signal is divided into eight sections for enabling processing to obtain an LCK_AND_TPi signal, AND eight memories are controlled in sequence; in the memory readout circuit, when a read signal CLKA generated by a module 12 counter is pulled high, data in a memory is updated to a multiplexer in the parallel-to-serial data interface circuit, another period level SEL generated by the module 12 counter is used for controlling the multiplexer in the parallel-to-serial data interface circuit, after LCK_AND_TPi is detected, the data in the memory is transmitted to a 12-bit shift register in the parallel-to-serial data interface circuit, after transmission is finished, the 12-bit shift register enters a shift mode, AND parallel data is converted into serial data to be output under the driving of a clock.
The synchronous signal circuit mainly provides a mark signal for identifying serial output DATA, and mainly generates three synchronous signals of a WORD signal WORD and a BIT signal BIT corresponding to the output DATA, and combines the DATA output DATA_OUT to facilitate subsequent DATA processing; the correspondence of the BIT signal BIT to the WORD signal WORD depends on the number of BITs of the data to be read.
After the parallel-serial data interface circuit receives the data transmission window signal TPi generated by the time sequence control circuit, the data transmission clock signal LCK_AND_TPi is generated by AND operation of the clock LCK signal, AND the signal is effective in the high level of the pulse width of the corresponding set data transmission window TPi, so that the data on the corresponding path is normally transmitted; the low-frequency clock is shielded outside the high-level pulse width of the data transmission window TPi, and the data transmission is forbidden; the parallel-to-serial data interface circuit completes serial output of data under control of the corresponding LCK_AND_TPi signal.
The beneficial effects are that: compared with the prior art, the shared array time-to-digital converter based on-chip storage has the following technical effects:
1. The invention is applied to TDC array circuits for large-scale data storage and transmission, and aims at finishing the storage and reading operation of quantized data by SRAM, and the data is serially output according to a specific period sequence by time-sharing multiplexing of parallel-serial data interface circuits under the coordination of a time sequence control circuit. Compared with the traditional scheme, the TDC data transmission rate is limited by power consumption, and quantized data is latched in a register formed by twenty-four transistors; in the scheme of the invention, the characteristics of high-speed data transmission capability and low power consumption of the SRAM are combined, and meanwhile, the on-chip storage realizes the latching of quantized data only through six transistors, so that compared with the traditional scheme, the scheme of the invention can greatly reduce the data reading time and the data reading power consumption on the premise of ensuring the consistency of frame frequency and data throughput.
2. The invention is applied to a TDC array circuit for large-scale data storage and transmission, the write-in and read-out paths of the SRAM ensure the establishment time and the holding time of data transmission, and the stored data can be constantly held as long as the SRAM is kept electrified, so that the length of the data storage time is increased to a certain extent, the probability of data leakage loss and insufficient establishment and holding time is reduced, and the reliability and the accuracy of data processing are improved. Meanwhile, the array TDC stored on the chip is assisted by a shared structure, when a multi-photon event occurs, the address of the pixel with the photon event can be autonomously arbitrated and output, the number of the TDCs is reduced, and the data reading power consumption and the area consumption are further reduced.
Drawings
FIG. 1 is a schematic diagram of a shared array time-to-digital converter based on-chip storage according to the present invention; the method comprises the following steps: a read-out synchronous signal generating circuit SYNC, a Timing Control circuit Timing Control, a synchronous signal circuit, a macro pixel circuit and a parallel-serial data interface circuit;
FIG. 2 is a diagram of a write channel structure and timing diagram for a macro-pixel;
FIG. 3 is a diagram of a read-out path structure in a macropixel;
FIG. 4 is a Timing Control circuit Timing Control block diagram;
FIG. 5 is a diagram showing a structure of a synchronization signal circuit SYNC;
FIG. 6 is a block diagram of a parallel-to-serial data interface circuit;
FIG. 7 is a schematic diagram of a modulo 12 counter circuit of a read path;
FIG. 8 is a timing diagram of the operation of the shared array time-to-digital converter based on-chip storage of the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
As shown in fig. 1, the overall circuit includes a macro-pixel circuit with an SRAM cell and a read/write channel, a timing control circuit, a synchronization signal circuit, and a parallel-serial data interface circuit; wherein:
The data transmission start mark and the data transmission end mark generated by the time sequence control circuit are connected with the synchronous signal circuit, the data transmission window signal generated by the time sequence control circuit is connected with the parallel-serial data interface circuit, and the output end of the pixel array system of the macro pixel circuit is connected with the parallel-serial data interface circuit; the global signals comprise an enable signal EN, a RESET signal RESET and TDC high-frequency clock signals HCK1 and HCK2 which are accessed into each macro pixel of the whole pixel array system through a symmetrical H-Tree type distribution network. The macro pixel circuit is formed by a static random access memory SRAM, a memory write-in and read-out passage, 4*4 pixel units and two-section TDCs together to form one macro pixel in a pixel array; each pixel unit comprises a quenching circuit and a finite state machine; the memory write path comprises an arbitration circuit, an address coding circuit, a data latch circuit and a delay reset circuit; the memory read path includes an accumulator, a modulo 12 counter; the parallel-serial data interface circuit includes a 12-bit shift register and a multiplexer.
Wherein: the 32-row-by-32-column pixel array comprises 8-row-by-16-column pixel array blocks, each 8-row-by-16-column pixel array block is composed of 4 macro pixels and a parallel-serial conversion circuit, and the parallel-serial conversion circuit is composed of a 12-bit shift register and a multiplexer. The 200MHz LCK signal is generated by Timing Control, and is used as the input of SYNC to generate different synchronous signal circuits, and the synchronous signal circuits are re-submitted to the Timing Control to be processed into Control signals of a 32-row by 32-column pixel array, and meanwhile, the global signals comprise an enable signal EN, a RESET signal RESET and a 800MHz TDC clock, and the symmetrical H-Tree type distribution network is connected into each pixel of the whole array. After photon events are detected by different single pixels in the 8-row by 16-column pixel array block, the address of the corresponding pixel is processed through the arbitration of a writing channel in the macro pixel, and meanwhile, a writing clock is generated to control the quantized data of the two-section TDC to be written into the SRAM; and in the data output stage, the read-out path in the macro pixel reads out data from the SRAM under the control of the read clock, and the data is transmitted to the parallel-serial conversion circuit by the bus to finish the sequential output of the data.
The shared array time-to-digital converter based on-chip storage of the invention is as follows: and in the on-chip storage data writing stage, when a trigger signal is detected in the effective period of an enable signal EN in the macro pixel circuit, the two-stage TDC finishes time interval quantization and latches data, the finite state machine records photon echo times, and the photon event which is the first to arrive is judged and reserved through a memory writing path and the quantized result is written into the SRAM. The time sequence control circuit traverses the address of each storage unit in the SRAM through controlling the data ports in different time periods and reads out quantized data according to the address sequence; the synchronous signal circuit generates a sign signal corresponding to the output data, ensures the accuracy of data reading, and finally serially reads the TDC quantized data according to the sequence through the parallel-serial data interface circuit.
Fig. 2 shows a write channel structure and a timing diagram in a macro pixel, after a single pixel detects a photon event, a Decision Maker module compares and latches the results for every two REQi signals, arbitrates the first arriving photon signal until all REQi signals are compared, and outputs a QOUT signal as a write clock. In order to ensure the accuracy of the arbitration result, it is necessary to reset the Decision Maker after each arbitration is completed, and simultaneously generate the dtof_delay signal for uniformly accessing the data latched by the TDC in fig. 1 into the SRAM.
The specific functions of the readout path in the macropixel of fig. 3 are: the SEL signal is used as a clock of a 5-bit synchronous counter to generate an address of a storage unit in the SRAM, data is output from the address to a 12-bit shift register according to a period, the lck_and_tpi signal control register transmits the data output to the multiplexer, AND the SEL signal control register receives the data from the SRAM. The specific working process is as follows: when the CLKA signal is effective, updating AND reading of on-chip stored data are completed once, when the SEL signal is pulled high, the LCK_AND_TPi signal reads data once from the memory through the multiplexer, the data are transmitted to the 12-bit shift register, after the transmission is finished, the 12-bit shift register enters a shift mode, AND parallel data are converted into serial data to be read under the driving of a clock; the lck_and_tpi is generated by the Timing Control circuit Timing Control in fig. 1, AND after being processed by the read synchronization signal generating circuit SYNC, the LCK signal is input again to the Timing Control circuit Timing Control, AND the LCK signal is enabled in a segmentation way, so as to obtain lck_and_tp0 to lck_and_tp7, respectively, AND sequentially Control the eight memories.
The Timing Control circuit Timing Control shown in fig. 4 enables different Control signals in different time periods, so that data are uniformly and orderly read out according to a preset sequence. The timing control circuit is composed of a counter driven by a data readout clock LCK and timing control logic, a binary asynchronous adder is adopted to count the LCK period of the data readout clock, the timing logic is used to generate a corresponding data transmission window TPi (i=0, 1, 2..N) to conduct row selection control on the array, and then the TPi signal is further processed to drive address data and TDC quantized data in each pixel subarray to be read out according to a preset sequence in a high-level pulse width of the corresponding TPi signal. Taking an 8×8 system array as an example, a 4-way parallel reading mode is adopted, the 8×8 array is divided into 48×2 subarrays, and each subarray shares 16 pixels with one data output I/O port for data transmission. In each 8×2 subarray, each row of data is serially output through the row selection control and parallel-serial output interface circuit, and the data of the pixels close to the output pins are always read out first in this way. The specific working procedure is as follows: when the counter counts to a count value corresponding to the timing logic, the timing logic generates a corresponding narrow pulse signal to drive and reset a corresponding D trigger, and the formed time window interval is TP 0-TP 1, TP 1-TP 2 … TP 6-TP 7. The count value limits the working time of the system, and the system needs to finish the operations of circuit reset, trigger signal detection, counting and the like in the interval of 0-TP 0. The time window intervals TP0 to TP1 and TP1 to TP2 are time windows for reading out the first row address information and the first row TDC quantized data, respectively, and the TP1 to TP2 window intervals complete the pixel point data transmission operation in which the trigger signal is detected in one row of pixels. The window sections TP2 to TP3 and TP3 to TP4 are respectively identical to TP0 to TP1 and TP1 to TP2, and are used for reading out the corresponding data of the pixels of the second row, and the functions of the rest window sections are similar. The FRAME signal is used to flag the intra-FRAME data read phase, the CENB signal flags write enable active, and the CENA signal flags read enable active.
Fig. 5 is a diagram of a synchronization signal circuit SYNC, which mainly provides a flag signal for identifying serial output data. The module generates three synchronization signals, namely a WORD signal (WORD) and a BIT signal (BIT) corresponding to the output DATA, and combines the DATA output (data_out) to facilitate subsequent DATA processing. The TP1 and LCK signals are provided by a time sequence control module, the output BIT signals are synchronously generated by the LCK signals, the corresponding relation between BIT and WORD depends on the BIT number of data to be read, and the output address data and TDC quantized data are respectively marked by a dual-mode counter.
Fig. 6 shows a parallel-serial data interface module, which is composed of a shift register and a multiplexer to realize the time-sharing multiplexing of data readout and serial output. The working flow is as follows: after the shift register pulls the SEL signal high, the data is read once from the memory under the drive of lck_and_tpi, then the SEL signal is converted to low level, AND the register enters a shift mode to convert the parallel data into serial data for reading.
Fig. 7 is a schematic diagram of a modulo 12 counter circuit of a read path. The modulo 12 Counter generates the CLKA and SEL signals required for FIG. 3, wherein the CLKA signal is used to read and update data from the memory, the counter_6 signal is selected as the CLKA signal, used to update data read from the memory, and the data is written into the shift register in conjunction with the SEL signal; the SEL signal is also used to accumulate memory addresses, and select counter_12 to generate the SEL signal, so that the address data is incremented by one each time counter_12 arrives, and the data is read each time counter_6 arrives.
In the shared array time-to-digital converter based on-chip storage of the present invention, the operation sequence of the whole circuit is as shown in fig. 8, after RESET, in the gating time of the enable signal EN, when the multiphoton event Reqi is triggered, the memory write path arbitrates whether the interval of the multiphoton event satisfies the operation of the write time interval, thereby retaining the photon time satisfying the requirement, generating the write clock DTOF, and the ADDRESS information is written in the ADDRESS BUS, and the quantized data DATABUS is written in the corresponding memory cell in the memory; after quantization is completed, the write enable jumps to a high level, the read clock CLKA works in a fixed period, a data reading operation and an address data updating operation are completed, and data is serially output through the parallel-serial data interface module of fig. 6.
Compared with the traditional scheme, the shared array time-to-digital converter based on-chip storage is provided with the following components: (1) The power consumption of on-chip storage consumption is low, each storage unit only uses six transistors to realize data latching, and meanwhile, the sharing structure reduces the number of TDCs, and further reduces the power consumption and the consumption of the area. (2) The data transmission speed stored on the chip is high, and the reading time is effectively reduced on the premise of the same data throughput. (3) The writing and reading paths stored on the chip can meet the establishment time and the holding time of data, and the probability of data writing or reading errors can be reduced when large-scale data transmission is faced.
The foregoing is only a preferred embodiment of the invention, it being noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the invention.
Claims (7)
1. The shared array time-to-digital converter based on-chip storage is characterized by comprising a macro pixel circuit with an SRAM unit and a read-write channel, a time sequence control circuit, a synchronous signal circuit and a parallel-serial data interface circuit; wherein:
the data transmission start mark and the data transmission end mark generated by the time sequence control circuit are connected with the synchronous signal circuit, the data transmission window signal generated by the time sequence control circuit is connected with the parallel-serial data interface circuit, and the output end of the pixel array system of the macro pixel circuit is connected with the parallel-serial data interface circuit; the global signals comprise an enable signal EN, a RESET signal RESET and a TDC, and the high-frequency clock signals HCK1 and HCK2 are accessed into each macro pixel of the whole pixel array system through a symmetrical H-Tree distribution network;
The macro pixel circuit is formed by a static random access memory SRAM, a memory write-in and read-out passage, 4*4 pixel units and two-section TDCs together to form one macro pixel in a pixel array;
in the macro pixel circuit, a memory read-out path realizes an address accumulation function through a 5-bit synchronous counter, traverses addresses of storage units in the SRAM, and completes parallel reading and serial output of data by multiplexing a 12-bit shift register and a multiplexer in a time-sharing way under the coordination of a time sequence control circuit;
The synchronous signal circuit mainly provides a mark signal for identifying serial output DATA, and mainly generates three synchronous signals of a WORD signal WORD and a BIT signal BIT corresponding to the output DATA, and combines the DATA output DATA_OUT to facilitate subsequent DATA processing; the correspondence of the BIT signal BIT to the WORD signal WORD depends on the number of BITs of the data to be read;
After the parallel-serial data interface circuit receives the data transmission window signal TPi generated by the time sequence control circuit, the data transmission clock signal LCK_AND_TPi is generated by AND operation of the clock LCK signal, AND the signal is effective in the high level of the pulse width of the corresponding set data transmission window TPi, so that the data on the corresponding path is normally transmitted; the low-frequency clock LCK signal is shielded outside the high-level pulse width of the data transmission window TPi, and the data transmission is forbidden; the parallel-to-serial data interface circuit completes serial output of data under control of the corresponding LCK_AND_TPi signal.
2. The on-chip storage based shared array time-to-digital converter of claim 1, wherein the macro-pixel circuit, each pixel cell includes a quenching circuit and a finite state machine; the memory write path comprises an arbitration circuit, an address coding circuit, a data latch circuit and a delay reset circuit; the memory read path includes an accumulator, a modulo 12 counter; the parallel-serial data interface circuit includes a 12-bit shift register and a multiplexer.
3. The shared array time-to-digital converter based on-chip storage of claim 2, wherein the macro-pixel circuit stores data in the on-chip storage stage, when the trigger signal is detected in the enable signal EN active period, the two-stage TDC finishes time interval quantization and latching, the finite state machine photon records the echo times, and judges and retains the photon signal which arrives first through the memory writing path, and after the write clock signal arrives, the data is written into the SRAM.
4. The on-chip storage-based shared array time-to-digital converter of claim 2 wherein said macro-pixel circuit stores data read-out phases on-chip, said timing control circuit traversing addresses of memory cells in the SRAM by controlling the data ports in different time periods and reading out quantized data in address order; the synchronous signal circuit generates a sign signal corresponding to the output data, ensures the accuracy of data reading, finally completes parallel-to-serial conversion of the data by the shift register, performs time-division multiplexing on the output port by the multiplexer, and serially reads TDC quantized data according to the sequence.
5. The on-chip storage based shared array time-to-digital converter of claim 2, wherein in the macro-pixel circuit, the finite state machine of each pixel sets the address bus a <0> address to 1 after detecting the DTOF signal after detecting the first photon event, ensuring that the a <0> address change does not affect the current data write address; the DTOF signal is generated after a delay reset circuit in a memory writing path judges and processes photon events reserved in an arbitration circuit; the finite state machine characterizes the number of currently detected echoes through a Q1 signal, an arbitration circuit of a memory write-in path keeps photon event information which arrives first, judges that two photon events smaller than 5ns are photon event conflicts, and discards the photon events which arrive after the two photon events collide.
6. The on-chip memory-based shared array time-to-digital converter of claim 5, wherein the arbitration circuit of the memory write path detects the REQ signal of each pixel, the Decision Maker module of the arbitration circuit compares the two signals, finally arbitrates the photon time signal that arrives first and inputs the photon time signal to the DELAY reset circuit to generate DTOF and dtof_delay signals, and the address coding circuit in the memory write path generates the address of the corresponding pixel, and when the dtof_delay signal is detected by the data latched by the two-stage TDC, the data is uniformly accessed into the SRAM.
7. The on-chip storage based shared array time-to-digital converter of claim 1, wherein in the macro-pixel circuit, the memory readout is specifically: the timing control circuit is composed of a counter driven by a data reading clock LCK signal and timing control logic, and different control signals are enabled in different time periods, so that data are read out uniformly and orderly according to a preset sequence; when the counter counts to a count value corresponding to the timing logic, the timing logic generates a corresponding narrow pulse signal to drive AND reset a corresponding D trigger to form a corresponding time window interval for corresponding data reading AND processing, AND the final result is that the clock LCK signal is divided into eight sections for enabling processing to obtain an LCK_AND_TPi signal, AND eight memories are controlled in sequence; in the memory readout circuit, when a read signal CLKA generated by a module 12 counter is pulled high, data in a memory is updated to a multiplexer in the parallel-to-serial data interface circuit, another period level SEL generated by the module 12 counter is used for controlling the multiplexer in the parallel-to-serial data interface circuit, after LCK_AND_TPi is detected, the data in the memory is transmitted to a 12-bit shift register in the parallel-to-serial data interface circuit, after transmission is finished, the 12-bit shift register enters a shift mode, AND parallel data is converted into serial data to be output under the driving of a clock LCK signal.
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