CN100498212C - CCD data acquisition and processing equipment used for high-speed displacement measurement - Google Patents

Abstract

The invention discloses a CCD data collecting and processing device which is used in high-speed displacement measurement, thereinto linear array CCD sensor outputs signal charge to A/D converting circuit for analog-to-digital conversion, the A/D converting circuit outputs digital signal to high-speed data buffer FIFO, the FIFO outputs pixel signal to signal processing circuit, it characterized in that: it possesses comparator selecting circuit, drive clock circuit and pixel counter, the comparator selecting circuit receives signal charge of said linear array CCD sensor, and outputs read, write signal to FIFO, outputs interrupting signal to signal processing circuit. The remarkable effects of the invention are: it can collect big signal output by CCD and process in real time, use resource of system to discriminate data information, eliminate useless information, realize collection in real time and in-phase process, and increase speed and efficiency of integral system.

Description

The ccd data collection and the treating apparatus that are used for high-speed displacement measuring

Technical field

The invention belongs to the ccd sensor field of measuring technique, specifically, relate to a kind of ccd data collection and treating apparatus of being used for high-speed displacement measuring that the Large Volume Data of line array CCD sensor output is carried out high speed acquisition and handles in real time.

Background technology

Charge coupled device ccd (Charge Coupled Device) is a kind of semiconductor photoelectric device of widespread use, incident light can be converted to signal charge and export one by one by pixel, has that noise is low, spectral response is wide, characteristics such as precision and sensitivity height.CCD is divided into linear array and face battle array two classes.In the industrial automation field, line array CCD sensor commonly used carries out various detections, as contactless dimensional measurement, displacement measurement etc.Carrying out high speed when measuring, is to realize the key measured to the collection of line array CCD output signal with handling.

Existing more to ccd signal data acquisition and Processing Technology Research, " centroid algorithm determine that the hardware of CCD image point position realizes " done as the Shanghai technology physics what is heard Lu Hong of the Chinese Academy of Sciences etc., comprise ccd sensor, the A/D change-over circuit, metadata cache FIFO, DSP signal processing circuit: after ccd sensor output signal electric charge carries out analog to digital conversion for the A/D change-over circuit, the output terminal output digital signal of A/D change-over circuit is given metadata cache FIFO, the output terminal output pixel signal of metadata cache FIFO is given the DSP signal processing circuit, the DSP signal processing circuit adopts centroid algorithm to determine the CCD image point position, improves measuring accuracy.The shortcoming of this method is: the data volume of ccd sensor output is bigger, need carry out AD conversion and storage to all pixel signals, carry out data processing with gravity model appoach more at last, make that the memory space and the treatment capacity of data are very big, not only expensive source but also time-consuming, measurement and image data speed are very slow, can't gather in real time and handle big data quantity, influence real-time picking rate and effect, can not be applied in the field that to carry out high-speed displacement measuring.

" a kind of quick CCD object localization method " that monarch Li Lan of Zhongnan Polytechnic College etc. does: comprise matrix CCD, video processor, the A/D change-over circuit, digital comparator, metadata cache FIFO, the DSP signal processing circuit: matrix CCD output two-dimensional video signal carries out analog to digital conversion for after video processor is handled the A/D change-over circuit, the output terminal output digital signal of A/D change-over circuit is given digital comparator, behind the digital comparator intercepting valid data, send to metadata cache FIFO again, the output terminal output digital video signal of metadata cache FIFO is given the DSP signal processing circuit, used digital comparator, can the big amplitude signal of area array CCD output effectively be extracted, thereby reduced the memory space and the treatment capacity of data.Its shortcoming is: because selected digital comparator will compare by turn to each data, specific rate is slower mutually with analog comparator, can reduce the speed of data screening; In addition, controller carries out discontinuous collection and processing to ccd output signal, gathers once and handles once, and measurement and image data speed are slower, can't realize the real-time processing to signal; And this method is to carry out edge contour with the two-dimensional CCD sensor to extract, and can't carry out high-speed displacement measuring.

" based on the research of the novel micro-displacement sensor of line array CCD " that Zhejiang University side's equality is done, comprise timing sequencer, ccd sensor, metadata cache FIFO, D/A converter, comparer and sampling hold circuit: wherein FIFO and D/A converter are formed the ramp signal generator, timing sequencer control ramp signal generator output ramp signal, comparer is relatively output signal and the reference voltage of CCD one by one, and according to comparative result control sampling hold circuit ramp signal is sampled and to keep last output result.The shortcoming of this method is: owing to do not use A/D converter and signal processor that ccd signal is gathered and subsequent treatment, also do not discern the physical location of pixel by counter, but the sampling retention value of directly using ramp signal is as the exposure image point position, so be difficult to guarantee the precision of measurement.

In sum, existing C CD signal data acquisition and treatment technology, usually the speed of measurement and data acquisition is slower, the effect of handling is bad in real time, can't realize uninterrupted collection and processing to ccd signal, the displacement measurement of only suitable static measurement or microinching object will lose efficacy for high-speed displacement measuring.

Summary of the invention

The purpose of this invention is to provide a kind of ccd data collection and treating apparatus that is used for high-speed displacement measuring, can carry out continual high speed acquisition and processing in real time to the big data quantity signal of ccd sensor output, effectively utilize system resource, make data acquisition and signal Processing to carry out simultaneously, the steering logic of appropriate design can guarantee the speed of data acquisition and the effect of handling in real time, promotes the quality of high-speed displacement measuring.The present invention can be used for measuring at a high speed, in real time the immediate movement of moving object.

For achieving the above object, the present invention is provided with a kind of ccd data collection and treating apparatus that is used for high-speed displacement measuring, comprises line array CCD sensor, A/D change-over circuit, data cache FIFO, signal processing circuit; After wherein said line array CCD sensor output signal electric charge carries out analog to digital conversion for described A/D change-over circuit, the output terminal output digital signal of A/D change-over circuit is given described data cache FIFO, the output terminal output pixel signal of data cache FIFO is given described signal processing circuit, its key is: also be provided with comparer screening circuit, drive clock circuit and pixel counter, wherein the input end of comparer screening circuit receives the signal charge of described line array CCD sensor, the output terminal of described comparer screening circuit exports read control signal respectively and write control signal is given described data cache FIFO, and described comparer screening circuit output look-at-me is given described signal processing circuit; Described drive clock circuit output pulse signal is given described line array CCD sensor, A/D change-over circuit, data cache FIFO and pixel counter, and this pixel counter output count signal is given described signal processing circuit.

Described drive clock circuit both provided its work essential scan clock for CCD, provided synchronous clock for data acquisition and treating apparatus again, make the collection of data and ccd sensor signal output synchronously.Owing to designed comparer screening circuit, the storage of data and reading all by comparer screening circuit start, thus signal processing circuit is freed from heavy control task; And system only needs effective pixel signal of CCD is stored and handled, and has shortened the time of signal processing circuit data processing greatly.The collection of data is relatively independent with processing two parts, when Acquisition Circuit is carried out high speed acquisition to ccd signal, realizes handling in real time thereby signal processing circuit reads the data that are stored among the FIFO.Can uninterruptedly scan line array CCD like this, thereby improve the speed of systematic survey.The native system data acquisition rate reaches as high as 40Mbyte/s, and the effect of handling is better in real time.

Described comparer screening circuit is by digital potentiometer, comparer and trigger are formed, three of digital potentiometer input end CS wherein, INC and U/D receive the control signal of described signal processing circuit output, the output terminal output threshold level of digital potentiometer is given the reverse input end of described comparer, the positive input of comparer receives the signal charge of described line array CCD sensor, the output terminal output trigger pip of comparer is given the input end D of trigger, the forward output terminal Q and the inverse output terminal Q of this trigger export read control signal and write control signal respectively, and the forward output terminal Q of trigger also exports described look-at-me.

Digital potentiometer output threshold level is given described comparer, when the signal charge value of line array CCD sensor is higher than threshold level, just can be compared device and confirm as valid data, and control trigger upset, output look-at-me, read control signal and write control signal, data cache FIFO and signal processing circuit are just effectively worked, and have saved resource space.

Because the amplitude of ccd output signal is subjected to Effect of Environmental and has certain variation, can not use fixed threshold so extract the useful signal of CCD, but adopt digital potentiometer to the supply voltage dividing potential drop, thereby insert an adjustable threshold level to comparer, make it to adapt to self changing of ccd output signal, thereby eliminate the influence of environment measuring.Digital potentiometer can be adjusted the position of its tap by three outside input pins, thereby changes resistance value, and these three pins comprise sheet choosing end CS, slip control end INC and direction control end U/D.This device use DSP controls three control ends of digital potentiometer, and the tap position of digital potentiometer is regulated on each amplitude size adaptation ground of measuring the ccd output signal after the preceding DSP of beginning changes according to AD, thereby provides an appropriate threshold to comparer.

Described line array CCD sensor is converted to signal charge with outside incident light, and export to the input end AIN of described A/D change-over circuit one by one by pixel, the clock end CLK of A/D change-over circuit and output enable end OE receive the reset pulse RS of described drive clock circuit output respectively and shift pulse SH, the digital output end D1 of A/D change-over circuit～D8 output digital signal is given input end D0～D7 of described data cache FIFO, and the output terminal Q0 of this data cache FIFO～Q7 output pixel signal is given described signal processing circuit; The input end of clock RCLK that reads of described data cache FIFO receives the clock signal that described signal processing circuit is exported, write input end of clock WCLK and accept the pulse RS ' of described drive clock circuit output pulse RS after oppositely, the full flag terminal FF of data cache FIFO and the full spacing wave of empty flag terminal EF output are given described signal processing circuit, this data cache FIFO is provided with and reads Enable Pin REN and receive described trigger forward output terminal Q and export described read control signal, is provided with to write Enable Pin WEN and receive described trigger inverse output terminal Q and export described write control signal.

The 8 bit data input end D0-D7 of data cache FIFO are corresponding with 8 position datawire D1-D8 of A/D change-over circuit to link to each other, write enable signal end WEN and link to each other with the inverse output terminal Q of comparator module and controlled by comparer screening circuit, make FIFO only store effective pixel signal of CCD output.The CLK end of A/D change-over circuit is provided with not gate and is connected with the WCLK end of FIFO.Because FIFO deposits data at each rising edge of writing clock, so the reset pulse RS of CCD after oppositely (being RS ') is sent into WCLK and holds as writing clock.The Q of output terminal in the same way that reads enable signal end REN and comparer screening circuit of FIFO links to each other, is provided by DSP and read clock RCLK, and full scale will FF and the empty sign EF IO that receives DSP holds simultaneously, reads storage data among the FIFO by DSP.FIFO is to the storage and DSP the reading by comparer screening circuit start data among the FIFO of A/D change-over circuit sampled data like this.

Described signal processing circuit is made up of level translator and signal processor DSP, wherein the input end 1B1～1B8 of level translator accepts the pixel signal of described data cache FIFO output, and is exported to input end GPIOA0～GPIOA7 of described signal processor DSP by output terminal 1A1～1A8; The input end 2B1 of level translator receives the full signal of the full flag terminal FF of described data cache FIFO, input end 2B2 receives the spacing wave of the empty flag terminal EF of described data cache FIFO, and is exported to input end GPIOA8 and the GPIOA9 of described signal processor DSP respectively by output terminal 2A1 and 2A2; Signal processor DSP is provided with clock signal terminal RCLK clock signal and gives described data cache FIFO, signal processor DSP is provided with the look-at-me that broken ends of fractured bone XNMI in the non-shielding receives described trigger output, signal processor DSP is provided with the GPIOA10 end, the GPIOA11 end, the GPIOA12 end connects three input end CS of digital potentiometer respectively, INC and U/D, export three control signals and give described digital potentiometer, counting clock end TCLKIN is set for the built-in described pixel counter of described signal processor DSP, this pixel counter and initiating terminal CAP1 receives the reset pulse RS of described drive clock circuit output respectively and shifts pulse SH.

The DSP that this device uses both can be used as processor, can be used as controller again and was used.Because DSP is the 3.3V power supply, and ultra high speed A and part of data acquisition are the 5V systems, so need with a level translator signal of 5V be transferred to the signal of 3.3V between FIFO and DSP.Level translator has two groups of independently-powered separately ports, and the A mouth is powered by VCCA, and supply voltage is 3.3V, and the B mouth is powered by VCCB, and supply voltage is 5V, 3.3V system and 5V system can be coupled together by level translator like this.Universal I pin GPIOA0～GPIOA7 of DSP is linked to each other respectively with the 1A1～1A8 of level translator as data line, receive 8 CCD useful signals that FIFO sends here; GPIOA8, GPIOA9 link to each other with empty sign EF with the full scale will FF of FIFO respectively by level translator; Universal timepiece source XCLKOUT links to each other with the RCLK end of FIFO as the clock of reading that offers FIFO.Non-shielding is interrupted XNMI and is linked to each other with the Q of output terminal in the same way of comparer screening circuit, is used for accepting look-at-me behind the useful signal end of output of CCD.

Pixel counter clock TCLKIN end is sent in the RS pulse of driven CCD, allowed the pixel counter that the pulse of RS is counted, be convenient to subsequent treatment; Simultaneously SH is sent into capture unit CAP1 end, the negative edge in that the beginning of each scan period of CCD is caught SH by CAP1 begins counting thereby generation seizure interruption starts the pixel counter.GPIOA10～GPIOA12 is used to control the tap position of digital potentiometer, links to each other with U/D with CS, the INC of digital potentiometer respectively.

Signal processor DSP in the described signal processing circuit is provided with:

Be used for the initialized device of DSP;

The device that is used for setting threshold; Regulate the digital potentiometer tap position, thereby provide appropriate threshold to comparer;

The device that is used for the starting impulse counting; Start the pixel counter, thereby the drive clock circuit output pulse is counted;

Be used to judge whether that comparer screens the device of the look-at-me of circuit output,

If there is not look-at-me, then return and describedly be used to judge whether that the device of the look-at-me of comparer screening circuit output judges once more,

If look-at-me is arranged, then enter the device that is used to latch the pixel counter;

Be used for reading the device of described data cache FIFO data;

The device that is used for data processing and result of calculation;

The device that is used for result's output.

DSP will handle after reading data among the FIFO, be to improve processing speed, adopt maximum value process to extract the particular location of measured data on the ccd array.The some CCD useful signals that read are compared,, just can obtain needed data message by calculating the position of the pairing picture point of peak point on ccd array with the signal of peak point as the output of testee picture point.

Remarkable result of the present invention is: can carry out continual high speed acquisition and processing in real time to the big data quantity signal of line array CCD sensor output, utilize system resource, data message is effectively screened, reject irrelevant information, realize the high speed acquisition of target data; Reasonably steering logic has guaranteed to make data acquisition and signal Processing to carry out simultaneously to the real-time processing of signal and the efficient running of each several part circuit, has improved the speed and the efficient of total system, can be widely used in the occasion that needs high-speed displacement measuring.

Description of drawings

Fig. 1 is a frame assumption diagram of the present invention;

Fig. 2 is the circuit theory diagrams of A/D change-over circuit and data cache FIFO;

Fig. 3 is the circuit theory diagrams of comparer screening circuit;

Fig. 4 is the circuit theory diagrams of signal processing circuit;

Fig. 5 is the workflow block diagram of signal processor DSP;

Fig. 6 is that ccd data is gathered sequential chart;

Fig. 7 is the working timing figure of comparer screening circuit;

Fig. 8 is the position view of CCD peak value picture point.

Embodiment

Below in conjunction with the drawings and specific embodiments the present invention being described in further detail, is example with the moment displacement of measuring moving object at a high speed, in real time:

As shown in Figure 1: a kind of ccd data collection and treating apparatus that is used for high-speed displacement measuring, form by line array CCD sensor 1, A/D change-over circuit 2, data cache FIFO3, signal processing circuit 4, comparer screening circuit 5, drive clock circuit 6 and pixel counter 7; After described line array CCD sensor 1 output signal electric charge carries out analog to digital conversion for described A/D change-over circuit 2, the output terminal output digital signal of A/D change-over circuit 2 is given described data cache FIFO3, the output terminal output pixel signal of data cache FIFO3 is given described signal processing circuit 4, wherein the input end of comparer screening circuit 5 receives the signal charge of described line array CCD sensor 1, the output terminal of described comparer screening circuit 5 exports read control signal respectively and write control signal is given described data cache FIFO3, and described comparer screening circuit 5 output look-at-mes are given described signal processing circuit 4; Described drive clock circuit 6 output pulse signals are given described line array CCD sensor 1, A/D change-over circuit 2, data cache FIFO3 and pixel counter 7, and these pixel counter 7 output count signals are given described signal processing circuit 4.

Described drive clock circuit 6 both provided its work essential scan clock for CCD, provided synchronous clock for data acquisition and treating apparatus again, make high-speed moving object moment displacement data collection and the signal output of CCD synchronously.Owing to designed comparer screening circuit 5, the storage of data and reading is all started by comparer screening circuit 5, thereby signal processing circuit 4 is freed from heavy control task; And system only needs effective pixel signal of CCD is stored and handled, and has shortened the time of signal processing circuit 4 data processing greatly.The collection of data is relatively independent with processing two parts, when Acquisition Circuit is carried out high speed acquisition to ccd signal, realizes handling in real time thereby signal processing circuit 4 reads the data that are stored among the FIFO.Can uninterruptedly scan line array CCD like this, thereby improve the speed of systematic survey.The native system data acquisition rate reaches as high as 40Mbyte/s, and the effect of handling is better in real time.

As shown in Figure 3: described comparer screening circuit 5 is by digital potentiometer 8, comparer 9 and trigger 10 are formed, three of digital potentiometer 8 input end CS wherein, INC and U/D receive the control signal of described signal processing circuit 4 outputs, the output terminal output threshold level of digital potentiometer 8 is given the reverse input end of described comparer 9, the positive input of comparer 9 receives the signal charge of described line array CCD sensor 1, the output terminal output trigger pip of comparer 9 is given the input end D of trigger 10, the forward output terminal Q and the inverse output terminal Q of this trigger 10 export read control signal and write control signal respectively, and the forward output terminal Q of trigger 10 also exports described look-at-me.

As shown in Figure 7: digital potentiometer 8 output threshold levels are given described comparer 9, when the signal charge value of line array CCD sensor 1 is higher than threshold level, just can be compared device 9 and confirm as valid data, and control trigger 10 upsets, output look-at-me, read control signal and write control signal, data cache FIFO3 and signal processing circuit 4 are just effectively worked, and have saved system resource, have improved work efficiency.

Comparer 9 adopts the MAX913 of MAXIM company.Because the amplitude of ccd output signal is subjected to the influence of bias light and measured object and has certain variation, can not use fixed threshold so extract the useful signal of CCD, but adopt 8 pairs of supply voltage dividing potential drops of digital potentiometer, thereby insert an adjustable threshold level for comparer 9, make it to adapt to self changing of ccd output signal, thereby eliminate the influence of environment measuring.Digital potentiometer uses the DS1804 of DALLAS company.It is the non-volatile digital potentiometer that contains 100 taps, can adjust the position of tap by three outside input pins, thereby changes resistance value, and these three pins comprise sheet choosing end CS, slip control end INC and direction control end U/D.Native system use DSP controls three control ends of DS1804, and the tap position of digital potentiometer is regulated on each amplitude size adaptation ground of measuring the ccd output signal after the preceding DSP of beginning changes according to AD, thereby provides an appropriate threshold to comparer.

As shown in Figure 2: described line array CCD sensor 1 is converted to signal charge with outside incident light, and export to the input end AIN of described A/D change-over circuit 2 one by one by pixel, the clock end CLK of A/D change-over circuit 2 and output enable end OE receive the reset pulse RS of described drive clock circuit 6 outputs respectively and shift pulse SH, the digital output end D1 of A/D change-over circuit 2～D8 output digital signal is given input end D0～D7 of described data cache FIFO3, and the output terminal Q0 of this data cache FIFO3～Q7 output pixel signal is given described signal processing circuit 4; The input end of clock RCLK that reads of described data cache FIFO3 receives the clock signal that described signal processing circuit 4 is exported, write input end of clock WCLK and accept the pulse RS ' of described drive clock circuit 6 output pulse RS after reverse, the full flag terminal FF of data cache FIFO3 and the full spacing wave of empty flag terminal EF output are given described signal processing circuit 4, this data cache FIFO3 is provided with and reads Enable Pin REN and receive described trigger 10 forward output terminal Q and export described read control signal, is provided with to write Enable Pin WEN and receive described trigger 10 inverse output terminal Q and export described write control signal.

As shown in Figure 6, A/D change-over circuit 2 adopts the TLC5540 of TI company.That data cache FIFO3 adopts is the IDT72240 of IDT company.The 8 position datawire D1-D8 of its 8 bit data input end D0-D7 and TLC5540 are corresponding to link to each other, and writes enable signal end WEN and links to each other with the inverse output terminal Q of comparator module and be subjected to 5 controls of comparer screening circuit, makes FIFO only store effective pixel signal that CCD exports.The CLK end of TLC5540 is provided with not gate and is connected with the WCLK end of IDT72240.Because IDT72240 deposits data at each rising edge of writing clock, so the reset pulse RS of CCD after oppositely (being RS ') is sent into WCLK and holds as writing clock.The Q of output terminal in the same way that reads enable signal end REN and comparer screening circuit 5 of IDT72240 links to each other, is provided by DSP and read clock RCLK, and full scale will FF and the empty sign EF IO that receives DSP holds simultaneously, reads storage data among the FIFO by DSP.FIFO is started by comparer screening circuit 5 reading of data among the FIFO the storage and the DSP of A/D change-over circuit 2 sampled datas like this.

As shown in Figure 4: described signal processing circuit 4 is made up of level translator 11 and signal processor DSP12, wherein the input end 1B1～1B8 of level translator 11 accepts the pixel signal of described data cache FIFO3 output, and is exported to input end GPIOA0～GPIOA7 of described signal processor DSP12 by output terminal 1A1～1A8; The input end 2B1 of level translator 11 receives the full signal of the full flag terminal FF of described data cache FIFO3, input end 2B2 receives the spacing wave of the empty flag terminal EF of described data cache FIFO3, and is exported to input end GPIOA8 and the GPIOA9 of described signal processor DSP12 respectively by output terminal 2A1 and 2A2; Signal processor DSP12 is provided with clock signal terminal RCLK clock signal and gives described data cache FIFO3, signal processor DSP12 is provided with the look-at-me that broken ends of fractured bone XNMI in the non-shielding receives described trigger 10 outputs, signal processor DSP12 is provided with the GPIOA10 end, the GPIOA11 end, the GPIOA12 end connects three input end CS of digital potentiometer 8 respectively, INC and U/D, export three control signals and give described digital potentiometer 8, counting clock end TCLKIN is set for the built-in described pixel counter 7 of described signal processor DSP12, this pixel counter 7 and initiating terminal CAP1 receives the reset pulse RS of described drive clock circuit 6 outputs respectively and shifts pulse SH.

That DSP uses is the TMS320F2812 of American TI Company, and this device both can be used as processor, can be used as controller again and was used.TMS320F2812 inside carries pixel counter 7.Because TMS320F2812 is the 3.3V power supply, and ultra high speed A and part of data acquisition are the 5V systems, so need the signal of 5V be transferred to the signal of 3.3V with a level translator (SN74ALVC164245) between FIFO and DSP.SN74ALVC164245 has two groups of independently-powered separately ports, and the A mouth is powered by VCCA, and supply voltage is 3.3V, and the B mouth is powered by VCCB, and supply voltage is 5V, 3.3V system and 5V system can be coupled together by SN74ALVC164245 like this.Universal I pin GPIOA0～GPIOA7 of TMS320F2812 is linked to each other respectively with 1A1～1A8 of SN74ALVC164245 as data line, receive 8 CCD useful signals that FIFO sends here; GPIOA8, GPIOA9 link to each other with empty sign EF with the full scale will FF of FIFO respectively by level translator; Universal timepiece source XCLKOUT links to each other with the RCLK end of FIFO as the clock of reading that offers FIFO.Non-shielding is interrupted XNMI and is linked to each other with the Q of output terminal in the same way of comparer screening circuit 5, is used for accepting look-at-me behind the useful signal end of output of CCD.Pixel counter clock TCLKIN end is sent in the RS pulse of driven CCD, allowed the pixel counter that the pulse of RS is counted, be convenient to subsequent treatment; Simultaneously SH is sent into capture unit CAP1 end, the negative edge in that the beginning of each scan period of CCD is caught SH by CAP1 begins counting thereby generation seizure interruption starts the pixel counter.GPIOA10～GPIOA12 is used to control the tap position of digital potentiometer, links to each other with U/D with CS, the INC of DS1804 respectively.

As shown in Figure 5: the signal processor DSP12 in the described signal processing circuit 4 is provided with:

Be used for the initialized device of DSP;

The device that is used for setting threshold; Regulate the digital potentiometer tap position, thereby provide appropriate threshold to comparer;

The device that is used for the starting impulse counting; Start the pixel counter, thus the device that 6 output pulses are counted to the drive clock circuit;

Be used to judge whether that comparer screens the device of the look-at-me of circuit 5 outputs,

If there is not look-at-me, then return and describedly be used to judge whether that the device of the look-at-me of comparer screening circuit (5) output judges once more,

If look-at-me is arranged, then enter the device that is used to latch the pixel counter;

Be used for reading the device of described data cache FIFO3 data;

The device that is used for data processing and result of calculation;

The device that is used for result's output.

DSP will handle after reading data among the FIFO, be to improve processing speed, adopt maximum value process to extract the particular location of measured data on the ccd array.The some CCD useful signals that read are compared,, just can obtain needed data message by calculating the position of the pairing picture point of peak point on ccd array with the signal of peak point as the output of testee picture point.

Its principle of work is as follows:

The utilization of line array CCD Displacement Measurement be laser triangulation principle at present commonly used, so accurately the image point position of measurement testee on CCD just becomes the main task of system.At first the simulating signal of line array CCD output is carried out the high-speed AD sampling, then with the data storage that collects in high-speed cache FIFO.Because CCD pixel number is many, there is no need all data that AD gathers are all stored, store so only will comprise those useful signals of image point position information.The useful signal that the signal system of being of the exposure pixel output on the CCD pixel array need store and handle, its amplitude is than the level height of invalid pixel output, so the useful signal that just can only line array CCD be exported by the screening of comparer 9 is stored among the FIFO, thereby reduces the memory space of FIFO and the data processing amount of DSP.DSP reads the useful signal among the FIFO, finds peak point again in conjunction with the count value of counter to the pulse of CCD pixel according to maximum value process, just can calculate the particular location of object picture point on line array CCD.Because the pixel number of useful signal is much smaller than the pixel number of whole CCD array, and effectively the position of pixel is again continuous, so at a CCD in the scan period, DSP reads the data among the FIFO and time of being handled is very short.

As shown in Figure 8:, use the pixel counter to come the pixel pulse of ccd sensor output is counted in order to calculate the position of the corresponding picture point of ccd output signal peak value on ccd array.Because the reset pulse RS and the pixel impulsive synchronization of driven CCD, so only need RS is counted.The pixel counter is started by the negative edge that CCD shifts pulse SH, and each a RS impulse meter all increases 1.Comparator module is sent interrupt request to DSP after CCD exports last effective pixel pulse, the value (being assumed to be M) that DSP has no progeny and at first latchs the pixel counter in accepting, read the data of storing among the FIFO then and find out peak value, if total L of the data of storing among the FIFO, maximal value is N data wherein, and then testee position of picture point on CCD is exactly M-L+N.Just can calculate the immediate movement S of high-speed moving object again in conjunction with the pixel of ccd sensor size and optical system correlation parameter:

$S=\frac{(M-L+N-O)\·r}{\mathrm{\β}}---\left(1\right)$

In the formula (1), O is an original position of measuring the preceding object picture point of beginning, and r is the pixel dimension of CCD, and β is the enlargement ratio of optical system.

DSP can show result by the output of the charactron on the measuring system instrument panel, return interruption then, waits for the look-at-me that next scan period comparator module is sent.In the process that DSP handles data, the scanning of ccd sensor is not interrupted, thereby has realized real-time processing truly.

Claims (5)

1, a kind of ccd data collection and treating apparatus that is used for high-speed displacement measuring comprises line array CCD sensor (1), A/D change-over circuit (2), data cache FIFO (3), signal processing circuit (4); After wherein said line array CCD sensor (1) output signal electric charge carries out analog to digital conversion for described A/D change-over circuit (2), the output terminal output digital signal of A/D change-over circuit (2) is given described data cache FIFO (3), the output terminal output pixel signal of data cache FIFO (3) is given described signal processing circuit (4), it is characterized in that: also be provided with comparer screening circuit (5), drive clock circuit (6) and pixel counter (7), wherein the input end of comparer screening circuit (5) receives the signal charge of described line array CCD sensor (1), the output terminal of described comparer screening circuit (5) exports read control signal respectively and write control signal is given described data cache FIFO (3), and described comparer screening circuit (5) output look-at-me is given described signal processing circuit (4); Described drive clock circuit (6) output pulse signal is given described line array CCD sensor (1), A/D change-over circuit (2), data cache FIFO (3) and pixel counter (7), and this pixel counter (7) output count signal is given described signal processing circuit (4).

2, ccd data collection and the treating apparatus that is used for high-speed displacement measuring according to claim 1, it is characterized in that: described comparer screening circuit (5) is by digital potentiometer (8), comparer (9) and trigger (10) are formed, wherein the output terminal of digital potentiometer (8) output threshold level is given the reverse input end of described comparer (9), the positive input of comparer (9) receives the signal charge of described line array CCD sensor (1), the output terminal output trigger pip of comparer (9) is given the input end D of trigger (10), the forward output terminal Q and the inverse output terminal Q of this trigger (10) export read control signal and write control signal respectively, and the forward output terminal Q of trigger (10) also exports described look-at-me.

3, ccd data collection and the treating apparatus that is used for high-speed displacement measuring according to claim 2, it is characterized in that: described line array CCD sensor (1) is converted to signal charge with outside incident light, and export to the input end AIN of described A/D change-over circuit (2) one by one by pixel, the clock end CLK of A/D change-over circuit (2) and output enable end OE receive the reset pulse RS of described drive clock circuit (6) output respectively and shift pulse SH, the digital output end D1 of A/D change-over circuit (2)～D8 output digital signal is given input end D0～D7 of described data cache FIFO (3), and the output terminal Q0 of this data cache FIFO (3)～Q7 output pixel signal is given described signal processing circuit (4); The input end of clock RCLK that reads of described data cache FIFO (3) receives the clock signal that described signal processing circuit (4) is exported, write input end of clock WCLK and accept the pulse RS ' of described drive clock circuit (6) output pulse RS after reverse, the full flag terminal FF of data cache FIFO (3) and the full spacing wave of empty flag terminal EF output are given described signal processing circuit (4), this data cache FIFO (3) is provided with and reads Enable Pin REN and receive described trigger (10) forward output terminal Q and export described read control signal, is provided with to write Enable Pin WEN and receive described trigger (10) inverse output terminal Q and export described write control signal.

4, ccd data collection and the treating apparatus that is used for high-speed displacement measuring according to claim 3, it is characterized in that: described signal processing circuit (4) is made up of level translator (11) and signal processor DSP (12), wherein the input end 1B1～1B8 of level translator (11) accepts the pixel signal of described data cache FIFO (3) output, and is exported to input end GPIOA0～GPIOA7 of described signal processor DSP (12) by output terminal 1A1～1A8; The input end 2B1 of level translator (11) receives the full signal of the full flag terminal FF of described data cache FIFO (3), input end 2B2 receives the spacing wave of the empty flag terminal EF of described data cache FIFO (3), and is exported to input end GPIOA8 and the GPIOA9 of described signal processor DSP (12) respectively by output terminal 2A1 and 2A2; Signal processor DSP (12) is provided with clock signal terminal RCLK clock signal and the look-at-me that broken ends of fractured bone XNMI in the non-shielding receives described trigger (10) output is set for described data cache FIFO (3), signal processor DSP (12).

5, ccd data collection and the treating apparatus that is used for high-speed displacement measuring according to claim 4 is characterized in that: the signal processor DSP (12) in the described signal processing circuit (4) is provided with:

Be used for the initialized device of DSP;

The device that is used for setting threshold;

The device that is used for the starting impulse counting;

Be used to judge whether that comparer screens the device of the look-at-me of circuit (5) output,

If there is not look-at-me, then return and describedly be used to judge whether that the device of the look-at-me of comparer screening circuit (5) output judges once more,

If look-at-me is arranged, then enter the device that is used to latch the pixel counter;

Be used for reading the device of described data cache FIFO (3) data;

The device that is used for data processing and result of calculation;

The device that is used for result's output.

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