CN105790763A - Six-channel analog to digital conversion module based on PC104 bus - Google Patents
Six-channel analog to digital conversion module based on PC104 bus Download PDFInfo
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- CN105790763A CN105790763A CN201410802509.8A CN201410802509A CN105790763A CN 105790763 A CN105790763 A CN 105790763A CN 201410802509 A CN201410802509 A CN 201410802509A CN 105790763 A CN105790763 A CN 105790763A
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Abstract
The invention provides a six-channel analog to digital conversion module based on a PC104 bus. The six-channel analog to digital conversion module mainly consists of a signal conditioning circuit, a multi-channel analog switch, an A/D analog to digital converter with a sampling holder, a data cache (FIFO) latch, a PC 104 control board and a CPLD. Wherein, an A/D conversion chip is an AD574 chip, the FIFO adopts a CY7C4231 chip of the CYPRESS company, and the latch adopts a 74LS373 chip. A clock of the analog to digital converter is obtained from a system clock signal provided by a CPU board of a PC/104 after carrying out CPLD frequency division, and the start and stop of the A/D conversion module are controlled by the CPLD easily. Moreover, under the control of the CPLD, a plurality of channels are circularly sampled for one time, sampling values and channel numbers are simultaneously transmitted into the FIFO, and after the sampling, the CPU can directly read out data from the FIFO according to timer interruption, reset the FIFO device after reading the data and open the clock of the A/D conversion module generated in the CPLD to carry out the next turn of sampling.
Description
Technical field
The present invention relates to a kind of analog and digital signal modular converter, adopt PC104 bus as the clematis stem road analog-to-digital conversion module of communication mode particularly to a kind of.
Background technology
The task of data collecting system is exactly that the analogue signal gathering sensor output converts the digital signal that computer can recognise that to, it is then fed into computer, the data obtained by computer display or print, thus realizing the supervision to some physical quantity, a portion data also will be used for controlling some physical quantity by the computer control system in production process.The quality of data collecting system performance, depends primarily on the accuracy and speed of its conversion data.When ensureing precision, should there is sample rate high as far as possible, to meet Real-time Collection, in real time process and to control the requirement [1] to sample rate in real time.
The sampling rate of data collecting system, resolution, precision, interface and capacity of resisting disturbance etc. are proposed increasingly higher requirement by the development of contemporary scientific technology, and many fields require have high-precision A/D conversion and process function in real time more and more.Meanwhile, market is to supporting that the requirement of more complicated display and communication interface is also improving, such as environmental monitoring, ammeter, armarium, portable data acquisition and industrial sensor and Industry Control etc..Adopt the PC/104 scheme controlled herein, by hardware controls A/D conversion and data storage, improve signals collecting precision and the disposal ability of system to greatest extent.
Wherein PC/104 bus forms with pin hole stack manner, has the advantage such as compact conformation, good, the low-power consumption of shock resistance, it is also possible to be operated under severe working environment, compatible with PCI standard, is suitable to high speed data transfer.And he also has the advantage such as high reliability and multiple operating system support, him is made to be applied widely in data collecting systems such as radar, sonar, Industry Control.FIFO is the data buffer of a kind of first in first out, performance for improving system is critically important, it is possible to continuous print data are flow to row cache, it is prevented that lose data when entering machine and storage operation, and data are to put together to store, it is possible to offloading the CPU.CPLD (CPLD) because of its belong to extensive in-system programmable components special IC and also have high density, at high speed, the feature such as high reliability.Therefore CPLD is applied to high--speed multi--channel data acquisition system and is greatly improved the motility of system design, improves the autgmentability of system.This A/D changes acquisition system Based PC/104 bus, as long as therefore supporting mainboard CPU each functional circuit such as through bus this data collecting system direct-connected of PC/104 bus.
Summary of the invention
Volume is little, cost is low, reliability is high, life-span length, detail programming convenient to it is an object of the invention to provide one, is equipped with the board of difference in functionality, provides the clematis stem road analog-to-digital conversion module of the system platform of standard for Embedded Application.
The object of the present invention is achieved like this:
A kind of clematis stem road analog-to-digital conversion module of Based PC 104 bus, its composition includes: signal conditioning circuit, multiway analog switch, form with the A/D analog-digital converter of sampling holder, data buffer storage (FIFO), latch and PC104 panel and CPLD, wherein A/D conversion chip adopts AD574 chip, FIFO adopts the CY7C4231 chip of CYPRESS company, latch adopts 74LS373 chip, and the CPLD playing logical block central role adopts the ispLSI1016 chip serial for ispLSI of Lattice company.
The clematis stem road analog-to-digital conversion module of described a kind of Based PC 104 bus, it is characterized in that being integrated with abundant signal condition function in module, signal condition is that the analogue signal carrying out sensor is transformed to for data acquisition, control process, performs to calculate the digital signal showing reading and other purposes.Analog sensor can measure a lot of physical quantity, such as temperature, pressure, power, flow, motion, position, PH, light intensity.
The clematis stem road analog-to-digital conversion module of described a kind of Based PC 104 bus, is characterized in that multichannel analog signals that sensor the exports radio-frequency component in signal conditioning circuit, elimination signal, and makes follow-up A/D sampling meet sampling thheorem.
The clematis stem road analog-to-digital conversion module of described a kind of Based PC 104 bus, it is characterized in that in native system, connect ispLSI1016 chip in circuit and mainly have two parts effect: first, control to analog switch H1508, by producing address signal A0, A1 and the A2 of analog switch, meanwhile, enable signal to be controlled by A4；Second, the control to the read-write of FIFO, it is necessary to assure not losing of the complete and write signal of read signal.
Data collecting system in the present invention is mainly by signal conditioning circuit, multiway analog switch, form with the A/D analog-digital converter of sampling holder, data buffer storage (FIFO), latch and PC104 panel and CPLD.Wherein A/D conversion chip adopts AD574 chip, and FIFO adopts the CY7C4231 chip of CYPRESS company, and latch adopts 74LS373 chip, and the CPLD of a logical block central role adopts the ispLSI1016 chip of the ispLSI series of Lattice company.
Being integrated with abundant signal condition function in this module, signal condition is that the analogue signal carrying out sensor is transformed to for data acquisition, control process, performs to calculate the digital signal showing reading and other purposes.Analog sensor can measure a lot of physical quantity, such as temperature, pressure, power, flow, motion, position, PH, light intensity etc..Generally, sensor signal can not be converted directly into numerical data, this is because sensor output is fairly small voltage, electric current or resistance variations.Therefore, must nurse one's health before transform data.Conditioning is amplified exactly, cushions or demarcates analogue signal so that it is being suitable for the input of A/D converter.Then, analogue signal is digitized by ADC, and digital signal is delivered to microcontroller or other digital devices, in order to the data for system process.
The multichannel analog signals of sensor output radio-frequency component in signal conditioning circuit, elimination signal, and make follow-up A/D sampling meet sampling thheorem.Pretreated signal enters No. six analog-digital converters, after A/D conversion, becomes digital signal, is stored in FIFO, reads data again through CPU.The clock signal of system that the clock of analog-digital converter is provided by the CPU board of PC/104 obtains after CPLD divides, and the startup of A/D modular converter and stopping are easily via CPLD control.And under the control of CPLD, multiple channel cycle are sampled once, and sampled value and channel number are simultaneously fed in FIFO, after having sampled, CPU directly can read data according to Interruption from FIFO, run through reset FIFO device after data, open the clock of the A/D modular converter produced in CPLD, enter next round sampling.So circulation, completes the high-speed real-time sampling of multichannel analog signals.Completely without the participation of CPU in sampling process, the data in CPU parallel processing mastery routine, improve efficiency.One piece of substrate of this partial design, PC/104 bus on cloth in the above, then the modules such as PC/104 bus module, data buffering module, latch module, A/D modular converter, CPLD are constituted a complete hardware system by stacking-type method of attachment.
In the present system, the ispLSI1016 chip connected in circuit mainly has two parts effect.First, the control to analog switch H1508, by producing address signal A0, A1 and the A2 of analog switch, meanwhile, enable signal and controlled by A4；Second, the control to the read-write of FIFO, it is necessary to assure not losing of the complete and write signal of read signal.The clock signal of AD574 produce with control input AD574 clock signal A/DCLK be by PC104 master board CPU board provide external timing signal through SYSCKL frequency dividing time delay after again with the output of an enumerator with after obtain.When the count value of enumerator has arrived the number of times of A/D module conversion in the CPU timing cycle set, enumerator stops counting, and the output EN of enumerator is from high to low, thus controlling the clock signal of A/D module.
The feature of the present invention and useful benefit:
(1) the most data acquisition application of the system module in the present invention is optimized, add abundant signal condition function, by some decoupling capacitors, the chip in circuit is carried out ground connection and connect power supply, so can improve the phenomenon that in signal, burr is many, make signal more steady, make system be more applicable for on-the-spot application, there is considerable flexibility, reliability and stability.
(2) in A/D changes, from analog input to digital output, there is the delayed of three cycles centre, and for being stored to the digital quantity in FIFO, first three should be invalid, and the 4th is only the data collected, during data in reading FIFO；In time FIFO should be zeroed out when CPU reads data in FIFO time.
Accompanying drawing explanation
Fig. 1 is principles of the invention structure chart；
Detailed description of the invention
Below in conjunction with accompanying drawing citing, the present invention is described in more detail:
A kind of clematis stem road analog-to-digital conversion module of Based PC 104 bus, its composition includes: signal conditioning circuit, multiway analog switch, form with the A/D analog-digital converter of sampling holder, data buffer storage (FIFO), latch and PC104 panel and CPLD, wherein A/D conversion chip adopts AD574 chip, FIFO adopts the CY7C4231 chip of CYPRESS company, latch adopts 74LS373 chip, and the CPLD playing logical block central role adopts the ispLSI1016 chip serial for ispLSI of Lattice company.
Being integrated with abundant signal condition function in above-mentioned module, signal condition is that the analogue signal carrying out sensor is transformed to for data acquisition, control process, performs to calculate the digital signal showing reading and other purposes.Analog sensor can measure a lot of physical quantity, such as temperature, pressure, power, flow, motion, position, PH, light intensity.
The multichannel analog signals of above-mentioned sensor output radio-frequency component in signal conditioning circuit, elimination signal, and make follow-up A/D sampling meet sampling thheorem.
In above-mentioned system, connecting ispLSI1016 chip in circuit mainly has two parts effect: first, the control to analog switch H1508, by producing address signal A0, A1 and the A2 of analog switch, meanwhile, enables signal and is controlled by A4；Second, the control to the read-write of FIFO, it is necessary to assure not losing of the complete and write signal of read signal.
It is principles of the invention structure chart in conjunction with Fig. 1, Fig. 1.Data collecting system in the present invention is mainly by signal conditioning circuit, multiway analog switch, form with the A/D analog-digital converter of sampling holder, data buffer storage (FIFO), latch and PC104 panel and CPLD.Wherein A/D conversion chip adopts AD574 chip, and FIFO adopts the CY7C4231 chip of CYPRESS company, and latch adopts 74LS373 chip, and the CPLD of a logical block central role adopts the ispLSI1016 chip of the ispLSI series of Lattice company
Being integrated with abundant signal condition function in this module, signal condition is that the analogue signal carrying out sensor is transformed to for data acquisition, control process, performs to calculate the digital signal showing reading and other purposes.Analog sensor can measure a lot of physical quantity, such as temperature, pressure, power, flow, motion, position, PH, light intensity etc..Generally, sensor signal can not be converted directly into numerical data, this is because sensor output is fairly small voltage, electric current or resistance variations.Therefore, must nurse one's health before transform data.Conditioning is amplified exactly, cushions or demarcates analogue signal so that it is being suitable for the input of A/D converter.Then, analogue signal is digitized by ADC, and digital signal is delivered to microcontroller or other digital devices, in order to the data for system process.
The multichannel analog signals of sensor output radio-frequency component in signal conditioning circuit, elimination signal, and make follow-up A/D sampling meet sampling thheorem.Pretreated signal enters No. six analog-digital converters, after A/D conversion, becomes digital signal, is stored in FIFO, reads data again through CPU.The clock signal of system that the clock of analog-digital converter is provided by the CPU board of PC/104 obtains after CPLD divides, and the startup of A/D modular converter and stopping are easily via CPLD control.And under the control of CPLD, multiple channel cycle are sampled once, and sampled value and channel number are simultaneously fed in FIFO, after having sampled, CPU directly can read data according to Interruption from FIFO, run through reset FIFO device after data, open the clock of the A/D modular converter produced in CPLD, enter next round sampling.So circulation, completes the high-speed real-time sampling of multichannel analog signals.Completely without the participation of CPU in sampling process, the data in CPU parallel processing mastery routine, improve efficiency.One piece of substrate of this partial design, PC/104 bus on cloth in the above, then the modules such as PC/104 bus module, data buffering module, latch module, A/D modular converter, CPLD are constituted a complete hardware system by stacking-type method of attachment.
Claims (4)
1. the clematis stem road analog-to-digital conversion module of Based PC 104 bus, its composition includes: signal conditioning circuit, multiway analog switch, form with the A/D analog-digital converter of sampling holder, data buffer storage (FIFO), latch and PC104 panel and CPLD, wherein A/D conversion chip adopts AD574 chip, FIFO adopts the CY7C4231 chip of CYPRESS company, latch adopts 74LS373 chip, and the CPLD playing logical block central role adopts the ispLSI1016 chip serial for ispLSI of Lattice company.
2. the clematis stem road analog-to-digital conversion module of a kind of Based PC 104 bus according to claim 1, it is characterized in that being integrated with abundant signal condition function in module, signal condition is that the analogue signal carrying out sensor is transformed to for data acquisition, control process, performs to calculate the digital signal showing reading and other purposes.Analog sensor can measure a lot of physical quantity, such as temperature, pressure, power, flow, motion, position, PH, light intensity.
3. the clematis stem road analog-to-digital conversion module of a kind of Based PC 104 bus according to claim 1, is characterized in that multichannel analog signals that sensor the exports radio-frequency component in signal conditioning circuit, elimination signal, and makes follow-up A/D sampling meet sampling thheorem.
4. the clematis stem road analog-to-digital conversion module of a kind of Based PC 104 bus according to claim 1, it is characterized in that in native system, connect ispLSI1016 chip in circuit and mainly have two parts effect: first, control to analog switch H1508, by producing address signal A0, A1 and the A2 of analog switch, meanwhile, enable signal to be controlled by A4；Second, the control to the read-write of FIFO, it is necessary to assure not losing of the complete and write signal of read signal.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106802609A (en) * | 2017-03-28 | 2017-06-06 | 河北工业大学 | The device and method of SVPWM is produced based on PC/104 buses and CPLD |
| CN106936436A (en) * | 2017-04-14 | 2017-07-07 | 湖南利能科技股份有限公司 | The multi channel signals sampling system and method for a kind of time sharing sampling |
| CN107014432A (en) * | 2017-04-12 | 2017-08-04 | 上海琪云压缩空气系统服务有限公司 | A kind of analog signal monitoring system and method |
| CN109067399A (en) * | 2018-07-26 | 2018-12-21 | 南京磐能电力科技股份有限公司 | A kind of ADC controller implementation method of multi-sampling rate |
| CN109102689A (en) * | 2018-08-20 | 2018-12-28 | 中北大学 | Pressure sensor with WIFI interface |
| CN113114254A (en) * | 2021-05-18 | 2021-07-13 | 天津凯发电气股份有限公司 | High-speed multi-channel synchronous analog quantity acquisition control method |
-
2014
- 2014-12-21 CN CN201410802509.8A patent/CN105790763A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106802609A (en) * | 2017-03-28 | 2017-06-06 | 河北工业大学 | The device and method of SVPWM is produced based on PC/104 buses and CPLD |
| CN107014432A (en) * | 2017-04-12 | 2017-08-04 | 上海琪云压缩空气系统服务有限公司 | A kind of analog signal monitoring system and method |
| CN106936436A (en) * | 2017-04-14 | 2017-07-07 | 湖南利能科技股份有限公司 | The multi channel signals sampling system and method for a kind of time sharing sampling |
| CN109067399A (en) * | 2018-07-26 | 2018-12-21 | 南京磐能电力科技股份有限公司 | A kind of ADC controller implementation method of multi-sampling rate |
| CN109067399B (en) * | 2018-07-26 | 2022-02-18 | 南京磐能电力科技股份有限公司 | Method for realizing ADC controller with multiple sampling rates |
| CN109102689A (en) * | 2018-08-20 | 2018-12-28 | 中北大学 | Pressure sensor with WIFI interface |
| CN113114254A (en) * | 2021-05-18 | 2021-07-13 | 天津凯发电气股份有限公司 | High-speed multi-channel synchronous analog quantity acquisition control method |
| CN113114254B (en) * | 2021-05-18 | 2022-08-26 | 天津凯发电气股份有限公司 | High-speed multi-channel synchronous analog quantity acquisition control method |
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Application publication date: 20160720 |