CN219496948U - High-reliability data acquisition card and data acquisition system - Google Patents

Abstract

The application discloses a high-reliability data acquisition card and a data acquisition system, comprising an FPGA module, an input module and an output module which are connected with the FPGA module, and further comprising a CPCI interface module, wherein the input module and the output module are connected with the outside through the CPCI interface module, and the FPGA module is connected with a host end through a PCI interface and the CPCI interface module in sequence; wherein, the CPCI interface module is used for performing function expansion; the FPGA module is connected with the PCI interface through a local bus, and the PCI interface is used for converting CPCI bus protocol into local bus protocol so that the host end accesses the FPGA module; the FPGA module is used for carrying out digital filtering processing on the acquired data. And the FPGA module is used for carrying out digital filtering processing on the data acquired by the input module so as to enhance the anti-interference capability of the system and improve the system precision.

Description

High-reliability data acquisition card and data acquisition system

Technical Field

The application belongs to the field of data acquisition, and particularly relates to a high-reliability data acquisition card and a data acquisition system.

Background

The data acquisition is widely applied to industries such as military, aerospace, aviation, machinery, railways and the like, and can finish tasks such as parameter collection and processing such as temperature, water level, wind speed, pressure and the like. With the informatization development of weapon systems, weapon systems are developing towards intelligence and dexterity, and the demands for capturing and collecting battlefield parameters are increasing. Meanwhile, in order to ensure that the electronic device can operate under severe environmental conditions, the design of the characteristics of miniaturization, high reliability, strong anti-interference capability and the like of the electronic device becomes particularly important. The adaptability of electronic equipment to various severe environments is still a technical problem to be solved in the field of military production, and is also a subject of continuous attention and research of design, structure and process designers of severe environment resistance.

The field working environment of the data acquisition system is generally bad, various interferences (commonly called noise) from the inside and the outside of the system are mixed, if the interferences cannot be well restrained and eliminated, the system cannot keep a normal working state, for the data acquisition system, when an input signal is very small and weak, data can be covered by the noise, the reliability of the signal is reduced, the accuracy of data acquisition can be greatly influenced, and a measured actual value and a data true value can generate no small deviation, so that a circuit cannot work normally.

Therefore, there is a need for an anti-tamper, highly reliable data acquisition device that can be adapted for use in harsh environments.

Disclosure of Invention

In order to solve the defects of the prior art, the application provides a high-reliability data acquisition card and a data acquisition system, which take an FPGA module as a core, can be suitable for CPCI bus architecture, realize the modularized design of a computer with severe environment resistance, and can improve the expansion function.

The technical effect to be achieved by the application is realized through the following scheme:

according to a first aspect of the present application, a high-reliability data acquisition card is provided, including an FPGA module, and an input module and an output module connected to the FPGA module, and further including a CPCI interface module, where the input module and the output module are both connected to the outside through the CPCI interface module, and the FPGA module is connected to the host end sequentially through a PCI interface and the CPCI interface module; wherein, the CPCI interface module is used for performing function expansion; the FPGA module is connected with the PCI interface through a local bus, and the PCI interface is used for converting CPCI bus protocol into local bus protocol so that the host end accesses the FPGA module; the FPGA module is used for carrying out digital filtering processing on the acquired data, the CPCI interface module is connected to the input module through an input signal conditioning circuit, and the input signal conditioning circuit is used for controlling the voltage of an analog signal input into the input module and filtering harmful high-frequency noise.

Preferably, the system comprises a clock circuit, wherein the clock circuit provides a 33MHz crystal oscillator clock for the FPGA module and the PCI interface.

Preferably, the input module is an analog-to-digital conversion module, the output module is a digital-to-analog conversion module, and the analog-to-digital conversion module and the digital-to-analog conversion module are respectively connected to programmable pins of the FPGA module, and the FPGA module directly controls and transmits the timing signals.

Preferably, the input module comprises two analog-to-digital conversion modules with 4 paths of input, the two analog-to-digital conversion modules are connected to the FPGA module through a shared data bus, and the FPGA module is connected to the analog-to-digital conversion modules through chip selection pins respectively for chip selection reading.

Preferably, the FPGA module is connected with a power circuit, the FPGA module supplies power to the analog-to-digital conversion module and the digital-to-analog conversion module, the FPGA module is connected to the digital-to-analog conversion module through a level conversion module, and the level conversion module is used for converting a 3.3V electrical signal into a 5V electrical signal.

Preferably, the input signal conditioning circuit includes a current/voltage conversion circuit, a signal isolation circuit, and a signal filtering circuit, wherein:

the current/voltage conversion circuit is used for converting 4-20mA current into 0-5V;

the signal isolation circuit adopts a linear optical coupling isolation circuit and is used for electric isolation;

the signal filtering circuit is used for performing first-order low-pass filtering and impedance transformation processing on the sampled voltage signal after performing optical coupling isolation on the analog signal.

Preferably, a dual-port RAM memory is provided in the FPGA module, and the dual-port RAM memory is used for latching output data converted by the FPGA module.

Preferably, an FIR digital filter is arranged in the FPGA module, and a fully-serial distributed computing module is arranged in the FIR digital filter.

According to a second aspect of the present application, a data acquisition system is provided, employing the above-described highly reliable data acquisition card.

The high-reliability data acquisition card has the technical effects that the FPGA module is adopted to carry out digital filtering processing on the data acquired by the input module, so that the anti-interference capability of the system is enhanced, and the system precision is improved; the input signal conditioning circuit is arranged, so that high-frequency noise of signals can be filtered, and the input signals can be safely processed, so that the anti-interference capability is further improved, and the safety of the data acquisition card is improved; by adopting two analog-to-digital conversion modules, the reliability of the device can be improved, the sampling efficiency can be improved, and hardware resources can be saved.

Drawings

In order to more clearly illustrate the embodiments or prior art solutions of the present application, the drawings that are required for the description of the embodiments or prior art will be briefly described below, it being apparent that the drawings in the following description are only some of the embodiments described in the present application, and that other drawings may be obtained according to these drawings without inventive faculty for a person skilled in the art.

FIG. 1 is a block diagram of a high reliability data acquisition card according to one embodiment of the present application;

fig. 2 is a schematic diagram of a connection structure between a CPCI interface module and an FPGA module in an embodiment of the present application;

FIG. 3 is a schematic diagram of a connection structure between an input module and an FPGA module according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a signal isolation circuit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a signal filtering circuit according to an embodiment of the present disclosure;

FIG. 6 is a schematic circuit diagram of an output module according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a level shift module according to an embodiment of the present application;

FIG. 8 is a flow chart of the internal logic of the FPGA module in one embodiment of the present application.

Detailed Description

For the purposes, technical solutions and advantages of the present application, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

As shown in fig. 1, the high-reliability data acquisition card in an embodiment of the present application includes an FPGA module 100, an input module 210 and an output module 220 connected to the FPGA module 100, and further includes a CPCI interface module 320, where the input module 210 and the output module 220 are connected to the outside through the CPCI interface module 320, and the FPGA module 100 is connected to the host through the PCI interface 310 and the CPCI interface module 320 in sequence; wherein, CPCI interface module 320 is used for performing function expansion; the FPGA module 100 is connected with the PCI interface 310 through a local bus, and the PCI interface 310 is configured to convert CPCI bus protocol into a local bus protocol, so that the host accesses the FPGA module 100; the FPGA module 100 is configured to perform digital filtering processing on the acquired data.

The FPGA module 100 in this embodiment is a core module of the present board card, and is responsible for digital logic control of the entire system. The clock circuit provides a 33MHz crystal oscillator clock for FPGA module 100 and PCI interface 310.

As shown in fig. 2, in an embodiment of the present application, the CPCI interface module 320 is connected to a host (upper computer), and the PCI interface bridge chip in the PCI interface 310 can convert CPCI bus protocol into local bus protocol, so as to realize the upper computer accessing to the FPGA module 100.

In this embodiment, the PCI interface bridge chip is PCI9030, and the PCI9030 is connected to the host side through a 33MHz and 32-bit PCI bus, and may be connected to the FPGA module 100 through a local bus. When the upper computer is to access the data acquisition card, the PCI interface bridge chip is used for mapping the PCI address into a local address, the local address is connected with the FPGA module 100, and then the data acquisition card is accessed through comprehensive processing control of the FPGA module 100.

In an embodiment of the present application, the CPCI interface module 320 is connected to the input module 210 through the input signal conditioning circuit 230, and performs a conditioning function on the input current-voltage signal, where the function of the input signal conditioning circuit 230 is specifically implemented in two aspects:

firstly, the voltage requirement of the input module 210 on the collected analog signals is met, the input voltage which can be received by the input module 210 is within a certain range, the input module 210 can be damaged if the input signal is too large, and the resolution of the input module 210 can not be fully utilized if the input signal is too small;

second, for analog signals, some ripple and noise signals are mixed in during the process of introducing the operational amplifier, so the input signal conditioning circuit 230 can filter out the harmful high-frequency noise in the sampling circuit when the signal is input, and a low-pass filter is also required to filter out the high-frequency noise introduced in the operational amplifier after the signal is output from the operational amplifier.

The input signal conditioning circuit 230 includes a current/voltage conversion circuit, a signal isolation circuit, and a signal filtering circuit, wherein:

the current loop receiver RCV420 selected by the current/voltage conversion circuit can allow the current to pass through the current loop receiver RCV420 within the range of 4-20mA, the voltage drop is smaller and is 1.5V, the requirement on the source end is not high, and 0-5V is directly output, so that the further processing of the back-end circuit is facilitated;

as shown in fig. 4, the signal isolation circuit adopts a linear optical coupler isolation circuit for electrical isolation, the linear optical coupler isolation circuit changes a single-shot mode relative to a common optical coupler, an optical receiving circuit for feedback is added, nonlinearities of the two optical receiving circuits keep relatively good consistency, and nonlinearity characteristics of a direct current path can be counteracted by the nonlinearity characteristics of the added optical receiving circuit, so that the design of the circuit achieves the purpose of linear isolation;

as shown in fig. 5, the low-pass filter circuit is configured to perform first-order low-pass filtering and impedance transformation processing on the sampled voltage signal after performing optical coupling isolation on the analog signal. The operational amplifier is used for completing impedance transformation and voltage following, the low-pass filtering is completed by an RC filter circuit, and a group of the low-pass filtering is respectively arranged at the front stage and the rear stage of the operational amplifier. The operational amplifier has low input bias current and high input impedance, so that the front and back stage circuits are not affected. An operational amplifier OP177AZ from ADI company is selected. Its input offset voltage is 4 μV, noise voltage is 118nV and common mode rejection ratio is very high.

Through the current loop receiving circuit, the optical coupler isolation circuit and the impedance matching circuit, signals before entering the analog-digital acquisition end are conditioned, and interference such as interference noise is well suppressed.

In this embodiment, the input module 210 is an analog-to-digital conversion module, the output module 220 is a digital-to-analog conversion module, and the pins of the FPGA are divided into two parts, i.e., dedicated pins and programmable pins. The special pins are used for circuits such as a clock circuit, a configuration circuit, a power circuit and the like; programmable pins are used to autonomously define as input, output, or bi-directional pins, etc. to implement program functions. The FPGA module 100 communicates with the PCI interface 310 and responds to a read-write command sent by the upper computer; the analog-to-digital conversion module and the digital-to-analog conversion module are directly controlled to generate time sequence signals required by the operation of the analog-to-digital conversion module and the digital-to-analog conversion module; the acquired data is subjected to digital filtering processing so as to enhance the anti-interference capability of the system and improve the system precision.

The FPGA module 100 is connected with a power circuit, and the FPGA module 100 supplies power to the analog-to-digital conversion module and the digital-to-analog conversion module.

As shown in fig. 3, the input module 210 in an embodiment of the present application includes two analog-to-digital conversion modules with 4 paths of inputs, which are responsible for converting the collected analog signals into digital signals that can be identified by a computer, and then analyzing and processing the digital signals, and finally converting the results of the digital signals into analog signals by the digital-to-analog conversion module so as to drive the executing mechanism.

The A/D chip in the analog-to-digital conversion module in the embodiment adopts an AD7865 chip, 8 paths of analog current signals are firstly converted into 0-5V voltage signals meeting the range requirement of the A/D chip in the digital-to-analog conversion module through the input signal conditioning circuit 230, and the voltage signals are isolated and filtered before entering the digital-to-analog conversion module (ADC). After processing, a relatively pure voltage signal is obtained as input to the ADC. Analog to digital conversion is performed by two ADCs. According to the characteristics of the AD7865 chip, the data bus is output tri-state, so that the data bus is shared, and the converted data is output to the FPGA module 100 through the data bus.

AD7865 samples 8 paths of input signals simultaneously and converts the signals in sequence; the number of conversion channels can be flexibly selected. In this embodiment, a hardware gating mode is adopted. The FPGA module 100 controls the rotational acquisition of the two ADs 7865. The two AD7865 chips share the data bus, when the FPGA sends out a reading instruction to one AD7865 chip, the other AD7865 chip is subjected to instruction conversion operation, so that the sampling efficiency is improved, and the two chips are adopted to replace the two boards, so that hardware resources can be saved.

The reliability of the board card can be improved through the multiple sampling chips, when one AD7865 chip fails, the other AD7865 chip can be driven to work, equipment is prevented from stopping running, and enough time is reserved for maintenance.

The digital-to-analog conversion module in one embodiment of the present application is used to convert discrete digital signals into continuously variable analog signals. The converted analog signals can drive the external actuator.

As shown in fig. 6, in this embodiment, the DAC chip in the DAC module is a DAC7724, and the DAC7724 has two different operating states depending on the power supply mode of external power supply. When it is the reference voltage pin V _REFH When +10V voltage is provided, output of 0-10V voltage can be achieved through the DAC 7724. In order to realize + -10V voltage output, +10V and-10V voltages are respectively connected to a reference voltage pin V of the DAC7724 chip _REFH And V _REFL 。

As shown in fig. 7, the FPGA chip adopted in the present embodiment is a 3.3VLVTTL (low voltage TTL) level standard, and the level signal required by the DAC7724 is 5V, so the FPGA module 100 needs to add a level conversion module before transmitting the digital signal to the DAC module; the level conversion module in this embodiment is SN74LVCH16T245DGGR, which converts the signal level of the FPGA module 100 from 3.3V to 5V.

The FPGA module 100 in this embodiment is provided with a dual-port RAM memory, and the dual-port RAM memory is used for latching output data converted by the FPGA module 100.

In an embodiment of the present application, an FIR digital filter is provided in the FPGA module 100, and a full-serial distributed computing module is provided in the FIR digital filter.

The FIR digital filter is formed by parameter setting by adopting an own FIR filter IP core in the FPGA module 100, the IP core is mature, the sampling precision is high, and compared with the traditional DSP filter design method, the method is simpler, more convenient and flexible, and the design period is obviously shortened.

The FIR digital filter in this embodiment is designed by using a window function method, and the window function is a hamming window, and compared with a window function commonly used in projects such as a rectangular window, a hamming window, a hanning window and a brakeman window, the transition zone of the hamming window is similar to the hanning window in width, but the sidelobe amplitude of the hamming window is smaller, so that the performance of the hamming window is better than that of the hanning window, the attenuation amplitude of the brakeman window is small, and the blocking of the high-frequency component of the low-pass filter is not facilitated. The present embodiment therefore uses a hamming window as the window function for digital filtering algorithm processing.

In the program algorithm of the FPGA module 100, a distributed algorithm is adopted, so that the hardware circuit scale is reduced, the pipeline processing is easy to realize, and the operation speed of the system is improved. When the multiply-add function is completed, a miscalculation result is generated by each bit corresponding to each input data, the addition is performed in advance to form a corresponding partial product, and then the partial products are accumulated to form a final result. And a full serial structure is adopted to further reduce the occupied resources. Besides the digital filter algorithm, the FPGA also needs to complete other control and protocol processing, so that the utilization rate of FPGA resources is high.

The internal workflow diagram of FPGA module 100 is shown in fig. 8:

the system is powered on and reset, the BUSY signal is inquired, the BUSY signal is used for indicating the end of A/D data conversion, if the BUSY signal is found, an AD chip selection signal is sent, an AD7865 specific chip is selected, analog-to-digital conversion is carried out after the data acquisition signal is received, an instruction is sent when the A/D data conversion is completed, the data after the A/D conversion is output and latched, and the data is stored in a double-port RAM memory in the FPGA.

The FPGA module 100 queries the enable signal and the write signal through the local bus of the PCI9030, the upper computer places the mode configuration into a 0x01 register, and the FPGA module 100 reads the content from the register, and the corresponding content is a/D conversion. When the a/D conversion is finished, the data corresponding to the digital quantity is put into the 0x01 register, and the PCI9030 read-write rate is faster than the AD7865 analog-to-digital conversion rate, so that the dual-port RAM memory of the FPGA module 100 can be used as a buffer space for the content of the input data. When the upper computer sends a query instruction of a read signal, reading data at a corresponding address in the dual-port RAM memory, performing digital filtering processing, and transmitting the processed value to the PCI interface 310 through a data line so as to be transmitted to the upper computer; when the address read by the FPGA module 100 is not 0x01, the next step is to determine, if the register address is 0x02, the FPGA module 100 reads the corresponding data in the dual-port RAM memory, so that DA output control can be performed.

According to a second aspect of the present application, a data acquisition system is provided, employing the above-described highly reliable data acquisition card.

The high-reliability data acquisition card has the technical effects that the FPGA module 100 is adopted to carry out digital filtering processing on the data acquired by the input module, so that the anti-interference capability of the system is enhanced, and the system precision is improved; the input signal conditioning circuit is arranged, so that high-frequency noise of signals can be filtered, and the input signals can be safely processed, so that the anti-interference capability is further improved, and the safety of the data acquisition card is improved; by adopting two analog-to-digital conversion modules, the reliability of the device can be improved, the sampling efficiency can be improved, and hardware resources can be saved.

It should be noted that the foregoing detailed description is exemplary and is intended to provide further explanation of the utility model. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. Furthermore, it will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components, and/or groups thereof.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or otherwise described herein.

Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways, such as rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein interpreted accordingly.

In the above detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, like numerals typically identify like components unless context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.

The above is only a preferred embodiment of the present utility model, and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims (9)

1. The high-reliability data acquisition card comprises an FPGA module, an input module and an output module, wherein the input module and the output module are connected with the FPGA module, and the high-reliability data acquisition card is characterized by further comprising a CPCI interface module, wherein the input module and the output module are connected with the outside through the CPCI interface module, and the FPGA module is connected with a host end through a PCI interface and the CPCI interface module in sequence; wherein, the CPCI interface module is used for performing function expansion; the FPGA module is connected with the PCI interface through a local bus, and the PCI interface is used for converting CPCI bus protocol into local bus protocol so that the host end accesses the FPGA module; the FPGA module is used for carrying out digital filtering processing on the acquired data, the CPCI interface module is connected to the input module through an input signal conditioning circuit, and the input signal conditioning circuit is used for controlling the voltage of an analog signal input into the input module and filtering harmful high-frequency noise.

2. The high reliability data acquisition card of claim 1 comprising a clock circuit that provides a 33MHz crystal oscillator clock for the FPGA module and the PCI interface.

3. The high-reliability data acquisition card of claim 1, wherein the input module is an analog-to-digital conversion module, the output module is a digital-to-analog conversion module, and the analog-to-digital conversion module and the digital-to-analog conversion module are respectively connected to programmable pins of the FPGA module and are directly controlled and send timing signals by the FPGA module.

4. The high-reliability data acquisition card of claim 3 wherein the input module comprises two 4-way input analog-to-digital conversion modules, the two analog-to-digital conversion modules being connected to the FPGA module by a common data bus, the FPGA module being connected to the analog-to-digital conversion modules by chip select pins, respectively, for chip select reading.

5. The high-reliability data acquisition card of claim 3, wherein the FPGA module is connected with a power circuit, the FPGA module supplies power to the analog-to-digital conversion module and the digital-to-analog conversion module, the FPGA module is connected to the digital-to-analog conversion module through a level conversion module, and the level conversion module is used for converting 3.3V electrical signals into 5V electrical signals.

6. The high reliability data acquisition card of claim 1 wherein the input signal conditioning circuit comprises a current/voltage conversion circuit, a signal isolation circuit, and a signal filtering circuit, wherein:

the current/voltage conversion circuit is used for converting 4-20mA current into 0-5V;

the signal isolation circuit adopts a linear optical coupling isolation circuit and is used for electric isolation;

the signal filtering circuit is used for performing first-order low-pass filtering and impedance transformation processing on the sampled voltage signal after performing optical coupling isolation on the analog signal.

7. The high-reliability data acquisition card according to claim 1, wherein a dual-port RAM memory is provided in the FPGA module, and the dual-port RAM memory is used for latching output data converted by the FPGA module.

8. The high-reliability data acquisition card of claim 1, wherein an FIR digital filter is arranged in the FPGA module, and a fully serial distributed computing module is arranged in the FIR digital filter.

9. A data acquisition system employing the highly reliable data acquisition card of any one of claims 1 to 8.