CN216486052U

CN216486052U - High-speed data acquisition module

Info

Publication number: CN216486052U
Application number: CN202122751334.0U
Authority: CN
Inventors: 罗白剑; 刘全敬
Original assignee: Guangxi Baoye Information Technology Co ltd
Current assignee: Guangxi Baoye Information Technology Co ltd
Priority date: 2021-11-11
Filing date: 2021-11-11
Publication date: 2022-05-10
Anticipated expiration: 2031-11-11

Abstract

The utility model relates to a high-speed data acquisition module, which solves the technical problem of low precision and comprises a signal conditioning unit for converting a single-end signal into a differential signal, wherein the signal conditioning unit is connected with n paths of ADC units, and 4 paths of ADC units are connected with a clock distribution unit and an FPGA unit; the FPGA unit controls n paths of ADC units to sample alternately through the clock unit; the output of the FPGA unit is connected with an FIFO memory; the output end of the signal conditioning unit is connected with the positive input end of the operational amplifier unit, the negative input end of the operational amplifier unit is connected with the capacitor C1 after being in short circuit with the output end, and the capacitor C1 is directly connected with the input end of the ADC unit; the technical scheme that n is an even number greater than or equal to 2 solves the problem well and can be used for data acquisition.

Description

High-speed data acquisition module

Technical Field

The utility model relates to the field of data acquisition, in particular to a high-speed data acquisition module.

Background

Data Acquisition (DAQ) refers to automatically acquiring non-electric quantity or electric quantity signals from analog and digital units to be tested, such as sensors and other devices to be tested, and sending the signals to an upper computer for analysis and processing. The data acquisition system is a flexible and user-defined measurement system implemented in conjunction with computer-based or other specialized test platform-based measurement software and hardware products.

The existing high-speed data acquisition module mostly adopts a signal conditioning unit to convert a single-ended signal into a differential signal, and then a controller is used for alternately controlling a plurality of ADC sampling units for control. However, the ADC sampling unit samples a terminal time after the CLK clock stabilizes the terminal time after the rising edge, and outputs the sample after the terminal time is stabilized. This creates a problem that channel crosstalk is likely to occur in the acquired waveform when the ADC chip is directly externally connected under the condition that the sampling period limits the control time.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem of poor sampling precision in the prior art. The high-speed data acquisition module has the characteristic of high sampling accuracy.

In order to solve the technical problems, the technical scheme is as follows:

a high-speed data acquisition module comprises a signal conditioning unit for converting a single-end signal into a differential signal, wherein the signal conditioning unit is connected with n paths of ADC units, and 4 paths of ADC units are connected with a clock distribution unit and an FPGA unit; the FPGA unit controls n paths of ADC units to sample alternately through the clock unit; the output of the FPGA unit is connected with the FIFO memory;

the output end of the signal conditioning unit is connected with the positive input end of the operational amplifier unit, the negative input end of the operational amplifier unit is connected with the capacitor R1 after being in short circuit with the output end, and the capacitor R1 is directly connected with the input end of the ADC unit; wherein n is an even number greater than or equal to 2.

When the FPGA controls multi-channel A/D acquisition, channel switching is firstly carried out, a period of time is kept, A/D acquisition is carried out when signals are stable, then a period of time is kept, and data are transmitted to an FIFO memory after A/D conversion is finished. The utility model adds the operational amplifier unit at the front end of the ADC unit for voltage following, and simultaneously disconnects the input end from the grounding end when the existing peripheral circuit of the ADC unit is adopted, and does not connect a resistor according to the suggestion of a manufacturer. Through experimental comparison, the signal ripple is eliminated, and the acquisition precision is improved.

In the above-mentioned scheme, for optimization, further, n is 2 × m, m is an even number greater than 2, the n-way operational amplifier units are controlled by the switch array, and the switch array gates the 2-way operational amplifier units at the same time to start the corresponding ADC units for sampling; and n average value calculation units are connected between the FPGA and the FIFO memory.

The preferred scheme further improves the sampling precision, when alternative sampling is carried out, 2 ADC sampling units are randomly gated through the switch array to carry out simultaneous sampling, and at the next alternative moment, 2 ADC sampling units are selected to carry out sampling simultaneously, so that a plurality of sampling data exist at the same moment. After the processing by the average calculator, the sampled values of the weighted average are transmitted as output values into a FIFO memory (first-in first-out memory) used in the prior art. The switch array can also play a role in protecting the ADC sampling unit.

Furthermore, the high-speed data acquisition module also comprises a power supply unit for supplying power to the ADC unit, the power supply unit comprises an integrated power supply chip NCP1086, and a VIN pin of the integrated power supply chip NCP1086 is connected in parallel with a capacitor C2, a resistor R1, a diode D1, a capacitor C1 and the ground and is also connected with a VCC voltage end; the Adj pin of the integrated power supply chip NCP1086 is connected with a resistor R2 and a capacitor C3 in parallel to the ground, and a resistor R3 is connected to the VOUT end of the integrated power supply chip NCP 1086; the VOUT end of the integrated power supply chip NCP1086 is connected with a resistor R3 and a capacitor C4 in parallel to the ground, the R5 is connected to the VDR end, and the R6 is connected to the VA end.

The power supply unit provided by the utility model has lower power consumption, when the sampling rate is 500MSPS, the consumed current is less than 1A, and the power is only 1.4W.

Further, the ADC unit is ADC08D 500.

Further, the operational amplifier unit is LM 2902.

The utility model has the beneficial effects that: the utility model adds the operational amplifier unit at the front end of the ADC unit for voltage following, and simultaneously disconnects the input end from the grounding end when the existing peripheral circuit of the ADC unit is adopted, and does not connect a resistor according to the suggestion of a manufacturer. Through experimental comparison, the signal ripple is eliminated, and the acquisition precision is improved. When alternate sampling is carried out, 2 ADC sampling units are randomly gated through the switch array to carry out simultaneous sampling, and at the next alternate moment, 2 ADC sampling units are selected to carry out simultaneous sampling, so that a plurality of sampling data exist at the same moment. After the processing by the average calculator, the sampled values of the weighted average are transmitted as output values into a FIFO memory (first-in first-out memory) used in the prior art. The switch array can also play a role in protecting the ADC sampling unit.

Drawings

The utility model is further illustrated with reference to the following figures and examples.

Fig. 1 is a schematic diagram of a high-speed data acquisition module in an embodiment.

Fig. 2 is a schematic diagram of a prior art sampling waveform.

Fig. 3 is a schematic diagram of a sampling waveform of the present embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.

Example 1

The embodiment provides a high-speed data acquisition module, as shown in fig. 1, the high-speed data acquisition module includes a signal conditioning unit for converting a single-end signal into a differential signal, the signal conditioning unit is connected with n-channel ADC units, and 4-channel ADC units are connected with a clock distribution unit and an FPGA unit; the FPGA unit controls n paths of ADC units to sample alternately through the clock unit; the output of the FPGA unit is connected with the FIFO memory;

When the FPGA controls multi-channel A/D acquisition, channel switching is firstly carried out, a period of time is kept, A/D acquisition is carried out when signals are stable, then a period of time is kept, and data are transmitted to an FIFO memory after A/D conversion is finished. In the embodiment, the operational amplifier unit is added at the front end of the ADC unit for voltage following, and meanwhile, when the conventional ADC unit peripheral circuit is adopted, the input end and the grounding end are disconnected, and the connecting resistor is not provided according to the suggestion of a manufacturer. Through experimental comparison, the signal ripple is eliminated, and the acquisition precision is improved. As shown in fig. 2, which is a prior art acquisition pattern, and fig. 3, which is the present embodiment, it can be seen that signal ripples are eliminated, and the accuracy is improved.

Preferably, n is 2 × m, m is an even number greater than 2, the n-way operational amplifier units are controlled by the switch array, and the switch array gates the 2-way operational amplifier units at the same time to start the corresponding ADC units for sampling; and n average value calculation units are connected between the FPGA and the FIFO memory.

Preferably, the high-speed data acquisition module further comprises a power supply unit for supplying power to the ADC unit, the power supply unit comprises an integrated power chip NCP1086, a VIN pin of the integrated power chip NCP1086 is connected in parallel with a capacitor C2, a resistor R1, a diode D1, a capacitor C1 to ground, and is connected to a VCC voltage terminal; the Adj pin of the integrated power supply chip NCP1086 is connected with a resistor R2 and a capacitor C3 in parallel to the ground, and a resistor R3 is connected to the VOUT end of the integrated power supply chip NCP 1086; the VOUT end of the integrated power supply chip NCP1086 is connected with a resistor R3 and a capacitor C4 in parallel to the ground, the R5 is connected to the VDR end, and the R6 is connected to the VA end.

The power consumption of the power supply unit provided by the embodiment is relatively low, when the sampling rate is 500MSPS, the consumed current is less than 1A, and the power is only 1.4W.

Specifically, the ADC unit is ADC08D 500.

Specifically, the operational amplifier unit is LM 2902.

In the embodiment, the operational amplifier unit is added at the front end of the ADC unit for voltage following, and meanwhile, when the conventional ADC unit peripheral circuit is adopted, the input end and the grounding end are disconnected, and the connecting resistor is not provided according to the suggestion of a manufacturer. Through experimental comparison, the signal ripple is eliminated, and the acquisition precision is improved. When alternate sampling is carried out, 2 ADC sampling units are randomly gated through the switch array to carry out simultaneous sampling, and at the next alternate moment, 2 ADC sampling units are selected to carry out simultaneous sampling, so that a plurality of sampling data exist at the same moment. After the processing by the average calculator, the sampled values of the weighted average are transmitted as output values into a FIFO memory (first-in first-out memory) used in the prior art. The switch array can also play a role in protecting the ADC sampling unit.

Although the illustrative embodiments of the present invention have been described above to enable those skilled in the art to understand the present invention, the present invention is not limited to the scope of the embodiments, and it is apparent to those skilled in the art that all the utility models utilizing the inventive concept can be protected as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims.

Claims

1. A high speed data acquisition module, characterized by: the high-speed data acquisition module comprises a signal conditioning unit for converting a single-end signal into a differential signal, the signal conditioning unit is connected with n paths of ADC units, and 4 paths of ADC units are connected with a clock distribution unit and an FPGA unit; the FPGA unit controls n paths of ADC units to sample alternately through the clock unit; the output of the FPGA unit is connected with the FIFO memory;

the output end of the signal conditioning unit is connected with the positive input end of the operational amplifier unit, the negative input end of the operational amplifier unit is connected with the capacitor C1 after being in short circuit with the output end, and the capacitor C1 is directly connected with the input end of the ADC unit; wherein n is an even number greater than or equal to 2.

2. The high speed data acquisition module of claim 1, wherein: the n is 2 x m, m is an even number more than 2, the n-path operational amplifier units are controlled by the switch array, and the switch array gates the 2-path operational amplifier units at the same moment to start the corresponding ADC units for sampling; and n average value calculation units are connected between the FPGA and the FIFO memory.

3. The high speed data acquisition module of claim 1, wherein: the high-speed data acquisition module also comprises a power supply unit for supplying power to the ADC unit, the power supply unit comprises an integrated power supply chip NCP1086, and a VIN pin of the integrated power supply chip NCP1086 is connected with a capacitor C2, a resistor R1, a diode D1 and a capacitor C1 in parallel to the ground and is also connected with a VCC voltage end; the Adj pin of the integrated power supply chip NCP1086 is connected with a resistor R2 and a capacitor C3 in parallel to the ground, and a resistor R3 is connected to the VOUT end of the integrated power supply chip NCP 1086; the VOUT end of the integrated power supply chip NCP1086 is connected with a resistor R3 and a capacitor C4 in parallel to the ground, the R5 is connected to the VDR end, and the R6 is connected to the VA end.

4. The high speed data acquisition module of claim 1, wherein: the ADC unit is ADC08D 500.

5. The high speed data acquisition module of claim 1, wherein: the operational amplifier unit is LM 2902.