CN113556126A - High speed analog to digital converter module - Google Patents
High speed analog to digital converter module Download PDFInfo
- Publication number
- CN113556126A CN113556126A CN202110777509.7A CN202110777509A CN113556126A CN 113556126 A CN113556126 A CN 113556126A CN 202110777509 A CN202110777509 A CN 202110777509A CN 113556126 A CN113556126 A CN 113556126A
- Authority
- CN
- China
- Prior art keywords
- analog
- electrically connected
- input
- trigger
- acquisition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0626—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by filtering
- H03M1/0629—Anti-aliasing
Abstract
The invention discloses a high-speed analog-to-digital converter module; the digital input/output device comprises an FPGA chip, wherein a bus buffer circuit is electrically connected to the FPGA chip, a digital input/output module is electrically connected to the bus buffer circuit, a DA conversion circuit is electrically connected to the bus buffer circuit, an AD converter is electrically connected to the bus buffer circuit, a gain-controllable operational amplifier is electrically connected to the AD converter, an analog switch switching circuit is electrically connected to the gain-controllable operational amplifier, analog input protection is electrically connected to the analog switch switching circuit, another group of AD/DA calibration circuits is electrically connected to the AD converter, and the other group of AD/DA calibration circuits is electrically connected to the DA conversion circuit; the invention has the advantages of analog input, analog output, TTL digital input and output, programmable digital IO multifunctional data acquisition card, and multiple acquisition modes.
Description
Technical Field
The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a high-speed analog-to-digital converter module.
Background
An analog-to-digital converter, or ADC for short, generally refers to an electronic component that converts an analog signal into a digital signal. A typical analog-to-digital converter converts an input voltage signal into an output digital signal. Since digital signals do not have practical significance per se, only one relative magnitude is represented. Therefore, any analog-to-digital converter needs a reference analog quantity as a conversion standard, and a common reference standard is the maximum convertible signal size. The basic principle of such a converter is to sample the input analog signal at regular time intervals and compare it with a series of standard digital signals, which converge successively until the two signals are equal. The binary number representing the signal is then displayed, and a wide variety of analog-to-digital converters exist, such as direct, indirect, high speed, high precision, ultra high speed, etc. Each in many forms. In contrast to the analog-to-digital converter, which is called "digital-to-analog converter" or "decoder", which is a device for converting digital quantity into continuously variable analog quantity, there are many kinds and many forms, however, there are various problems in the analog-to-digital converters on the market.
Although a broadband-input high-speed low-power analog-to-digital converter disclosed in the publication No. CN103825614B has the characteristics of broadband input, high speed, and low power consumption, and has better flexibility and versatility, it does not solve the problems of the existing product that the fast bundle conversion and data acquisition cannot be realized, and the acquisition mode cannot be changed, and so on, and therefore we propose a high-speed analog-to-digital converter module.
Disclosure of Invention
It is an object of the present invention to provide a high speed analog to digital converter module to solve the above problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme: a high-speed analog-to-digital converter module comprises an FPGA chip, wherein a bus buffer circuit is electrically connected to the FPGA chip, a digital quantity input/output module is electrically connected to the bus buffer circuit, a panel connector is electrically connected to the digital quantity input/output module, a DA conversion circuit is electrically connected to the bus buffer circuit, the DA conversion circuit is electrically connected to the panel connector, an AD converter is electrically connected to the bus buffer circuit, a gain-controllable operational amplifier is electrically connected to the AD converter, an analog switch switching circuit is electrically connected to the gain-controllable operational amplifier, an analog quantity input protection is electrically connected to the analog switch switching circuit, the analog quantity input protection is electrically connected to the panel connector through analog quantity input, and a group of AD/DA calibration circuits is electrically connected to the analog quantity input protection, the AD converter is electrically connected with another group of AD/DA calibration circuits, the other group of AD/DA calibration circuits is electrically connected with the DA conversion circuit, and the panel connector is electrically connected with the bus buffer circuit through the PFI.
Preferably, the FPGA chip is electrically connected with an EEPROM memory module and an SDRAM memory module, and the SDRAM memory module is electrically connected with the FPGA chip through an address bus, a data bus, and a control bus.
Preferably, the FPGA chip is electrically connected with a PCI9054 bus control chip, the PCI9054 bus control chip is electrically connected with another group of EEPROM memory modules, and the PCI9054 bus control chip is in intercommunication connection with the FPGA chip through an address bus, a data bus and a control signal.
Preferably, the PCI9054 bus control chip is electrically connected with a PXI connector through an address bus, a data bus and a control signal, and the PXI connector is electrically connected with an external device.
Preferably, the analog input has 32 single-ended/16 differential configurable analog input channels, supports hybrid input, multiplexes one set of the AD converters, and controls gating through software;
when the single-end input is carried out, the ground end of a signal to be tested is connected to the public ground of the circuit board card by a lead, and the other end of the signal to be tested is connected to the corresponding input port of the circuit board card;
when 16 paths of differential input are carried out, two ends of a signal to be measured are respectively connected to two differential input channels by using conducting wires, and the voltage difference of the two input ends is measured.
Preferably, the digital input/output module is 32 TTL digital input/output channels, and the TTL digital input/output channels are standard TTL levels, and are grouped into 8 channels, and the direction is selectable.
Preferably, the triggering modes of the analog input channel include the following three modes:
A. software triggering
A user operates a corresponding register to trigger AD conversion, and the triggering is used for single acquisition;
B. external analog triggering
A circuit board card pin APFI0 is an analog-digital conversion external analog quantity trigger signal, a user sets an internal threshold voltage firstly, the threshold voltage setting is multiplexed with a digital-analog conversion pin, then an analog trigger signal of-10V- +10V is input through a pin APFI0, the analog trigger signal is compared with the threshold voltage set in the circuit board card, the circuit board card supports two trigger modes of being greater than or less than the set threshold voltage, only the edge of the analog quantity exceeding or being lower than the set threshold level is sensitive during triggering, and the trigger is used for triggering an acquisition mode;
C. external TTL trigger
The PFIn of the circuit board card is an analog-to-digital conversion external TTL digital quantity trigger signal, the circuit board card supports three trigger modes of a rising edge, a falling edge, a rising edge or a falling edge, the circuit board card is sensitive to the first edge of the TTL digital quantity only during triggering, and the triggering is used for triggering a post-acquisition mode.
Preferably, the analog input is selected by two clock types, which are as follows:
a. internal clock
The circuit board card is internally provided with a 40MHz reference clock, different clock frequencies can be obtained through frequency division, each rising edge of the clock can trigger an AD conversion device to carry out AD conversion,
a maximum of 1 MHz;
a minimum of 1 Hz;
b. external clock
TTL square wave clock signals can be introduced through a circuit board card pin PFIn, each rising edge of the clock can trigger an AD conversion device to carry out AD conversion once,
input voltage: vih (min) 2.0V, VIL (MAX) 0.8V;
input frequency: less than or equal to 1 MHz;
and the analog input provides three data acquisition modes, which are as follows:
c. single acquisition mode
The analog quantity acquisition channel acquires data in a single time by using a software trigger mode;
d. continuous acquisition mode
The analog quantity acquisition channel is based on the working mode that an internal clock or an external clock continuously acquires data, the acquisition is always carried out as long as the acquisition clock is always provided, and the acquisition is stopped when the acquisition clock is stopped;
e. post-trigger acquisition mode
And the analog quantity acquisition channel performs continuous acquisition after detecting a trigger event set based on the trigger source, and stops data acquisition manually.
Preferably, the rear end of the analog switch switching circuit is electrically connected with a PGA and an anti-aliasing filter;
the analog switch switching circuit is switched from one input channel to another channel, the PGA gain in the circuit board card is correspondingly switched, the PGA and the anti-aliasing filter receive a step signal, and the output of the circuit can reach an expected input value after the set-up time.
Preferably, the setup time is a time required for a signal to reach a predetermined accuracy through the analog switch switching circuit, the PGA, and the anti-aliasing filter, and it is necessary to pay attention to ensure a setup time that can guarantee a high speed:
1) a low impedance signal source;
2) the cable is high in quality and short as possible;
3) note scan channel order: the voltage difference of adjacent channels is kept to be minimum, and a grounding channel is inserted between signal channels, so that the switching from a large range to a small range is avoided;
4) the channels not used are recommended to be grounded;
5) and selecting a proper sampling rate.
Compared with the prior art, the invention has the beneficial effects that:
the multifunctional data acquisition card with analog input, analog output, TTL digital input and output and programmable digital IO has strong functions, can meet the industrial measurement requirements of different users, has good compatibility, is suitable for various system configurations, and has multiple acquisition modes, and a single acquisition mode: the analog quantity acquisition channel acquires data in a single time by using a software trigger mode; continuous acquisition mode: the analog quantity acquisition channel is based on the working mode that the internal clock continuously acquires data, the acquisition is always carried out as long as the acquisition clock is always provided, and the acquisition is stopped when the acquisition clock is stopped; and (3) triggering a post-acquisition mode: and the analog quantity acquisition channel performs continuous acquisition after detecting a trigger event set based on the trigger source, and stops data acquisition manually.
Drawings
FIG. 1 is a schematic diagram of the system of the present invention;
FIG. 2 is a schematic diagram of an analog single-ended input connection according to the present invention;
FIG. 3 is a schematic diagram of the analog differential input connection of the present invention;
FIG. 4 is a schematic diagram of the analog output connection of the present invention;
FIG. 5 is a schematic diagram of TTL digital input/output connection according to the present invention;
FIG. 6 is a schematic diagram of an acquisition mode after triggering according to the present invention;
FIG. 7 is a schematic diagram of AD multiplexing according to the present invention;
fig. 8 is a schematic diagram of the AD acquisition setup time of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 8, the present invention provides a technical solution: a high-speed analog-to-digital converter module comprises an FPGA chip, wherein a bus buffer circuit is electrically connected to the FPGA chip, a digital quantity input/output module is electrically connected to the bus buffer circuit, a panel connector is electrically connected to the digital quantity input/output module, a DA conversion circuit is electrically connected to the bus buffer circuit, the DA conversion circuit is electrically connected to the panel connector, an AD converter is electrically connected to the bus buffer circuit, a gain-controllable operational amplifier is electrically connected to the AD converter, an analog switch switching circuit is electrically connected to the gain-controllable operational amplifier, an analog quantity input protection is electrically connected to the analog switch switching circuit, the analog quantity input protection is electrically connected to the panel connector through analog quantity input, and a group of AD/DA calibration circuits is electrically connected to the analog quantity input protection, the AD converter is electrically connected with another group of AD/DA calibration circuits, the other group of AD/DA calibration circuits is electrically connected with the DA conversion circuit, and the panel connector is electrically connected with the bus buffer circuit through the PFI.
In this embodiment, preferably, the FPGA chip is electrically connected to an EEPROM memory module and an SDRAM memory module, and the SDRAM memory module is electrically connected to the FPGA chip through an address bus, a data bus, and a control bus.
In this embodiment, preferably, the FPGA chip is electrically connected to a PCI9054 bus control chip, the PCI9054 bus control chip is electrically connected to another group of EEPROM memory modules, and the PCI9054 bus control chip is in intercommunication connection with the FPGA chip through an address bus, a data bus, and a control signal.
In this embodiment, preferably, the PCI9054 bus control chip is electrically connected to a PXI connector through an address bus, a data bus and a control signal, and the PXI connector is electrically connected to an external device.
In this embodiment, preferably, the analog input has 32 single-ended/16 differential configurable analog input channels, supports hybrid input, multiplexes one set of AD converters for analog input, and is gated under software control;
when the single-end input is carried out, the ground end of a signal to be tested is connected to the public ground of the circuit board card by a lead, and the other end of the signal to be tested is connected to the corresponding input port of the circuit board card;
when 16 paths of differential input are carried out, two ends of a signal to be measured are respectively connected to two differential input channels by using conducting wires, and the voltage difference of the two input ends is measured.
In this embodiment, preferably, the digital input/output module is 32 TTL digital input/output channels, and the TTL digital input/output channels are standard TTL levels, and are grouped into 8 channels, and the direction is selectable.
In this embodiment, preferably, the triggering modes of the analog input channel include the following three types:
A. software triggering
A user operates a corresponding register to trigger AD conversion, and the triggering is used for single acquisition;
B. external analog triggering
A circuit board card pin APFI0 is an analog-digital conversion external analog quantity trigger signal, a user sets an internal threshold voltage firstly, the threshold voltage setting is multiplexed with a digital-analog conversion pin, then an analog trigger signal of-10V- +10V is input through a pin APFI0, the analog trigger signal is compared with the threshold voltage set in the circuit board card, the circuit board card supports two trigger modes of being greater than or less than the set threshold voltage, only the edge of the analog quantity exceeding or being lower than the set threshold level is sensitive during triggering, and the trigger is used for triggering an acquisition mode;
C. external TTL trigger
The PFIn of the circuit board card is an analog-to-digital conversion external TTL digital quantity trigger signal, the circuit board card supports three trigger modes of a rising edge, a falling edge, a rising edge or a falling edge, the circuit board card is sensitive to the first edge of the TTL digital quantity only during triggering, and the triggering is used for triggering a post-acquisition mode.
In this embodiment, preferably, the analog input is selected by two kinds of adopted clocks, and the two kinds of adopted clocks are as follows:
a. internal clock
The circuit board card is internally provided with a 40MHz reference clock, different clock frequencies can be obtained through frequency division, each rising edge of the clock can trigger an AD conversion device to carry out AD conversion,
a maximum of 1 MHz;
a minimum of 1 Hz;
b. external clock
TTL square wave clock signals can be introduced through a circuit board card pin PFIn, each rising edge of the clock can trigger an AD conversion device to carry out AD conversion once,
input voltage: vih (min) 2.0V, VIL (MAX) 0.8V;
input frequency: less than or equal to 1 MHz;
and the analog input provides three data acquisition modes, which are as follows:
c. single acquisition mode
The analog quantity acquisition channel acquires data in a single time by using a software trigger mode;
d. continuous acquisition mode
The analog quantity acquisition channel is based on the working mode that an internal clock or an external clock continuously acquires data, the acquisition is always carried out as long as the acquisition clock is always provided, and the acquisition is stopped when the acquisition clock is stopped;
e. post-trigger acquisition mode
And the analog quantity acquisition channel performs continuous acquisition after detecting a trigger event set based on the trigger source, and stops data acquisition manually.
In this embodiment, preferably, the PGA and the anti-aliasing filter are electrically connected to a rear end of the analog switch switching circuit;
the analog switch switching circuit is switched from one input channel to another channel, the PGA gain in the circuit board card is correspondingly switched, the PGA and the anti-aliasing filter receive a step signal, and the output of the circuit can reach an expected input value after the set-up time.
In this embodiment, preferably, the setup time is a time required for a signal to reach a predetermined accuracy through the analog switch switching circuit, the PGA, and the anti-aliasing filter, and in order to ensure a high-speed setup time, attention is required:
1) a low impedance signal source;
2) the cable is high in quality and short as possible;
3) note scan channel order: the voltage difference of adjacent channels is kept to be minimum, and a grounding channel is inserted between signal channels, so that the switching from a large range to a small range is avoided;
4) the channels not used are recommended to be grounded;
5) and selecting a proper sampling rate.
The working principle and the using process of the invention are as follows: when the device is used, the electrical connection is realized through the panel connector, the transmission of data information is further realized, then analog quantity input protection can receive analog data information, the analog data information is transmitted to the analog switch switching tube circuit after being calibrated and compensated through the AD/DA calibration circuit, the switching of channels is realized, 32 single-ended/16-differential configurable analog quantity input channels are realized, mixed input is supported, the output data information is transmitted to the gain-controllable operational amplifier, the gain amplification processing of the data information is realized, the data information is transmitted to the bus buffer circuit, or the data information is transmitted to the AD/DA calibration circuit for processing and then transmitted to the DA conversion circuit, the analog information is converted into digital information and then transmitted to the bus buffer circuit, and the DA conversion circuit can directly receive the data information through the panel connector, the panel connector can receive and process data information through the digital quantity input/output module and then transmit the data information to the bus buffer circuit, then the bus buffer circuit transmits the data information to the FPGA chip, the FPGA chip can selectively store the data information in the EEPROM storage module and the SDRAM storage module and transmit the data information to the PCI9054 bus control chip, and the PCI9054 bus control chip stores the data information in the EEPROM storage module and transmits the data information to an external device for use and processing through the PXI connector.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. High-speed analog-to-digital converter module, including the FPGA chip, its characterized in that: the FPGA chip is electrically connected with a bus buffer circuit, the bus buffer circuit is electrically connected with a digital quantity input/output module, the digital quantity input/output module is electrically connected with a panel connector, the bus buffer circuit is electrically connected with a DA conversion circuit, the DA conversion circuit is electrically connected with the panel connector, the bus buffer circuit is electrically connected with an AD converter, the AD converter is electrically connected with a gain-controllable operational amplifier, the gain-controllable operational amplifier is electrically connected with an analog switch switching circuit, the analog switch switching circuit is electrically connected with an analog quantity input protection, the analog quantity input protection is electrically connected with the panel connector through analog quantity input, the analog quantity input protection is electrically connected with one group of AD/DA calibration circuits, and the AD converter is electrically connected with another group of AD/DA calibration circuits, the other group of AD/DA calibration circuits is electrically connected with the DA conversion circuit, and the panel connector is electrically connected with the bus buffer circuit through the PFI.
2. The high speed analog to digital converter module of claim 1, wherein: the FPGA chip is electrically connected with an EEPROM storage module and an SDRAM storage module, and the SDRAM storage module is electrically connected with the FPGA chip through an address bus, a data bus and a control bus.
3. The high speed analog to digital converter module of claim 1, wherein: the FPGA chip is electrically connected with a PCI9054 bus control chip, the PCI9054 bus control chip is electrically connected with another group of EEPROM storage modules, and the PCI9054 bus control chip is in intercommunication connection with the FPGA chip through an address bus, a data bus and a control signal.
4. The high speed analog to digital converter module of claim 3, wherein: the PCI9054 bus control chip is electrically connected with a PXI connector through an address bus, a data bus and a control signal, and the PXI connector is electrically connected with external equipment.
5. The high speed analog to digital converter module of claim 1, wherein: the analog quantity input is provided with 32 single ends/16 differential configurable analog quantity input channels, supports mixed input, multiplexes one set of AD converter, and is gated by software control;
when the single-end input is carried out, the ground end of a signal to be tested is connected to the public ground of the circuit board card by a lead, and the other end of the signal to be tested is connected to the corresponding input port of the circuit board card;
when 16 paths of differential input are carried out, two ends of a signal to be measured are respectively connected to two differential input channels by using conducting wires, and the voltage difference of the two input ends is measured.
6. The high speed analog to digital converter module of claim 1, wherein: the digital quantity input/output module is 32 paths of TTL digital quantity input/output channels, the TTL digital quantity input/output channels are standard TTL electrical levels, 8 paths are combined, and the direction is selectable.
7. The high speed analog to digital converter module of claim 1, wherein: the triggering modes of the analog quantity input channel include the following three modes:
A. software triggering
A user operates a corresponding register to trigger AD conversion, and the triggering is used for single acquisition;
B. external analog triggering
A circuit board card pin APFI0 is an analog-digital conversion external analog quantity trigger signal, a user sets an internal threshold voltage firstly, the threshold voltage setting is multiplexed with a digital-analog conversion pin, then an analog trigger signal of-10V- +10V is input through a pin APFI0, the analog trigger signal is compared with the threshold voltage set in the circuit board card, the circuit board card supports two trigger modes of being greater than or less than the set threshold voltage, only the edge of the analog quantity exceeding or being lower than the set threshold level is sensitive during triggering, and the trigger is used for triggering an acquisition mode;
C. external TTL trigger
The PFIn of the circuit board card is an analog-to-digital conversion external TTL digital quantity trigger signal, the circuit board card supports three trigger modes of a rising edge, a falling edge, a rising edge or a falling edge, the circuit board card is sensitive to the first edge of the TTL digital quantity only during triggering, and the triggering is used for triggering a post-acquisition mode.
8. The high speed analog to digital converter module of claim 1, wherein: the analog quantity input is selected by two adopted clocks, and the two adopted clocks are as follows:
a. internal clock
The circuit board card is internally provided with a 40MHz reference clock, different clock frequencies can be obtained through frequency division, each rising edge of the clock can trigger an AD conversion device to carry out AD conversion,
a maximum of 1 MHz;
a minimum of 1 Hz;
b. external clock
TTL square wave clock signals can be introduced through a circuit board card pin PFIn, each rising edge of the clock can trigger an AD conversion device to carry out AD conversion once,
input voltage: vih (min) 2.0V, VIL (MAX) 0.8V;
input frequency: less than or equal to 1 MHz;
and the analog input provides three data acquisition modes, which are as follows:
c. single acquisition mode
The analog quantity acquisition channel acquires data in a single time by using a software trigger mode;
d. continuous acquisition mode
The analog quantity acquisition channel is based on the working mode that an internal clock or an external clock continuously acquires data, the acquisition is always carried out as long as the acquisition clock is always provided, and the acquisition is stopped when the acquisition clock is stopped;
e. post-trigger acquisition mode
And the analog quantity acquisition channel performs continuous acquisition after detecting a trigger event set based on the trigger source, and stops data acquisition manually.
9. The high speed analog to digital converter module of claim 1, wherein: the rear end of the analog switch switching circuit is electrically connected with a PGA and an anti-aliasing filter;
the analog switch switching circuit is switched from one input channel to another channel, the PGA gain in the circuit board card is correspondingly switched, the PGA and the anti-aliasing filter receive a step signal, and the output of the circuit can reach an expected input value after the set-up time.
10. The high speed analog to digital converter module of claim 9, wherein: the setup time is the time required for a signal to reach a prescribed accuracy through the analog switch switching circuit, the PGA, and the anti-aliasing filter, and it is necessary to pay attention to ensure a high-speed setup time:
1) a low impedance signal source;
2) the cable is high in quality and short as possible;
3) note scan channel order: the voltage difference of adjacent channels is kept to be minimum, and a grounding channel is inserted between signal channels, so that the switching from a large range to a small range is avoided;
4) the channels not used are recommended to be grounded;
5) and selecting a proper sampling rate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110777509.7A CN113556126A (en) | 2021-07-09 | 2021-07-09 | High speed analog to digital converter module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110777509.7A CN113556126A (en) | 2021-07-09 | 2021-07-09 | High speed analog to digital converter module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113556126A true CN113556126A (en) | 2021-10-26 |
Family
ID=78102865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110777509.7A Withdrawn CN113556126A (en) | 2021-07-09 | 2021-07-09 | High speed analog to digital converter module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113556126A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114217581A (en) * | 2021-12-06 | 2022-03-22 | 华中科技大学 | Data acquisition system for production workshop |
| CN114578743A (en) * | 2022-05-06 | 2022-06-03 | 四川赛狄信息技术股份公司 | Ship-borne multi-channel signal acquisition synchronous control system based on FPGA |
-
2021
- 2021-07-09 CN CN202110777509.7A patent/CN113556126A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114217581A (en) * | 2021-12-06 | 2022-03-22 | 华中科技大学 | Data acquisition system for production workshop |
| CN114578743A (en) * | 2022-05-06 | 2022-06-03 | 四川赛狄信息技术股份公司 | Ship-borne multi-channel signal acquisition synchronous control system based on FPGA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8324885B2 (en) | Mixed signal acquisition system for a measurement instrument | |
| CN113556126A (en) | High speed analog to digital converter module | |
| CN111965447B (en) | Hardware configurable analog signal comprehensive test system | |
| CN111398781A (en) | Analog chip test circuit and system | |
| CN103840899B (en) | A kind of transmitting-receiving subassembly automatic test equipment | |
| CN205506896U (en) | Oscilloscope circuit | |
| CN114660979B (en) | Multichannel shared bandwidth arbitrary signal generating and collecting device | |
| CN207440565U (en) | Multichannel navigation array signal acquisition processing main plate based on radio frequency ADC | |
| CN216118413U (en) | Time measuring circuit | |
| CN214315264U (en) | Be used for direct sampling transceiver module of broadband radio frequency | |
| CN114414874A (en) | High-precision self-calibration synchronous triggering device and method | |
| CN207541221U (en) | Use USB and the JTAG control devices of tool voltage adjustable function | |
| CN114002584A (en) | Semiconductor chip digital test card | |
| CN207586311U (en) | A kind of multiport rf power measurement instrument | |
| CN112816784A (en) | Resistance test circuit and system | |
| CN220105530U (en) | Time measurement and voltage signal acquisition device | |
| CN219065604U (en) | Interface impedance matching detection circuit | |
| CN211697939U (en) | Channel isolation oscilloscope | |
| CN218183356U (en) | Modular radio frequency performance test equipment | |
| CN216486052U (en) | High-speed data acquisition module | |
| CN217034560U (en) | Support signal acquisition board of 4 ways communications | |
| US11946951B2 (en) | Measurement device and method | |
| CN218957064U (en) | Data acquisition system | |
| CN213342226U (en) | Work conversion testing device of radio frequency module | |
| CN220019796U (en) | Measurement circuit and test machine for parameters to be calibrated |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20211026 |