CN214315264U - Be used for direct sampling transceiver module of broadband radio frequency - Google Patents
Be used for direct sampling transceiver module of broadband radio frequency Download PDFInfo
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Abstract
The utility model relates to a receiving and transmitting module for broadband radio frequency direct sampling, which comprises a digital signal processing unit, a receiving and transmitting unit, a peripheral interface, an ADC/DAC unit, a clock unit and a power supply unit; the peripheral interface is connected with the transceiving unit and the digital signal processing unit, the transceiving unit is connected with the ADC/DAC unit, the ADC/DAC unit is connected with the digital signal processing unit, and the clock unit is connected with the ADC/DAC unit and the digital signal processing unit; and the output end of the power supply unit is connected with the digital signal processing unit and the ADC/DAC unit. The utility model discloses the high performance FPGA, ADC/DAC are adopted more to the meter system for complete machine system receives the launch bandwidth big, and the developments are high. In the whole machine system, the digital signal processing unit and the radio frequency unit adopt independent module design, so that the use flexibility and the improvement of the channel isolation index are improved.
Description
Technical Field
The utility model relates to a signal processing technology field especially relates to a be used for direct sampling transceiver module of broadband radio frequency.
Background
Digital transceiver acquisition systems have been used for many years in a variety of applications including terrestrial cellular networks, satellite communications and radar-based surveillance, earth observation and monitoring. In the past, transceiver systems used intermediate frequency architectures in these applications, and frequency mixing was used to collect and transmit broadband signals. This design requires a large number of discrete devices and multiple analog-to-digital (ADC)/digital-to-analog (DAC) converters to accomplish it. And the defects of large volume, high power consumption, large design difficulty and the like exist.
Converter technology is evolving every year, with the sampling rates of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) of major semiconductor companies being orders of magnitude faster than products ten years ago. For example, in 2005, the fastest 12-bit resolution ADC sample rate bit 250MSPS was around the world. By 2018, the sampling rate of 12-bit ADCs has reached 6.4 GSPS. As a result of these performance enhancements, the converter can directly digitize RF frequency signals and provide sufficient dynamic range for modern communications and broadband radio frequency direct sampling systems.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome prior art's shortcoming, provide a be used for the direct receiving and dispatching module that samples of broadband radio frequency, solved the not enough of current signal receiving and dispatching system existence.
The purpose of the utility model is realized through the following technical scheme: a direct sampling transceiver module for broadband radio frequency comprises a digital signal processing unit, a transceiver unit, a peripheral interface, an ADC/DAC unit, a clock unit and a power supply unit; the peripheral interface is connected with the transceiving unit and the digital signal processing unit, the transceiving unit is connected with the ADC/DAC unit, the ADC/DAC unit is connected with the digital signal processing unit, and the clock unit is connected with the ADC/DAC unit and the digital signal processing unit; and the output end of the power supply unit is connected with the digital signal processing unit and the ADC/DAC unit.
Further, the peripheral interface comprises an LRM backplane interface and a front panel connector; the LRM back board interface is connected with the transceiving unit, and the front board connector is connected with the digital signal processing unit.
Further, the transceiver unit includes 4 receiving channels and 2 transmitting channels; the output end of the LRM back plate interface is connected with the 4-path receiving channel, and the output end of the 4-path receiving channel is connected with the input end of the ADC/DAC unit; the output end of the ADC/DAC unit is connected with the input end of the 2-path emission channel, and the output end of the 2-path emission channel is connected with the input end of the LRM backplane interface.
Furthermore, the ADC/DAC unit includes two ADC chips and one DAC chip, the output ends of each two receiving channels in the 4 receiving channels are connected to the input end of one ADC chip, and the output ends of the DAC chip are connected to the input ends of the 2 transmitting channels; and the ADC chip and the DAC chip are connected with the digital signal processing unit.
Furthermore, the receiving channel comprises an amplitude limiter, a numerical control attenuator, a low noise amplifier, a through filter and a radio frequency switch which are connected in sequence; the output end of the LRM back plate interface is connected with the amplitude limiter, and the output end of the radio frequency switch is connected with the ADC chip.
Furthermore, the transmitting channel comprises a gating switch, an amplifier, a through filter and a radio frequency switch which are connected in sequence; the output end of the DAC chip is connected with the radio frequency switch, and the gating switch is connected with the input end of the LRM backplane interface.
Further, the clock unit comprises a clock generator, a clock distributor, an external reference clock source and a TCXO clock source; the output end of the TCXO clock source is connected with the digital signal processing unit, the output end of the external reference clock source is connected with the clock generator through a buffer, the output end of the clock generator is connected with the clock distributor, the digital signal processing unit and the ADC/DAC unit, and the output end of the clock distributor is connected with the digital signal processing unit.
Furthermore, the power supply unit comprises an under-voltage and over-voltage protection chip, a direct current conversion chip, a power detection chip and a voltage reduction and stabilization circuit; the LRM back plate interface outputs a +28V power supply to the under-voltage and over-voltage protection chip, the output end of the under-voltage and over-voltage protection chip is connected with the input end of the direct current conversion chip, and the output end of the direct current conversion chip is connected with the output end of the power detection chip; the output end of the power detection chip is connected with the input end of the voltage reduction and voltage stabilization circuit, and the output end of the voltage reduction and voltage stabilization circuit is respectively connected with the digital signal processing unit and the ADC/DAC unit.
The utility model has the advantages of it is following:
1. the design system mostly adopts high-performance FPGA and ADC/DAC, so that the receiving and transmitting bandwidth of the whole system is large and the dynamic is high.
2. Under the same index, compared with the traditional intermediate frequency mixing scheme, the system has greatly reduced volume.
3. Under the same index, the power consumption of the whole machine is greatly reduced.
4. In the whole machine system, the digital signal processing unit and the radio frequency unit adopt independent module design, so that the use flexibility and the improvement of the channel isolation index are improved.
5. And the ASAAC avionics system structure standard is adopted, so that the system reliability and the use scene are increased.
6. Under the ASAAC structural standard, the indexes of small volume, low power consumption, multiple channels and large bandwidth are realized.
Drawings
Fig. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of a transceiver unit;
FIG. 3 is a schematic diagram of a clock unit topology;
fig. 4 is a schematic diagram of a hardware structure of the power supply unit.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application provided below in connection with the appended drawings is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application. The invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, a transceiver module for broadband radio frequency direct sampling includes a digital signal processing unit, a transceiver unit, a peripheral interface, an ADC/DAC unit, a clock unit and a power supply unit; the peripheral interface is connected with the transceiving unit and the digital signal processing unit, the transceiving unit is connected with the ADC/DAC unit, the ADC/DAC unit is connected with the digital signal processing unit, and the clock unit is connected with the ADC/DAC unit and the digital signal processing unit; and the output end of the power supply unit is connected with the digital signal processing unit and the ADC/DAC unit.
The core of the digital signal processing unit is an FPGA chip with the model of XC7VX690T and is responsible for signal processing and peripheral interface control. The clock unit provides a TCXO clock source or an external reference clock 100M, and an internal reference source is used by default to provide a reference clock required by the work for the FPGA on the board and other parts.
Further, the peripheral interface comprises an LRM backplane interface and a front panel connector; the LRM back board interface is connected with the transceiving unit, and the front board connector is connected with the digital signal processing unit. The front panel connector comprises a J70A-2F 2-051-TH interface and an N25Q512A11G8F40G interface.
Further, as shown in fig. 2, the transceiver unit includes 4 receiving channels and 2 transmitting (excitation) channels; the output end of the LRM back plate interface is connected with the 4-path receiving channel, and the output end of the 4-path receiving channel is connected with the input end of the ADC/DAC unit; the output end of the ADC/DAC unit is connected with the input end of the 2-path emission channel, and the output end of the 2-path emission channel is connected with the input end of the LRM backplane interface.
Furthermore, the ADC/DAC unit includes two ADC chips and one DAC chip, the output ends of each two receiving channels in the 4 receiving channels are connected to the input end of one ADC chip, and the output ends of the DAC chip are connected to the input ends of the 2 transmitting channels; and the ADC chip and the DAC chip are connected with the digital signal processing unit.
The model of the ADC chip is ADC12DJ3200, and the ADC12DJ3200 supports direct input frequency sampling from direct current to 10 GHz. In a dual-channel mode, the sampling frequency supported by the ADC12DJ3200 is up to 3200MSPS respectively; in the single channel mode, the supported sampling frequency is up to 6400MSPS respectively. Programmable switching functions of channel number (dual channel mode) and nyquist bandwidth (single channel mode) can be used to develop flexible hardware that can meet the requirements of high channel number or wide transient signal bandwidth applications. The full power input bandwidth of 8.0GHz (-3dB), combined with the available frequency exceeding the-3 dB point in both dual-channel and single-channel modes, can perform direct radio frequency sampling on L, S, C and the X frequency band of the frequency agile system.
ADC12DJ3200 may implement deterministic latency and multi-device synchronization using a high speed JESD204B output interface with up to 16 serial lanes and subclass 1 compatibility. The serial output channels support rates up to 12.8Gbps and may be configured to switch bit rates and channel numbers. The device has innovative synchronization characteristics of non-noise aperture delay (TAD) adjustment, SYSREF window and the like, and simplifies the system design of phased array radar and MIMO communication. An optional Digital Down Converter (DDC) in dual channel mode can reduce the interface rate (both real and complex decimation modes) and support mixing of digitized signals (complex decimation mode only).
The model of the DAC chip is AD9172, and the AD9172 is a high-performance double 16-bit digital-to-analog converter (DAC) which supports the DAC sampling rate of 12.6 GSPS. The DAC has an 8 lane and 15 Gbps JESD204B data input port, a high performance DAC clock multiplier, and digital signal processing capability for single and multi-frequency direct-to-Radio Frequency (RF) wireless applications.
Furthermore, the receiving channel comprises an amplitude limiter, a numerical control attenuator, a low noise amplifier, a through filter and a radio frequency switch which are connected in sequence; the output end of the LRM back plate interface is connected with the amplitude limiter, and the output end of the radio frequency switch is connected with the ADC chip.
Furthermore, the transmitting channel comprises a gating switch, an amplifier, a through filter and a radio frequency switch which are connected in sequence; the output end of the DAC chip is connected with the radio frequency switch, and the gating switch is connected with the input end of the LRM backplane interface.
Wherein, Low Noise Amplifier (LNA) requires small noise coefficient and high linearity, and because receiving channels 1, 2 and 4 require direct path frequency band DC-6.4GHz, HMC8411LP2FE of ADI company is selected; the LNA of receive channel 3 selects the Qorvo corporation low noise amplifier TQP3M 9008; the amplifier is QPA6489A from qorvo.
The receiving channel and the transmitting channel need to use a radio frequency switch to select different radio frequency branches, an alternative switch of the transmitting channel selects HMC849ALP4CE of ADI company, and the two switches can meet the requirement of 80dB of turn-off ratio of a transmitting signal; the receiving channel selects PE42521 from peregrine company; the three-out-of-one and four-out-of-one switches both use one-out-of-four devices, and the radio frequency switch selects the HMC241LP3E from ADI.
The receiving channel adjustable numerical control attenuator selects HMC624 and HMC424 of ADI company, the adjustable range of a single chip is 31.5dB, and the step is 0.5 dB; the amplitude limiter selects an amplitude limiting diode MADL-011023 and 14150T from MACOM company for amplitude limiting;
further, as shown in fig. 3, the clock unit includes a clock generator (HMC 7044), a clock distributor (HMC 987), an external reference clock source, and a TCXO clock source; the output end of the TCXO clock source is connected with the digital signal processing unit, the output end of the external reference clock source is connected with the clock generator through a BUFFER (BUFFER), the output end of the clock generator is connected with the clock distributor, the digital signal processing unit and the ADC/DAC unit, and the output end of the clock distributor is connected with the digital signal processing unit.
The signal processing clock source is mainly from the external reference clock of the board, and simultaneously supports TCXO input, and a user can manually switch. The FPGA and other parts are provided with clocks required by operation through a clock distributor and a PLL. There are two options for the reference clock, user selectable. The first method comprises the following steps: inputting an onboard TCXO clock; and the second method comprises the following steps: and the external reference clock is directly connected to the front panel LRM through the SMA radio frequency head to realize the input of the external reference clock, and the external reference clock is used for inputting by default.
Further, as shown in fig. 4, the power supply unit includes an under-voltage and over-voltage protection chip (LTC 4364), a dc conversion chip (EHHD 006A0B 41-HZ), a power detection chip (INA 260 AI), and a step-down voltage regulator circuit; the LRM back plate interface outputs a +28V power supply to the under-voltage and over-voltage protection chip, the output end of the under-voltage and over-voltage protection chip is connected with the input end of the direct current conversion chip, and the output end of the direct current conversion chip is connected with the output end of the power detection chip; the output end of the power detection chip is connected with the input end of the voltage reduction and voltage stabilization circuit, and the output end of the voltage reduction and voltage stabilization circuit is respectively connected with the digital signal processing unit and the ADC/DAC unit.
Further, the voltage reduction and stabilization circuit comprises a voltage reducer LTM4644, a voltage reduction and stabilization device ADP5054 and the like, wherein the LTM4644 supplies power to the ADC chip and the FPGA chip, and the ADP5054 supplies power to the DAC chip; the ADC chip and the DAC chip are powered by LDOs to provide power sources separately, the board layout is considered, a distributed power source architecture design is adopted, the DC-DC adopts a switching power supply 1MHz, and the PSRR 40dB @1MHz of the rear LDO is adopted.
The whole board power supply is the front panel LRM interface +28V power supply input, the board card adopts the LRM interface +28V power supply input, an under-voltage overvoltage protection chip is arranged at the front end of the power supply input, when the voltage is higher than 36V and lower than 18V, the power supply is turned off, a user can monitor the power consumption and the voltage of the board card in real time through the FPGA, the power supply interface provides the power supply needed by the board for the digital signal processing board, meanwhile, a 12V power supply is provided for the radio frequency FMC buckling board, the power supply design of the FPGA is delayed according to the power supply time sequence of the FPGA, and the power supply time sequence control is carried out through the TPS3808G01 chip.
The foregoing is illustrative of the preferred embodiments of this invention, and it is to be understood that the invention is not limited to the precise form disclosed herein and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the concept as disclosed herein, either as described above or as apparent to those skilled in the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A transceiver module for wideband rf direct sampling, comprising: the device comprises a digital signal processing unit, a transceiving unit, a peripheral interface, an ADC/DAC unit, a clock unit and a power supply unit; the peripheral interface is connected with the transceiving unit and the digital signal processing unit, the transceiving unit is connected with the ADC/DAC unit, the ADC/DAC unit is connected with the digital signal processing unit, and the clock unit is connected with the ADC/DAC unit and the digital signal processing unit; and the output end of the power supply unit is connected with the digital signal processing unit and the ADC/DAC unit.
2. A transceiver module for wideband radio frequency direct sampling according to claim 1, wherein: the peripheral interface comprises an LRM backplane interface and a front panel connector; the LRM back board interface is connected with the transceiving unit, and the front board connector is connected with the digital signal processing unit.
3. A transceiver module for wideband radio frequency direct sampling according to claim 2, wherein: the receiving and transmitting unit comprises 4 paths of receiving channels and 2 paths of transmitting channels; the output end of the LRM back plate interface is connected with the 4-path receiving channel, and the output end of the 4-path receiving channel is connected with the input end of the ADC/DAC unit; the output end of the ADC/DAC unit is connected with the input end of the 2-path emission channel, and the output end of the 2-path emission channel is connected with the input end of the LRM backplane interface.
4. A transceiver module for wideband radio frequency direct sampling according to claim 3, wherein: the ADC/DAC unit comprises two ADC chips and a DAC chip, the output ends of every two receiving channels in the 4 receiving channels are connected with the input end of one ADC chip, and the output ends of the DAC chip are connected with the input ends of the 2 transmitting channels; and the ADC chip and the DAC chip are connected with the digital signal processing unit.
5. The transceiver module of claim 4, wherein: the receiving channel comprises an amplitude limiter, a numerical control attenuator, a low noise amplifier, a through filter and a radio frequency switch which are connected in sequence; the output end of the LRM back plate interface is connected with the amplitude limiter, and the output end of the radio frequency switch is connected with the ADC chip.
6. The transceiver module of claim 4, wherein: the transmitting channel comprises a gating switch, an amplifier, a through filter and a radio frequency switch which are connected in sequence; the output end of the DAC chip is connected with the radio frequency switch, and the gating switch is connected with the input end of the LRM backplane interface.
7. A transceiver module for wideband radio frequency direct sampling according to claim 1, wherein: the clock unit comprises a clock generator, a clock distributor, an external reference clock source and a TCXO clock source; the output end of the TCXO clock source is connected with the digital signal processing unit, the output end of the external reference clock source is connected with the clock generator through a buffer, the output end of the clock generator is connected with the clock distributor, the digital signal processing unit and the ADC/DAC unit, and the output end of the clock distributor is connected with the digital signal processing unit.
8. A transceiver module for broadband radio frequency direct sampling according to any one of claims 2-7, characterized by: the power supply unit comprises an under-voltage and over-voltage protection chip, a direct-current conversion chip, a power detection chip and a voltage reduction and stabilization circuit; the LRM back plate interface outputs a +28V power supply to the under-voltage and over-voltage protection chip, the output end of the under-voltage and over-voltage protection chip is connected with the input end of the direct current conversion chip, and the output end of the direct current conversion chip is connected with the output end of the power detection chip; the output end of the power detection chip is connected with the input end of the voltage reduction and voltage stabilization circuit, and the output end of the voltage reduction and voltage stabilization circuit is respectively connected with the digital signal processing unit and the ADC/DAC unit.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114070219A (en) * | 2021-11-11 | 2022-02-18 | 中国电子科技集团公司第二十九研究所 | Filter network for eliminating electromagnetic wave interference effect |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114070219A (en) * | 2021-11-11 | 2022-02-18 | 中国电子科技集团公司第二十九研究所 | Filter network for eliminating electromagnetic wave interference effect |
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