CN114002584A

CN114002584A - Semiconductor chip digital test card

Info

Publication number: CN114002584A
Application number: CN202111290650.0A
Authority: CN
Inventors: 王丽国; 冯龙; 柴国占
Original assignee: Shenzhen Ti Intelligent Technology Suzhou Co ltd
Current assignee: Shenzhen Ti Intelligent Technology Suzhou Co ltd
Priority date: 2021-11-02
Filing date: 2021-11-02
Publication date: 2022-02-01

Abstract

The invention relates to the technical field of semiconductor chips and discloses a semiconductor chip digital test card, wherein a board card comprises a main board, 2 DIO sub-boards (each DIO sub-board is provided with 64 DIO signals) and a PPMU sub-board (each PPMU sub-board is composed of 16 sources), wherein one of the main board, the DIO sub-boards and the PPMU sub-board are provided with 3 intels, and 2 FPGAs are responsible for controlling the 2 DIO sub-boards to generate DI/DO signals. The semiconductor chip digital test card adopts CY10FPGA of intel and an interface chip E818AFH to achieve 128-channel high-density and 50MHz high-speed output; the OPA277 operational amplifier is adopted to complete the PPMU with multiple gears; the development is completely independent, and import replacement can be partially completed; through 128 DIO interfaces, each path can be set with output level, comparison level and high-ancestor state; 16 PPMU modules and 4-gear current sources; a 50MHz rate; IIC and SPI functions are integrated, and an upper computer can be directly programmed and controlled; the data comparison function is integrated, and the analysis of test data can be completed in the FPGA; a low cost solution.

Description

Semiconductor chip digital test card

Technical Field

The invention relates to the technical field of semiconductor chips, in particular to a semiconductor chip digital test card.

Background

A semiconductor chip: the semiconductor device which can realize a certain function is made by etching and wiring on a semiconductor wafer, not only a silicon wafer, but also a common semiconductor material such as gallium arsenide (gallium arsenide is toxic, so that some inferior circuit boards do not decompose the gallium arsenide) and germanium.

In the field of semiconductor chip testing, high-speed digital modules are monopolized abroad all the time, although corresponding products exist in China, the performance difference is larger compared with that of the products in the foreign countries, so that the products are mainly purchased in the foreign countries at present, and the main pain points are as follows: the channel density is not enough, and 64 channels (such as STS8300 series measured and controlled by Huafeng) are mainly used domestically; the PPMU has less current gear; low rate, 33MHz (st 8300 series for peak measurement and control); the cost is high; therefore, a low-cost semiconductor chip digital test card capable of high-speed output is proposed to solve the above problems.

Disclosure of Invention

Technical problem to be solved

Aiming at the defects of the prior art, the invention provides a semiconductor chip digital test card which has the advantages of low cost, high-speed output and the like and solves the problems of insufficient channel density, low speed and high cost.

(II) technical scheme

In order to realize the purposes of low cost and high-speed output, the invention provides the following technical scheme: a semiconductor chip digital test card comprising: the board card consists of a main board, 2 DIO sub-boards (each DIO sub-board has 64 DIO signals) and a PPMU sub-board (each PPMU sub-board consists of 16 sources), wherein one of the two sub-boards has 3 intel CY10 FPGAs, and the 2 FPGAs are responsible for controlling the 2 DIO sub-boards to generate DI/DO signals to carry out digital channel test on a chip to be tested; the FPGA is responsible for controlling one PPMU daughter board, performs open-short circuit test on a chip to be tested, outputs a total 128 paths of signals, and uses 256 output optocoupler relays and the inside to perform isolation control, wherein the 128 relays are used for switching the output 128 signals onto two DIO daughter boards; the remaining 128 relays are used for switching the output 128 signals to the PPMU daughter board, and since the PPMU has 16 paths of sources in total, the 128 paths of signals share one path of PPMU source signal in average every 8 paths of signals;

the DIO digital system has 128 channels in total, and functions are similar for each channel (Chn), as shown in fig. 1, wherein DRE represents data direction, 0 represents output drive, and 1 represents input data comparison; pat (pattern data) represents transmitted data; VIH and VIL represent level settings; DCLP/DCLM stands for clamp voltage setting; VOH/VOL is a comparison level setting at the time of data input; the input and output of data of each pin and the PPMU function are switched through a high-speed optical coupler, and an I2C interface, an SPI interface function and an IO interface are multiplexed in the FPGA; the highest rate of I2C may be up to 2Mbps, and the rate of SPI may be up to 50 Mbps.

Preferably, each of the 128 DIO interfaces can be set with an output level, a comparison level and an advanced state, and the 128 DIO interfaces are realized by using an E818AFH interface chip and have a maximum working speed of 50 MHz.

Preferably, 16 way PPMU module, 4 grades of current sources, 50MHz speed, I2C, SPI interface output and DIO interface output are inside multiplexing in FPGA, and the speed of I2C and SPI can be selected by the host computer, the highest speed 2Mbps of I2C, the highest speed 50Mbps of SPI.

Preferably, the IIC and SPI functions are integrated, an upper computer can be directly programmed and controlled, and the PPMU-16-path source circuit is used for measuring parameters such as open circuit and short circuit, wherein the voltage range is +/-5V, the precision is 0.05%, the current range is +/-20 uA/200uA/2mA/20mA, and the precision is 0.2% in total for four gears.

Preferably, the integrated data comparison function can complete analysis of test data in the FPGA, the datamemory is used for storing drive or comparison data, a value 0 represents a low level, and a value 1 represents a high level; dirrmemory is used to indicate the direction of data flow, a value of 0 indicates drive, and a value of 1 indicates compare; the enmemory is used for indicating whether the data is valid, the value 0 represents invalid, and the value 1 represents valid.

(III) advantageous effects

Compared with the prior art, the invention provides a semiconductor chip digital test card, which has the following beneficial effects:

1. the semiconductor chip digital test card achieves 128-channel high-density and 50MHz high-speed output by adopting CY10FPGA of intel and an interface chip E818 AFH; the OPA277 operational amplifier is adopted to complete the PPMU with multiple gears; the development is completely independent, and import replacement can be partially completed; a low cost solution;

2. the semiconductor chip digital test card can set output level, comparison level and high-voltage state in each path through 128 paths of DIO interfaces; 16 PPMU modules and 4-gear current sources; a 50MHz rate; IIC and SPI functions are integrated, and an upper computer can be directly programmed and controlled; the data comparison function is integrated, and the analysis of test data can be completed in the FPGA; a low cost solution.

Drawings

FIG. 1 is a system diagram of the architecture of the present invention;

FIG. 2 is a block diagram of the design of the present invention;

FIG. 3 is a diagram of an input interface of the motherboard according to the present invention;

FIG. 4 is a diagram of a portion of a power filter according to the present invention;

FIG. 5 is a diagram of a level shifting portion of the present invention;

FIG. 6 is a configuration diagram of a first FPGA of the present invention;

FIG. 7 is a diagram of the interface portion of the PPMU sub-board;

FIG. 8 is a diagram of the IO switched to PPMU interface via a relay according to the present invention;

FIG. 9 is a diagram of the relay switching to the DIO daughter board of the present invention;

FIG. 10 is a diagram of an output interface of the motherboard according to the present invention;

FIG. 11 is a diagram of the interface design of the DIO daughter board of the present invention;

FIG. 12 is a DAC layout for the motherboard of the present invention;

FIG. 13 is a layout view of a DIO daughter board of the present invention;

FIG. 14 is a diagram of a PPMU design in accordance with the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The first embodiment is as follows: the board card consists of a main board, 2 DIO sub-boards (each DIO sub-board has 64 DIO signals) and a PPMU sub-board (each PPMU sub-board consists of 16 sources), wherein one of the two sub-boards has 3 intel CY10 FPGAs, and the 2 FPGAs are responsible for controlling the 2 DIO sub-boards to generate DI/DO signals to carry out digital channel test on a chip to be tested; the FPGA is responsible for controlling one PPMU daughter board, performs open-short circuit test on a chip to be tested, outputs a total 128 paths of signals, and uses 256 output optocoupler relays and the inside to perform isolation control, wherein the 128 relays are used for switching the output 128 signals onto two DIO daughter boards; the remaining 128 relays are used for switching the output 128 signals to the PPMU daughter board, and since the PPMU has 16 paths of sources in total, the 128 paths of signals share one path of PPMU source signal in average every 8 paths of signals;

Example two: as shown in fig. 2, the design block diagram of the digital system is mainly explained as follows:

(1) the 128-channel DIO interface is realized by adopting an E818AFH interface chip, and the highest working speed is 50 MHz;

(2) I2C, SPI interface output and DIO interface output are multiplexed in the FPGA, the rates of I2C and SPI can be selected by an upper computer, the highest rate of I2C is 2Mbps, and the highest rate of SPI is 50 Mbps;

(3) PPMU-16 source circuit for measuring open and short circuit parameters, wherein the voltage range is + -5V, the precision is 0.05%, the current range is + -20 uA/200uA/2mA/20mA, and the precision is 0.2%;

(4) datamemory is used to store drive or compare data, with a value of 0 indicating a low level and a value of 1 indicating a high level; dirrmemory is used to indicate the direction of data flow, a value of 0 indicates drive, and a value of 1 indicates compare; the enmemory is used for indicating whether the data is valid or not, wherein a value of 0 represents invalid, and a value of 1 represents valid;

each DIO channel corresponds to one bit of each memory, so that each DIO channel has 3 bits of data to represent the state, and five states of high driving, low driving, high comparing, low comparing and high resisting of each DIO channel can be realized;

the Result _ memory is used for storing waveform test results, 2 bits represent a DIO channel and can represent four states of PASS, target high measurement low, target low measurement high and intermediate level;

FIG. 3 shows the input interface of the motherboard, which mainly comprises a power supply part (power supplies of + -54V/+ -15V, etc.), and a control part (data bus: LAD 0-LAD 15, address bus: LA 1-LA 18, control line WR/RD, chip select signal SLOTX, etc.).

Fig. 4 shows a power supply filter portion.

Fig. 5 is a level conversion section.

Because the data, the address and the control signal which enter the main board from the outside are all 5V level, in order to enable the FPGA to receive correctly, a 74LVC4245 chip is used for converting the 5V level into 3.3V level, and therefore the FPGA chip is accessed.

Fig. 6 is a configuration of a first FPGA, which mainly includes a power-on portion of a core power supply, a FLASH configuration portion, and a burning interface, and the configuration of the remaining two FPGAs is similar to that of the first FPGA;

fig. 7 is an interface portion of the PPMU daughter board, and the function and design of a specific PPMU will be given later.

Fig. 8 shows the design of switching the output IO to the PPMU interface through the relay, and it can be seen that 8 IO ports (DIO 0-DIO 7) share one source output (S0-F/S0-S) of the PPMU, a total of 16 similar structures are provided on the main board, a total of 128 DIOs share 16 PPMU source outputs (S0-S15), and a total of 128 optocoupler relays are provided;

fig. 9 is a design for switching output IO to a DIO daughter board through a relay, and it can be seen that each output interface (DIO 0-DIO 7) corresponds to one IO interface (IO 0-IO 7), there are 16 similar structures on the main board, and 128 DIOs correspond to 128 IO ports (IO 0-IO 127) in total, and there are 128 optocoupler relays in total;

FIG. 10 shows the output interface of the motherboard, and for the description of FIGS. 8 and 9, DIO is the external output of the motherboard, and is directly connected to the external pins of the chip to be tested, IO pins are connected to the DIO daughter board, and S0-F/S0-S source output is connected to the PPMU daughter board;

FIG. 11 is an interface design for a DIO daughter board.

Fig. 12 is a motherboard DAC design, primarily used to generate the levels of a DIO daughter board, primarily with four levels,

for the IO output, two levels of driving high (VHREF _1) and driving low (VLREF _1) exist, and for the IO input, two levels of comparing high (VCAREF _1) and comparing low (VCBREF _1) exist;

the level is mainly used for a DIO daughter board, two DAC chips are arranged on the mainboard, one DAC chip is responsible for level setting of 64 IO ports, the other DAC chip is responsible for level setting of the remaining 64 DIO ports, and therefore two groups of IO ports capable of setting the level respectively exist.

FIG. 13 is a design of a DIO daughter board. In the figure, 8 IO interfaces are provided, 8 similar modules are provided on the daughter board, namely 64 IO interfaces, the daughter board has two blocks, and 128 IO interfaces are provided.

As can be seen, the IO function is mainly completed by the chip E818AHF, the driving DATA of the FPGA is input by the DATA pin and then output by the DOUT pin; the output data of the chip to be tested is output from the VINP pin through the IO pin, and the compared result data is output by the QA/QB pin. Whether the chip can work in a high-resistance state is controlled by an EN pin;

in order to protect the E818 chip, the clamping level of +/-8 VDIO is added on the input pin and the output pin, so that the E818 chip is prevented from being burnt out;

it can be seen that the DATA DATA can be output by DOUT drive, setting the VH/VL drive levels; the data input is input by VINP, and the comparison level can be set by CVA/CVB; when EN is high, DOUT can be set to Hi-Z state; the working frequency can reach 50MHz

Fig. 14 is a PPMU design.

A PPMU daughterboard has 16 source outputs, each source having the following functions:

FVMI(Force Voltage measure current)

FIMV(Force current measure voltage)

FVMV(Force Voltage measure voltage)

the PPMU structure of each pin is the same, and one PPMU is shared by every 8 channels.

The PPMU design adopts a 4-wire mode and has a feedback mode, and the FPGA can set the current and the voltage loaded on the load through a DAC chip; because the board card has a certain distance to the load, and the lead has a resistor, so that loss and voltage drop are reduced, a mode of measuring actual current and voltage at a far end is adopted, the actual current and voltage are compared with a set value of the DAC, and a difference value is loaded to the load through an operational amplifier, so that loss and voltage drop are compensated, and the set current and voltage of the DAC are consistent with the far-end voltage and current actually sampled.

Sampling the current by adopting a sampling resistor with high precision and small temperature drift; the load end voltage is processed through the ADC chip through the operational amplifier, sampling and FPGA;

the invention has the beneficial effects that: the semiconductor chip digital test card achieves 128-channel high-density and 50MHz high-speed output by adopting CY10FPGA of intel and an interface chip E818 AFH; the OPA277 operational amplifier is adopted to complete the PPMU with multiple gears; the development is completely independent, and import replacement can be partially completed; a low cost solution; through 128 DIO interfaces, each path can be set with output level, comparison level and high-ancestor state; 16 PPMU modules and 4-gear current sources; a 50MHz rate; IIC and SPI functions are integrated, and an upper computer can be directly programmed and controlled; the data comparison function is integrated, and the analysis of test data can be completed in the FPGA; a low cost solution;

it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims

1. A semiconductor chip digital test card, comprising:

the board card consists of a main board, 2 DIO sub-boards (each DIO sub-board has 64 DIO signals) and a PPMU sub-board (each PPMU sub-board consists of 16 sources), wherein one of the two sub-boards has 3 intel CY10 FPGAs, and the 2 FPGAs are responsible for controlling the 2 DIO sub-boards to generate DI/DO signals to carry out digital channel test on a chip to be tested; the FPGA is responsible for controlling one PPMU daughter board, performs open-short circuit test on a chip to be tested, outputs a total 128 paths of signals, and uses 256 output optocoupler relays and the inside to perform isolation control, wherein the 128 relays are used for switching the output 128 signals onto two DIO daughter boards; the remaining 128 relays are used for switching the output 128 signals to the PPMU daughter board, and since the PPMU has 16 paths of sources in total, the 128 paths of signals share one path of PPMU source signal in average every 8 paths of signals;

the DIO digital system has 128 channels in total, and functions are similar for each channel (Ch n), as shown in fig. 1, wherein DRE represents data direction, 0 represents output drive, and 1 represents input data comparison; pat (pattern data) represents transmitted data; VIH and VIL represent level settings; DCLP/DCLM stands for clamp voltage setting; VOH/VOL is a comparison level setting at the time of data input; the input and output of data of each pin and the PPMU function are switched through a high-speed optical coupler, and an I2C interface, an SPI interface function and an IO interface are multiplexed in the FPGA; the highest rate of I2C may be up to 2Mbps, and the rate of SPI may be up to 50 Mbps.

2. The semiconductor chip digital test card of claim 1, wherein the 128 DIO interfaces each can set an output level, a compare level, and a high-voltage generation status, and the 128 DIO interfaces are implemented by an E818AFH interface chip with a maximum operating speed of 50 MHz.

3. The semiconductor chip digital test card of claim 1, wherein the 16 PPMU module, 4-step current source, 50MHz rate, I2C, SPI interface output and DIO interface output are multiplexed inside FPGA, I2C and SPI rates are selectable by host computer, I2C highest rate is 2Mbps, SPI highest rate is 50 Mbps.

4. The semiconductor chip digital test card of claim 1, wherein the integrated IIC and SPI functions, the upper computer can be directly programmed and controlled, PPMU — 16 source circuits, for measuring parameters such as open circuit and short circuit.

5. The semiconductor chip digital test card of claim 1, wherein the voltage range is ± 5V with an accuracy of 0.05%, the current range is ± 20uA/200uA/2mA/20mA with a total of four steps with an accuracy of 0.2%.

6. The semiconductor chip digital test card of claim 1, wherein the integrated data comparison function is capable of performing analysis of test data within the FPGA.

7. The semiconductor chip digital test card of claim 1, wherein the datamemory is used to store driving or comparison data, a value of 0 indicates a low level, and a value of 1 indicates a high level; dirrmemory is used to indicate the direction of data flow, a value of 0 indicates drive, and a value of 1 indicates compare; the enmemory is used for indicating whether the data is valid, the value 0 represents invalid, and the value 1 represents valid.