CN115389912B

CN115389912B - OTP MCU chip detection device and detection method

Info

Publication number: CN115389912B
Application number: CN202211031671.5A
Authority: CN
Inventors: 徐春; 吉巍; 汪德文; 陈杰
Original assignee: Wuxi Zhongxiang Technology Co ltd
Current assignee: Wuxi Zhongxiang Technology Co ltd
Priority date: 2022-08-26
Filing date: 2022-08-26
Publication date: 2023-08-29
Anticipated expiration: 2042-08-26
Also published as: CN115389912A

Abstract

The embodiment of the application discloses a chip detection device and a method, comprising a burning machine, an FPGA main control chip, a chip detection card seat and a detection circuit; the chip detection card seat is used for placing an OTP MCU chip to be detected, is connected to the burning machine and is used for receiving a detection instruction of the burning machine; the FPGA main control chip is arranged on the burning machine and is in communication connection with the burning machine; the detection circuit comprises an interface conversion circuit and an ADC detection circuit which are respectively connected with the FPGA main control chip and the chip detection card seat; the FPGA main control chip sends a test instruction and receives test data through an SPI interface of the interface conversion circuit, judges the detection result of the OTP MCU chip, and controls the burning machine to burn the OTP MCU chip under the condition that the detection result is qualified. The device realizes detection and burning of the multipath chips by adding the main control chip, omits the transfer time for detecting the burning, and improves the detection and burning efficiency.

Description

OTP MCU chip detection device and detection method

Technical Field

The embodiment of the application relates to the field of chip detection, in particular to an OTP MCU chip detection device and method.

Background

In the chip production process flow, after the chip production is completed, the produced chip needs to be subjected to burning before delivery by a detection department. The MCU of OTP only can have one-time programming, so it is important to ensure that all modules in the MCU can work normally before programming. In addition, the MCU is internally provided with analog modules such as an ADC (analog to digital), a comparator, a DAC (digital to analog), an OP (operational amplifier), and the like, so that the normal working performance of each module of the chip is ensured, each key parameter of the chip is required to be tested, and particularly, the trimming of the bandgap and the OSC is required, and the two modules directly determine the performance of the MCU. Because MCU application fields are many, therefore the programming procedure is also many, OTP MCU can not write the test code into the chip because of the uniqueness, can't carry out the functional test.

In the related art, the burner only ensures the correctness of burning, but cannot completely ensure the correctness of the chip function. The method needs to independently test instruments and equipment one by one and repair parameters, and has low test efficiency and high test cost.

Disclosure of Invention

The embodiment of the application provides an OTP MCU chip detection device and a detection method. The technical scheme is as follows:

in one aspect, an OTP MCU chip detection device is provided, the device comprises a burning machine, an FPGA main control chip, a chip detection card seat and a detection circuit;

the chip detection card seat is used for placing the OTP MCU chip to be detected, and is connected to the burning machine and used for receiving a test instruction of the burning machine;

the FPGA main control chip is arranged on the burning machine and is in communication connection with the burning machine;

the detection circuit comprises an interface conversion circuit and an ADC detection circuit, and the interface conversion circuit and the ADC detection circuit are connected with the FPGA main control chip and the chip detection card seat respectively;

and the FPGA main control chip sends a test instruction and receives test data through an SPI interface of the interface conversion circuit, judges a detection result of the OTP MCU chip, and controls the burning machine to burn the OTP MCU chip under the condition that the detection result is qualified.

On the other hand, an OTP MCU chip detection and programming method is provided, the method is used for an FPGA main control chip in the OTP MCU chip detection and programming device described in the above aspect, and the method includes:

powering up the device, wherein the FPGA chip loads a test algorithm, a test instruction, a firmware program and a chip code to be burned in a data memory; the data memory is connected with the FPGA main control chip, and the FPGA main control chip is arranged on the burning machine;

sending assembly checking instructions to at least two paths of chip detection card seats through an interface conversion circuit, wherein the assembly checking instructions are used for detecting assembly conditions of the OTP MCU chip;

the chip detection card seat is polled and sent with a pin check instruction through the interface conversion circuit in sequence, and the feedback level is detected; the pin checking instruction comprises a pin mark number of the OTP MCU chip;

under the normal condition of a pin, a band gap reference trimming instruction is sent to the chip detection card seat, and the band gap reference trimming instruction is continuously sent based on the difference value between the feedback voltage and the reference voltage of the ADC detection circuit; the ADC detection circuit is connected between the FPGA main control chip and the chip detection card seat, and the band gap reference trimming instruction is used for controlling the OTP MCU chip to output the reference voltage;

under the condition of outputting the reference voltage, sending an OSC crystal oscillator trimming instruction to the chip detection card seat, modulating according to a feedback signal and continuing to send the OSC crystal oscillator trimming instruction; the OSC crystal oscillator trimming instruction is used for controlling PWM wave output target frequency;

and under the condition of outputting the PWM wave with the target frequency, adjusting the power supply voltage of the chip detection card seat, and burning the chip code to be burned into the OTP MCU chip.

The technical scheme provided by the embodiment of the application has the beneficial effects that at least: an independent FPGA main control chip is arranged on a traditional burning machine, a test number instruction burning code in a memory is read by the main control chip, and a specified assembly checking instruction, a pin checking instruction, a test instruction and a trimming instruction are sent to a chip detection card seat through an interface conversion unit, so that various parameters of each OTP MCU chip are checked and trimmed by combining the feedback voltage of an ADC detection circuit; after trimming is finished and the chip is in a field supporting condition, the burning machine is directly controlled to burn and check the chip after burning, functions of the test board and the burning machine are integrated, time for carrying out secondary transfer and equipment replacement between chip detection and burning is omitted, and the efficiency of chip detection and burning is improved.

Drawings

Fig. 1 is a schematic structural diagram of an OTP MCU chip detection and recording device according to an embodiment of the application;

FIG. 2 is a flowchart of an OTP MCU chip detecting and burning method according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating connection of a power management module according to an embodiment of the present application;

fig. 4 is a flowchart of a detection and burning process according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The burning machine is a machine for burning finished product data after the chip is designed and processed, the OTP MCU chip is an OTP Memory, and a one-time programmable read-Only Memory (One Time Programable Read-Only Memory) is a Memory type of the MCU. The MCU can be classified into MASK ROM, OTP ROM, FLASH ROM, etc. according to the memory type thereof. The program/data of the MASK ROM is solidified when leaving the factory, and is suitable for application occasions with fixed program/data; the MCU program/data of the FALSH ROM can be repeatedly erased and written, has strong flexibility, and is suitable for occasions where the program/data need to be changed; the MCU of the OTP ROM has one-time programmable capability, and is suitable for application occasions requiring certain flexibility and incapability of changing after writing data. In the scheme, the OTP MCU can only have one burning opportunity, so that all modules in the MCU can be ensured to work normally before burning. The MCU is internally provided with analog modules such as an ADC (analog to digital), a comparator, a DAC (digital to analog), an OP (operational amplifier), and the like, so that the normal working performance of each module of the chip is ensured, each key parameter of the chip is required to be tested, and particularly, the band gap reference and the OSC clock oscillation are required to be modified, and the two directly determine the performance of the MCU. The device can also test the function of each module and the pin bonding condition, so that each factory chip can work normally.

Fig. 1 is a schematic structural diagram of an OTP MCU chip detection and recording device according to an embodiment of the application.

Based on the existing burning machine, an altera FPGA (cycloniv ep4ce6e22c8 n) is integrated as a main control chip, a chip detection card seat and a detection circuit are connected with a data memory and an acousto-optic display unit in an external mode. The chip detection card seat is used for installing an OTP MCU chip to be detected and burnt, each path of chip detection card seat is connected to the main control chip through the ADC detection circuit and the interface conversion circuit respectively, and each path of chip detection card seat is connected with a burning interface of the burning machine respectively and used for carrying out program and code burning when the test passes.

The OTP MCU chip detected by the device is integrated with functions of an ADC/DAC/CMP, OSC, MCU microprocessor, low-voltage checking, PWM, bandgap, WDT, timer and the like, and the functions all need to be checked and tested. Especially, the bandgap and OSC require trimming of the clock before the chip leaves the factory because the accuracy of OSC does not reach 1% of the design requirements due to the problems of the chip production process. The same is true for the 1.2V voltage reference of Bandgap, which requires trimming to 1% accuracy. In addition, due to the problem of the packaging process, the problem of wire disconnection, unstable binding and the like often occur during the bonding of pins. According to the scheme, a series of detection work is completed through the FPGA main control chip, manual participation or secondary conversion equipment detection is not relied on, the test time is shortened, and the productivity and the efficiency are improved.

The main control chip is provided with a controller unit, a burning coprocessor, an ADC trimming control unit, an OSC clock oscillation trimming unit, a chip pin bonding inspection unit and the like aiming at the function to be tested, and each unit is respectively corresponding to corresponding test instructions, codes and test algorithms and stored in a data memory, and the data memory is also arranged on the burning machine table and is electrically connected with the main control chip. The test content comprises the steps of checking the assembly state of the chip, checking the OTP vacancy, checking the internal functions of the MCU, checking the pin string, trimming the band gap and trimming the OSC, and controlling the burning machine to burn data and check the burning completion again after the checking is completed, so that the burning is ensured to be correct.

In the scheme, the coprocessor of the FPGA main control chip is two independent units, so that the device can burn two OTP MCU chips at the same time. Therefore, two paths of independent chip test card seats, corresponding interface conversion circuits and ADC detection circuits are arranged. Each group of chip test card seats are respectively connected with corresponding burning interfaces on the burning machine. The ADC detection circuit is used for converting the tested voltage data into digital signals for analysis by the main control chip, and the data interface conversion unit is used for coordinating different working voltages between the FPGA and the OTP MCU chip. The acousto-optic display unit and the power management unit are controlled by the FPGA main control chip, and the power management unit outputs corresponding working voltages under different conditions so as to ensure detection and burning. And the sound-light display unit can carry out sound-light alarm when the test result of the chip is not passed.

In summary, the scheme is that an independent FPGA main control chip is arranged on a traditional burning machine, a main control chip reads a test number instruction burning code in a memory, and an interface conversion unit sends a specified assembly checking instruction, a pin checking instruction, a test instruction and a trimming instruction to a chip detection card seat, and the parameters of each OTP MCU chip are checked and trimmed by combining the feedback voltage of an ADC detection circuit; after trimming is finished and the chip is in a field supporting condition, the burning machine is directly controlled to burn and check the chip after burning, functions of the test board and the burning machine are integrated, time for carrying out secondary transfer and equipment replacement between chip detection and burning is eliminated, and the efficiency of chip detection and burning is improved.

Fig. 2 is a flowchart of an OTP MCU chip detection and programming method according to an embodiment of the present application, which is used for an FPGA main control chip in an OTP MCU chip detection and programming device. The method specifically comprises the following steps:

in step 201, the device is powered on, and the FPGA chip loads the test algorithm, the test instruction, the firmware program and the chip code to be burned in the data memory.

The FPGA chip is internally integrated with a controller, the whole process is coordinated and completed by the controller, related test algorithms, test instructions, firmware programs and chip codes to be burned are all stored in a data memory, after equipment is powered on or restarted, the FPGA automatically loads firmware into a ROM in the FPGA, and the controller is started.

Step 202, the fpga master control chip sends an assembly inspection instruction to at least two paths of chip detection card seats through the interface conversion circuit.

It should be noted that, because the device is an integrated design, the OTP MCU chip needs to provide different operating voltages during detection and burning, so the FPGA also needs to control the power management module separately. After initialization and during detection, the main control chip controls the first power supply unit of the power supply management module to provide 3.3V power supply voltage, and for the OTP MCU chip in a test state, two independent second power supply units are needed to provide 5V detection voltage for the OTP MCU chip, and when one chip or power supply is damaged and the next operation cannot be executed, the main control chip can close one voltage output according to a feedback result and timely carry out audible and visual alarm.

The interface conversion circuit is used for data transmission between different working voltages, namely, in the scheme, the voltage is converted between 5V and 3.3V through a conversion chip or an MOS tube. The FPGA sends assembly inspection instructions to the two paths of chip sockets 1 and the chip socket2 through the interface conversion circuit respectively. The circuit is connected with the socket through an SPI interface, and the SPI interface is used for description later. The FPGA sequentially sends 50 ID reading commands to the two sockets through the SPI interface. The read ID command is used for detecting whether the OTO MCU chip is completely inserted into the socket and whether the socket is damaged. If the data of 0xC2 is read back, the chip in the socket works normally, and if the data of 0xC2 is not fed back after 50 commands are finished, the chip is judged to be abnormal.

And 203, when the chip works normally, receiving an external test instruction, sending a vacancy check to the chip detection card seat through the interface conversion circuit, and receiving a feedback instruction of the OTP MCU chip.

The empty check is a special check for the OTP MCU, and since the OTP chip has a single-write feature, it has to be empty checked to determine whether other data is written or burned into it. And the main control chip receives the feedback instruction to confirm according to the SPI interface. And when the OTP MCU is full 1 data, indicating that the OTP MCU chip is not burnt, otherwise, storing the data in the chip abnormally.

And 204, when the space bit check meets the condition, sending a test code to the chip detection card seat.

The test codes are also sent to the socket chip through the SPI, the OTP MCU chip in the socket analyzes the codes, and the main control chip reads the state signals and the processing results in the chip interface through the SPI interface, so that whether the chip works normally can be judged.

Step 205, the main control chip sequentially polls the chip detection card seat through the interface conversion circuit to send pin inspection instructions and detect feedback level.

The polling times are determined according to the number of PIN PINs of the chip, the main control chip sequentially generates corresponding PIN checking instructions according to the PIN sequence numbers, the corresponding PIN checking instructions are sent to the OTP MCU chip through the SPI interface, after receiving and determining a target IO PIN, a PIN switch is turned on, and low level 0 is output. The main control chip is responsible for receiving the signal value of the feedback level, and when detecting low level 0, the main control chip sends a pin checking instruction again, controls the corresponding pin to output high level and detects. When the received level signal value is inconsistent with the signal value required by the pin checking instruction, the pin is indicated to have a problem, namely, the chip is judged to be abnormal. And after the test of one IO pin is finished, continuously selecting the next IO pin, and repeating the operation until the test of all pins is polled.

Step 206, under the normal condition of the pin, sending a band gap trimming instruction to the chip detection card seat, and continuing to send the band gap trimming instruction based on the difference value between the feedback voltage and the reference voltage of the ADC detection circuit.

And when the test on all the pins is completed and no abnormality occurs, sending a Bandgap trimming instruction to the chip detection card seat. In this scheme, the reference voltage for band gap trimming is 1.2V, but because of the difference of the production process, the chip may not meet the desired requirement, so that trimming is required. The method specifically comprises the following steps:

a, a Bandgap trimming instruction based on a reference voltage is sent to a chip detection card seat through an interface conversion circuit.

And B, receiving the feedback voltage after analog-to-digital conversion through an ADC detection circuit, and judging whether the difference value between the feedback voltage and the reference voltage is larger than an error threshold value.

The OTP MCU outputs an analog signal, the analog signal is required to be converted by an ADC detection circuit and then judged by the FPGA, and the process is required to be completed by relying on a built-in algorithm. In the scheme, the target reference voltage is set to be 1.2V, the trimming precision is 1%, and the maximum adjusting times are 100 times. And the main control chip determines an error threshold according to the precision. When the voltage fed back by the MCU is too low, a command for reducing the voltage of the bandgap is correspondingly sent.

C, when the difference value of the two is smaller than the error threshold value, indicating that the voltage precision trimming is successful; and when the difference value is larger than the error threshold value and the trimming frequency is smaller than the trimming upper limit, continuously sending a Bandgap trimming instruction according to the difference value until the voltage precision is trimmed to be within the error threshold value, otherwise, outputting the abnormal chip.

If the voltage is detected to reach 1% precision in the period and 100 times of adjustment are not reached, the data are memorized and burnt into a socket chip, so that the value is called after the chip is electrified every time, and the reference voltage precision of the chip reaches 1% design requirement. If the adjustment accuracy of the chip is greater than 1% after 100 times, judging that the chip is abnormal.

Step 207, sending an OSC crystal oscillator trimming command to the chip detection card base under the condition of outputting the reference voltage, modulating according to the feedback signal, and continuing to send the OSC crystal oscillator trimming command.

After the reference voltage adjustment is completed, the PWM wave frequency of the OSC continues to be adjusted. This procedure requires the invocation of a test algorithm for OSC, and the tuning procedure is similar to step 206. The method comprises the following steps:

a, sending an OSC crystal oscillator trimming instruction to a chip detection card seat through an interface conversion circuit;

b, receiving the PWM frequency of the feedback signal, and judging whether the difference value between the PWM frequency and the target frequency is larger than an error threshold value;

c, when the difference value of the two is smaller than the error threshold value, indicating that the OSC trimming is successful; and when the difference value is larger than the error threshold value and the trimming frequency is smaller than the trimming upper limit, continuously sending an OSC crystal oscillator trimming instruction according to the difference value until the frequency precision is trimmed to be within the error threshold value, otherwise, outputting the abnormal chip.

The accuracy and maximum number of adjustments to OSC are the same as the voltage of Bandgap. And sending an instruction for outputting the PWM signal to the MCU through the SPI interface, checking the frequency of the fed-back PWM by the FPGA, and if the precision is more than 1%, sending an OSC crystal oscillator trimming instruction to the socket continuously until the trimming precision meets the requirement, and finally writing the obtained data into the MCU correspondingly.

And step 208, under the condition of outputting the PWM wave with the target frequency, adjusting the power supply voltage of the chip detection card seat, and burning the chip code to be burned into the OTP MCU chip.

After the OSC trimming is finished, determining that each index parameter of the OTP MCU chip is normal, and performing burning work. The burning process needs to be completed by controlling a burning machine. However, in order to complete the burning and detecting operations, the main control chip and the burning machine are required to cooperate, and the working voltages of the MCU during the burning and the testing are different, so that the main control chip is also required to regulate the voltages. The main control chip needs to send a second control instruction to the power management module to control the third power supply unit to provide 8.5V burning voltage for the chip detection card seat. The burning voltage also needs at least two paths, and under the action of the coprocessor, asynchronous test can be ensured when the two paths of chips are asynchronous in time sequence, and mutual interference is avoided.

Fig. 4 is a flowchart of a detection and burning process according to the present embodiment of the application. After the equipment is powered on, firstly loading a firmware program, after the firmware is loaded successfully, loading the burning code again, and after the burning code is loaded successfully, waiting for an instruction to start detection. The instruction may be an instruction sent by the burning machine to the main control chip, or triggered by a button of the testing machine. The first step of detection is to detect whether a burning instruction exists in the RAM or not so as to ensure that the burning can be normally performed after the detection is successful, otherwise, the burning can only be performed after the detection is not performed. After determining that a burning instruction exists, detecting whether the OTP MCU chip is assembled in place; after the assembly check is executed, an OTP vacancy check is executed to judge whether the data in the chip is abnormal or not. After the OTP vacancy check, the internal functions are checked. And if the detection result is normal, continuing to carry out pin bonding inspection. After the pin detection is normal, band trimming and OSC trimming are continuously carried out, and whether the inside of the chip is abnormal or not is judged according to a corresponding trimming algorithm. Under the condition that all indexes are normal, the burning machine can be controlled to execute the burning step on the chip. The data memory stores codes to be burnt, data verification is carried out through the SPI interface after the burning is completed, whether the burning is correct or not is judged, and when the burnt data is abnormal, sound and light reminding is carried out on the corresponding loop; when the chip is burned normally, a complete detection and burning cycle is completed, the chip to be tested is replaced, and the detection process is continuously executed.

In summary, the detection and burning device and the method provided by the embodiment of the application realize the integration of burning and detection, and for the detection of the OTP MCU, an independent FPGA main control chip, a power management module and a data storage module are introduced, and at least two paths of chip detection can be processed simultaneously through a coprocessor of the FPGA. The main control chip can respectively carry out assembly inspection, pin bonding inspection, internal function inspection, vacancy inspection, bandgap trimming and OSC trimming on the two detection loops by loading various overdetection instructions and algorithms in the data storage module. After the detection is finished, the chip is not required to be transported, but the burning machine is continuously controlled to directly conduct burning and burning detection, the time for carrying out secondary transportation and equipment replacement between the chip detection and burning is omitted, and the efficiency of the chip detection and burning is improved.

The foregoing describes preferred embodiments of the present application; it is to be understood that the application is not limited to the specific embodiments described above, wherein devices and structures not described in detail are to be understood as being implemented in a manner common in the art; any person skilled in the art will make many possible variations and modifications, or adaptations to equivalent embodiments without departing from the technical solution of the present application, which do not affect the essential content of the present application; therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application still fall within the scope of the technical solution of the present application.

Claims

1. The OTP MCU chip detection and burning method is characterized in that the method is used for an FPGA main control chip in an OTP MCU chip detection and burning device, and the device comprises a burning machine table, an FPGA main control chip, a chip detection card seat, a detection circuit and a power management unit; the OTP MCU chip to be tested is placed on the chip detection card seat; the chip detection card seat is connected to the burning machine and receives a test instruction of the burning machine; the FPGA main control chip is arranged on the burning machine and is in communication connection with the burning machine;

the FPGA main control chip sends a test instruction and receives test data through an SPI interface of the interface conversion circuit, and controls the burning machine to burn the OTP MCU chip;

the power management unit is connected with the FPGA main control chip and the chip detection card seat and is used for providing corresponding working voltage;

the method comprises the following steps:

powering up the device, wherein the FPGA chip loads a test algorithm, a test instruction, a firmware program and a chip code to be burned in a data memory;

sending an assembly inspection instruction to at least two paths of chip detection card seats through an interface conversion circuit; the assembly checking instruction is used for detecting the assembly condition of the OTP MCU chip;

under the normal condition of a pin, a band gap reference trimming instruction is sent to the chip detection card seat, and the band gap reference trimming instruction is continuously sent based on the difference value between the feedback voltage and the reference voltage of the ADC detection circuit; the band gap reference trimming instruction is used for controlling the OTP MCU chip to output the reference voltage;

under the condition of outputting the reference voltage, sending an OSC crystal oscillator trimming instruction to the chip detection card seat, modulating according to the PWM wave frequency of a feedback signal, and continuing to send the OSC crystal oscillator trimming instruction; the OSC crystal oscillator trimming instruction is used for controlling PWM wave output target frequency;

2. The method of claim 1, wherein after the device is powered on, the FPGA master control chip sends a first control instruction to the power management unit, and the first power unit provides a 3.3V supply voltage to control the second power unit to provide a 5V detection voltage to each path of the chip detection card holder;

after sending the assembly inspection instruction to the chip detection card seat, the method further comprises the following steps:

when the chip works normally, an external test instruction is received, a vacancy checking instruction is sent to the chip detection card seat through the interface conversion circuit, and a feedback instruction of the OTP MCU chip is received; the vacancy checking instruction is used for performing vacancy checking on the OTP MCU chip; when the OTP MCU is full 1 data, indicating that the OTP MCU chip is not burnt, otherwise, storing the data in the chip abnormally;

when the space bit check meets the condition, a test code is sent to the chip detection card seat; the test code is used for carrying out internal analysis on the OTP MCU chip, so that the state signals and the processing results in the chip interface can be conveniently read through the interface conversion circuit.

3. The method according to claim 2, wherein the polling the chip test card socket by the interface conversion circuit to send a pin check command and detect a feedback level sequentially includes:

the interface conversion circuit is used for controlling the OTP MCU chip target IO pin and outputting low level, wherein each path of chip detection card seat contains the pin checking instruction corresponding to the pin sequence number;

receiving a level signal fed back by a target IO pin, and judging whether the chip is abnormal or not according to the level signal value;

when the level signal value is low, polling the pin sequence number and continuing to send the pin checking instruction until all IO pins of the chip are polled; when the level signal is at a high level, the corresponding IO pin is abnormal.

4. The method of claim 3, wherein sending a bandgap reference trimming instruction to the chip detection cartridge and continuing to send the bandgap reference trimming instruction based on a difference between a feedback voltage of an ADC detection circuit and a reference voltage, comprises:

sending the band gap reference trimming instruction based on the reference voltage to the chip detection card seat through the interface conversion circuit;

receiving the feedback voltage subjected to analog-to-digital conversion through the ADC detection circuit, and judging whether the difference value between the feedback voltage and the reference voltage is larger than an error threshold value or not;

when the difference value of the two is smaller than the error threshold value, indicating that the voltage precision trimming is successful; when the difference value is larger than the error threshold value and the trimming frequency is smaller than the trimming upper limit, continuously sending the band gap reference trimming instruction according to the difference value until the voltage precision is trimmed to be within the error threshold value, otherwise, outputting abnormal chips; wherein the reference voltage of the bandgap reference is 1.2V.

5. The method of claim 4, wherein the sending an OSC crystal oscillator trimming command to the chip test card holder, modulating and continuing to send the OSC crystal oscillator trimming command according to a feedback signal, comprises:

sending the OSC crystal oscillator trimming instruction to the chip detection card seat through the interface conversion circuit;

receiving the PWM frequency of the feedback signal, and judging whether the difference value between the PWM frequency and the target frequency is larger than an error threshold value;

when the difference value of the two is smaller than the error threshold value, indicating that the OSC crystal oscillator is successfully repaired and regulated; and when the difference value is larger than the error threshold value and the trimming frequency is smaller than the trimming upper limit, continuously sending the OSC crystal oscillator trimming instruction according to the difference value until the frequency precision is trimmed to be within the error threshold value, otherwise, outputting abnormal chips.

6. The method of claim 5, wherein adjusting the power supply voltage of the chip test card holder and burning the chip code to be burned into the OTP MCU chip comprises:

under the condition of outputting the PWM wave with the target frequency, determining that the OTP MCU chip is normal, sending a second control instruction to the power management unit, and controlling a third power unit in the power management unit to provide 8.5V burning voltage for the chip detection card seat;

reading codes to be recorded in the data memory, and recording each path of OTP MCU chips through a recording interface of the recording machine; and after the burning is finished, re-reading whether the burning data are matched with the codes to be burned in the data memory or not, and indicating that the chip is burned normally when the judgment result is consistent, otherwise prompting through an acousto-optic display unit.