CN115389912A

CN115389912A - OTP MCU chip detection device and detection method

Info

Publication number: CN115389912A
Application number: CN202211031671.5A
Authority: CN
Inventors: 徐春; 吉巍; 汪德文; 陈杰
Original assignee: Wuxi Zhongxiang Technology Co ltd
Current assignee: Wuxi Zhongxiang Technology Co ltd
Priority date: 2022-08-26
Filing date: 2022-08-26
Publication date: 2022-11-25
Anticipated expiration: 2042-08-26
Also published as: CN115389912B

Abstract

The embodiment of the application discloses a chip detection device and a chip detection method, wherein the chip detection device comprises a burning machine table, an FPGA main control chip, a chip detection card seat and a detection circuit; the chip detection card seat is used for placing an OTP MCU chip to be detected, is connected to the burn-in machine table and is used for receiving a detection instruction of the burn-in machine table; the FPGA main control chip is arranged on the testing machine table and is in communication connection with the burning machine table; the detection circuit comprises an interface conversion circuit and an ADC detection circuit which are respectively connected with the FPGA main control chip and the chip detection card seat; the FPGA main control chip sends a test instruction and receives test data through an SPI interface of the interface conversion circuit, the detection result of the OTP MCU chip is judged, and the burn-recording machine is controlled to burn the OTP MCU chip under the condition that the detection result is qualified. This device realizes detecting and burning to multichannel chip through adding main control chip, omits the transit time that detects the burning, improves and detects and burns record efficiency.

Description

OTP MCU chip detection device and detection method

Technical Field

The embodiment of the application relates to the field of chip detection, in particular to an OTP MCU chip detection device and a detection method.

Background

In the chip production process, after the chip production is completed, the produced chip needs to be burned before leaving the factory by a detection department. The OTP MCU can be programmed only once, so it is important to ensure that all the modules inside the MCU can work normally before programming. And the MCU is internally provided with analog modules such as an ADC, a comparator, a DAC, an OP and the like, in order to ensure the normal working performance of each module of the chip, the testing of each key parameter of the chip is required, particularly the trimming of the bandgap and the OSC is required, and the two modules directly determine the performance of the MCU. Because the MCU has a plurality of application fields, so the programming programs are also a plurality, and the OTP MCU can not program the test code into the chip and can not perform the function test due to the uniqueness.

In the related art, the burner only ensures the correctness of burning, but cannot completely ensure the correctness of the chip function. The testing efficiency is low and the testing cost is high because the testing and parameter adjustment of the instrument and equipment are required to be independently adopted.

Disclosure of Invention

The embodiment of the application provides an OTP MCU chip detection device and a detection method. The technical scheme is as follows:

on one hand, the OTP MCU chip detection device is provided and comprises a burn machine table, an FPGA main control chip, a chip detection card seat and a detection circuit;

the chip detection card seat is used for placing the OTP MCU chip to be detected and is connected to the burn machine table for receiving a detection instruction of the burn machine table;

the FPGA main control chip is arranged on the testing machine table and is in communication connection with the burning machine table;

the detection circuit comprises an interface conversion circuit and an ADC detection circuit, and the interface conversion circuit and the ADC detection circuit are connected with the FPGA main control chip and the chip detection card seat respectively;

the FPGA main control chip sends a test instruction and receives test data through an SPI interface of the interface conversion circuit, judges a detection result of the OTP MCU chip, and controls the burning machine station to burn the OTP MCU chip under the condition that the detection result is qualified.

On the other hand, a method for detecting and burning an OTP MCU chip is provided, where the method is used for an FPGA main control chip in the OTP MCU chip detecting and burning device in the above aspect, and the method includes:

the equipment is powered on, and the FPGA chip loads a test algorithm, a test instruction, a firmware program and a chip code to be burned in a data memory; the data storage is connected with the FPGA main control chip, and the FPGA main control chip is installed on the test machine table;

sending an assembly checking instruction to at least two paths of chip detection card seats through an interface conversion circuit, wherein the assembly checking instruction is used for detecting the assembly condition of the OTP MCU chip;

polling and sending a pin inspection instruction to the chip detection card seat through the interface conversion circuit in sequence, and detecting a feedback level; the pin inspection instruction comprises a pin label of the OTP MCU chip;

under the condition that a pin is normal, sending a Bandgap reference trimming instruction to the chip detection card holder, and continuously sending the trimming instruction based on the difference value of the feedback voltage of the ADC detection circuit and the reference voltage; the ADC detection circuit is connected between the FPGA main control chip and the chip detection card seat, and the trimming instruction is used for controlling the OTP MCU chip to output the reference voltage;

under the condition of outputting the reference voltage, sending an OSC crystal oscillator trimming instruction to the chip detection card holder, modulating according to a feedback signal and continuously sending the OSC trimming instruction; the OSC trimming instruction is used for controlling the PWM wave to output a target frequency;

and under the condition of outputting the PWM wave of the target frequency, adjusting the power supply voltage of the chip detection card seat, and burning the chip code to be burnt into the OTP MCU chip.

The beneficial effects that technical scheme that this application embodiment brought include at least: an independent FPGA main control chip is installed on a traditional burning machine table, a test number instruction burning code in a memory is read by the main control chip, a specified assembly check instruction, a pin check instruction, a test instruction and a trimming instruction are sent to a chip detection card seat through an interface conversion unit, and all parameters of all paths of OTP MCU chips are checked and trimmed by combining the feedback voltage of an ADC detection circuit; after the trimming is completed and under the condition that the chip is supported, the burn-in machine station is directly controlled to burn and record the chip and then check the chip, functions of the test station and the burn-in station are integrated, time for secondary transferring and equipment replacing between chip detection and burning is omitted, and chip detection and burning efficiency is improved.

Drawings

Fig. 1 is a schematic structural diagram of an OTP MCU chip detecting and burning device according to an embodiment of the present application;

FIG. 2 is a flowchart of a method for detecting and burning an OTP MCU chip according to an embodiment of the present disclosure;

FIG. 3 is a schematic connection diagram of a power management module according to an embodiment of the present application;

fig. 4 is a flowchart of a detection and burning process provided in an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The programming machine is a machine which needs to perform finished product data programming after the chip is designed and processed, the OTP MCU chip is an OTP Memory, and a One Time programmable read-Only Memory (One Time programmable read-Only Memory) is a Memory type of the MCU. The MCU may be classified into MASK ROM, OTP ROM, FLASH ROM, etc. according to its memory type. The program/data of the MASK ROM is solidified when the MASK ROM leaves a factory, and the MASK ROM is suitable for application occasions where the program/data are fixed and unchanged; the MCU program/data of the FALSH ROM can be repeatedly erased and written, the flexibility is strong, and the method is suitable for occasions where the program/data need to be changed; the MCU of the OTP ROM has one-time programmable capability and is suitable for application occasions which not only require certain flexibility but also cannot be changed after data is written. The OTP MCU in the scheme can only have one-time burning opportunity, so that all modules in the MCU can work normally before burning. The MCU is internally provided with analog modules such as an ADC, a comparator, a DAC, an OP and the like, and in order to ensure the normal working performance of each module of the chip, each key parameter of the chip needs to be tested, particularly the bandgap reference and the OSC clock oscillation need to be modified, and the two modules directly determine the performance of the MCU. The device can also test the function and pin bonding condition of each module, and ensure that each factory chip can work normally.

Fig. 1 is a schematic structural diagram of an OTP MCU chip detecting and burning device according to an embodiment of the present disclosure.

On the basis of the existing burning machine, the FPGA (CycloneIV ep4ce6e22c8 n) of an altera is integrated as a main control chip, and the chip detection card seat, the detection circuit are externally connected with a data memory and an acousto-optic display unit. The chip detection card seats are used for installing OTP MCU chips to be detected and burned, each chip detection card seat is connected to the main control chip through the ADC detection circuit and the interface conversion circuit, and each chip detection card seat is connected with the burning interface of the burning machine table and used for burning programs and codes when the test is passed.

The OTP MCU chip detected by the device is integrated with functions of ADC/DAC/CMP, OSC, MCU microprocessor, low voltage check, PWM, bandgap, WDT, timer and the like, which need to be checked and tested. Especially bandgap and OSC have accuracy of less than 1% of design requirement due to problems of chip production process, so that the clock needs to be modified before the chip leaves factory. The same is true for the 1.2V voltage reference of Bandgap, which needs to be adjusted to 1% accuracy. In addition, due to the problems of the packaging process, the problems of wire disconnection, insecure binding and the like often occur during the pin bonding. According to the scheme, a series of detection work needs to be finished through the FPGA main control chip, manual participation or secondary conversion equipment detection is not relied on, the test time is reduced, and the productivity and the efficiency are improved.

The main control chip is provided with a controller unit, a burning co-processing unit, an ADC (analog to digital converter) trimming control unit, an OSC (open source clock) oscillation trimming unit, a chip pin bonding inspection unit and the like aiming at functions to be tested, each unit is respectively and correspondingly provided with a corresponding test instruction, a corresponding code and a corresponding test algorithm to be stored in a data memory, and the data memory is also arranged on a burning machine table and is electrically connected with the main control chip. The test contents comprise the assembly state inspection, OTP vacancy inspection, MCU internal function inspection, pin banding inspection, band adjustment and OSC adjustment of the chip, and after the inspection is finished, the burn-in machine is controlled again to burn data and burn-in finished inspection, so that the burn-in is ensured to be correct.

The coprocessors of the FPGA main control chip in the scheme are two independent units, so that the device can burn two OTP MCU chips at the same time. Therefore, two independent chip test card seats, corresponding interface conversion circuits and ADC detection circuits are arranged. Each group of chip test card seats is respectively connected with a corresponding burning interface on the burning machine table. The ADC detection circuit aims to convert the tested voltage data into digital signals for the analysis of the main control chip, and the data interface conversion unit is used for coordinating different working voltages between the FPGA chip and the OTP MCU chip. The acousto-optic display unit and the power management unit are controlled by the FPGA main control chip, and the power management unit outputs corresponding working voltage under different conditions to ensure the detection and burning. And the acousto-optic display unit can give an acousto-optic alarm when the test result of the chip is tested to be failed.

In conclusion, the scheme is that an independent FPGA main control chip is installed on a traditional burning machine table, a test number instruction burning code in a memory is read by the main control chip, a specified assembly check instruction, a specified pin check instruction, a specified test instruction and a specified trimming instruction are sent to a chip detection card seat through an interface conversion unit, and the feedback voltage of an ADC detection circuit is combined to realize the check and trimming of various parameters of various OTP MCU chips; after the trimming is finished and under the condition of a chip support field, the burn-in station is directly controlled to burn and record the chip and then check the chip, functions of the test station and the burn-in station are integrated, the time for carrying out secondary transfer and equipment replacement between chip detection and burn-in is eliminated, and the chip detection and burn-in efficiency is improved.

Fig. 2 is a flowchart of the OTP MCU chip detection and burning method according to the embodiment of the present application, and is used for an FPGA main control chip in the OTP MCU chip detection and burning device. The method specifically comprises the following steps:

step 201, the device is powered on, and the FPGA chip loads the test algorithm, the test instruction, the firmware program, and the chip code to be burned in the data memory.

The FPGA chip is internally integrated with a controller, all processes are completed by the controller in a coordinated mode, relevant test algorithms, test instructions, firmware programs and chip codes to be burned are all stored in a data storage, and after the device is powered on or restarted, the FPGA automatically loads firmware into a ROM inside the FPGA and starts the controller.

And 202, sending an assembly checking instruction to the at least two chip detection card seats by the FPGA main control chip through an interface conversion circuit.

It should be noted that, because the device is an integrated design, the OTP MCU chip needs to provide different operating voltages during detection and burning, and therefore the FPGA needs to separately control the power management module. After initialization and during detection, the main control chip can control the first power supply unit of the power supply management module to provide 3.3V power supply voltage, for the OTP MCU chip in a test state, two independent second power supply units are needed to provide 5V detection voltage for the OTP MCU chip, and when one of the chips or the power supply is damaged and the next operation cannot be executed, the main control chip can close one of the voltage outputs according to a feedback result, so that acousto-optic alarm is timely performed.

The interface conversion circuit is used for data transmission between different working voltages, namely, the interface conversion circuit is used for converting between 5V voltage and 3.3V voltage through a conversion chip or an MOS tube in the scheme. The FPGA sends assembly inspection instructions to the two

chip sockets

1 and 2 respectively through the interface conversion circuit. SPI interface connection is adopted between the circuit and the socket, and the SPI interface is used for description subsequently. The FPGA sends 50 ID reading commands to the two sockets in sequence through the SPI interface. The ID reading command is used for detecting whether the OTO MCU chip is completely inserted into the socket or not and whether the socket is damaged or not. If the data of 0xC2 is read back, the chip in the socket is indicated to work normally, and if 0xC2 is not fed back after 50 commands are finished, the chip is judged to be abnormal.

And 203, when the chip works normally, receiving an external test instruction, sending vacancy check to the chip detection card holder through the interface conversion circuit, and receiving a feedback instruction of the OTP MCU chip.

The vacancy check is a special check for the OTP MCU, and the OTP chip has a write-once characteristic, so the vacancy check must be performed to determine whether other data is written therein or whether the chip is burned. And the main control chip receives the feedback instruction according to the SPI interface for confirmation. And when the OTP ROM contains all 1 data, indicating that the OTP MCU chip is not burned, otherwise, storing the internal data of the chip abnormally.

And step 204, when the empty bit check meets the condition, sending a test code to the chip detection card seat.

The testing codes are also sent to the socket chip through the SPI, the OTP MCU chip in the socket analyzes the codes, and the main control chip reads the state signals and the processing results in the chip interface through the SPI to judge whether the chip works normally or not.

In step 205, the main control chip polls the chip detection card socket in sequence through the interface conversion circuit to send a pin inspection instruction, and detects the feedback level.

The polling times are determined according to the number of the PIN PINs of the chip, the main control chip sequentially generates corresponding PIN checking instructions according to the PIN serial numbers, sends the PIN checking instructions to the OTP MCU chip through the SPI, and turns on an internal PIN switch to output a low level 0 after receiving and determining the target IO PIN. The main control chip is responsible for receiving the signal value of the feedback level, and when the low level 0 is detected, the main control chip sends the pin inspection instruction again to control the corresponding pin to output the high level and detect the high level. When the received level signal value is inconsistent with the signal value required by the pin detection instruction, the pin is indicated to have a problem, namely the chip is judged to be abnormal. And when the test of one IO pin is finished, continuously selecting the next IO pin, and repeating the operation until the test of all the pins is finished.

And step 206, under the condition that the pin is normal, sending a Bandgap trimming instruction to the chip detection card holder, and continuously sending the trimming instruction based on the difference value between the feedback voltage of the ADC detection circuit and the reference voltage.

And when the test on all the pins is finished and no abnormity occurs, sending a Bandgap trimming instruction to the chip detection card seat. The reference voltage for band trimming in the scheme is 1.2V, but due to the difference of production processes, the chip of the scheme can not meet the expected requirement, so that the chip needs to be trimmed. The method specifically comprises the following steps:

and A, sending a reference voltage-based Bandgap trimming instruction to the chip detection card seat through an interface conversion circuit.

And B, receiving the feedback voltage subjected to analog-to-digital conversion through an ADC detection circuit, and judging whether the difference value between the feedback voltage and the reference voltage is greater than an error threshold value.

The OTP MCU outputs analog signals, the analog signals need to be converted by an ADC detection circuit and then judged by the FPGA, and the process needs to be completed by depending on a built-in algorithm. In the scheme, the target reference voltage is set to be 1.2V, the trimming precision is 1 percent, and the maximum adjusting times are 100 times. And the main control chip determines an error threshold according to the precision. When the voltage fed back by the MCU is too low, an instruction for reducing the voltage of the bandgap is correspondingly sent.

C, when the difference value of the two is smaller than the error threshold value, indicating that the voltage precision is successfully modified; and when the difference value is greater than the error threshold value and the trimming times are less than the trimming upper limit, continuously sending a Bandgap trimming instruction according to the difference value until the voltage precision is trimmed to be within the error threshold value, otherwise, outputting the abnormal condition of the chip.

If the voltage reaches 1% precision and the voltage is not adjusted for 100 times, the data is memorized and is burnt into the chip of the socket, so that the value is called after the chip is powered on every time, and the precision of the reference voltage of the chip reaches 1% design requirement. And if the adjustment precision of the chip is more than 1% after 100 times, judging that the chip is abnormal.

And step 207, sending an OSC crystal oscillator trimming instruction to the chip detection card socket under the condition of outputting the reference voltage, modulating according to the feedback signal, and continuously sending the OSC trimming instruction.

After the reference voltage adjustment is completed, the PWM wave frequency of the OSC continues to be adjusted. This process requires invoking a test algorithm for the OSC, and the adjustment process is similar to step 206. The method comprises the following steps:

a, sending an OSC (open channel OSC) trimming instruction to a chip detection card seat through an interface conversion circuit;

b, receiving the PWM frequency of the feedback signal, and judging whether the difference value between the PWM frequency and the target frequency is greater than an error threshold value;

c, when the difference value of the two is smaller than the error threshold, indicating that the OSC is successfully repaired; and when the difference is greater than the error threshold and the trimming times are less than the trimming upper limit, continuously sending an OSC trimming instruction according to the difference until the frequency precision is trimmed to be within the error threshold, otherwise, outputting an abnormal chip.

The accuracy and maximum number of adjustments to the OSC is the same as the voltage of Bandgap. And sending a command for outputting a PWM signal to the MCU through the SPI, checking the frequency of the fed-back PWM by the FPGA, and if the precision is more than 1%, sending an OSC (open channel control) trimming command to the socket continuously until the trimming precision meets the requirement, and writing the finally obtained data into the MCU correspondingly.

And step 208, under the condition of outputting the PWM wave of the target frequency, adjusting the power supply voltage of the chip detection card holder, and burning the chip code to be burned into the OTP MCU chip.

After OSC trimming is completed, determining that all index parameters of the OTP MCU chip are normal, and performing burning. The burning process needs to be completed by controlling the burning machine. However, in order to complete the recording and detecting operations, the main control chip and the recording machine are required to be cooperatively performed, and the operating voltages of the MCU during recording and testing are different, so that the main control chip is required to adjust the voltages. The main control chip needs to send a second control instruction to the power management module to control the third power supply unit to provide 8.5V burning voltage for the chip detection card seat. The burning voltage also needs at least two paths, and under the action of the coprocessor, asynchronous testing can be guaranteed to be carried out when the two paths of chips are asynchronous in time sequence, and the asynchronous testing is not interfered mutually.

Fig. 4 is a flowchart of the detection and burning process provided in this embodiment of the present application. After the equipment is powered on, a firmware program is loaded, after the firmware is successfully loaded, the burning code is loaded again, and after the burning code is successfully loaded, an instruction for starting detection can be waited. The command may be a command sent by the burner station to the main control chip, or may be triggered by a button of the tester. The first step of the detection is to detect whether a burning command exists in the RAM or not so as to ensure that burning can be normally carried out after the detection is successful, otherwise, burning can be carried out only by detection. After the burning instruction is determined, detecting whether the OTP MCU chip is assembled in place or not; and after the assembly check is executed, the OTP vacancy check is executed again, and whether the internal data of the chip is abnormal or not is judged. After the OTP vacancy is checked, the internal function is checked. And under the condition that the detection result is normal, continuing to perform pin bonding inspection. And after the pin is detected to be normal, continuing to carry out Bandgap trimming and OSC trimming, and judging whether the interior of the chip is abnormal or not according to a corresponding trimming algorithm. And under the condition that all indexes are determined to be normal, controlling the burning machine to perform a burning step on the chip. The data storage stores a substitute burning code, data verification is carried out through the SPI after burning is finished, whether burning is correct or not is judged, and when the burning data is abnormal, sound and light reminding is carried out on a corresponding loop; when the chip is burned normally, a complete detection and burning cycle is completed, the chip to be detected is replaced, and the detection process is continuously executed.

In summary, the device and the method for detecting and burning provided by the embodiment of the application realize the integration of burning and detecting, and introduce an independent FPGA main control chip, a power management module and a data storage module aiming at the detection of the OTP type MCU, and can simultaneously process at least two paths of chip detection through a coprocessor of the FPGA. The main control chip can respectively carry out assembly inspection, pin bonding inspection, internal function inspection, vacancy inspection, bandgap adjustment and OSC adjustment on the two detection loops by loading various over-detection instructions and algorithms in the data storage module. After the detection is finished, the chip does not need to be transferred, but the burning machine table is continuously controlled to directly burn and record the chip, so that the time for carrying out secondary transfer and equipment replacement between the chip detection and burning is saved, and the chip detection and burning efficiency is improved.

The above description is that of the preferred embodiment of the present invention; it is to be understood that the invention is not limited to the particular embodiments described above, in which devices and structures not described in detail are understood to be implemented in a manner that is conventional in the art; any person skilled in the art can make many possible variations and modifications, or modify equivalent embodiments, without departing from the technical solution of the invention, without affecting the essence of the invention; therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims

1. An OTP MCU chip detection and burning device is characterized by comprising a burning machine table, an FPGA main control chip, a chip detection card seat and a detection circuit;

the chip detection card seat is used for placing the OTP MCU chip to be detected, is connected to the burn-in machine table and is used for receiving a detection instruction of the burn-in machine table;

the FPGA main control chip sends a test instruction and receives test data through an SPI interface of the interface conversion circuit, judges a detection result of the OTP MCU chip, and controls the burn-in machine to burn the OTP MCU chip under the condition that the detection result is qualified.

2. The apparatus according to claim 1, wherein a controller unit, a burning coordination processing unit, an ADC trimming control unit, an OSC clock oscillation trimming unit, and a chip pin bonding inspection unit are integrated in the FPGA main control chip, and each unit corresponds to a corresponding test instruction and a corresponding test algorithm and is stored in a data storage; the data memory also comprises a firmware program and a chip code to be burned.

3. The device of claim 2, wherein a coprocessor comprising at least two sets of independent units is built in the FPGA main control chip, the test machine comprises at least two burning interfaces, and each burning interface is connected with the chip detection card holder; and the two independent units of the co-processor respectively process the two detection circuits and the corresponding detection data.

4. The device according to claim 3, wherein the FPGA main control chip is connected with a power management unit and an acousto-optic display unit, the power management unit is further connected to the chip detection card socket and provides corresponding working voltage, and the acousto-optic display unit is used for carrying out acousto-optic prompt according to the test result of each OTP MCU chip;

the power management unit comprises a first power unit, at least two paths of same second power units and a third power unit, the first power unit is used for supplying power to the FPGA main control unit, the second power unit is used for providing detection voltage for the chip detection card holder in a detection state, and the third power unit is used for providing burning voltage for the chip detection card holder in a burning state.

5. An OTP MCU chip detecting and burning method, wherein the method is used for the FPGA main control chip in the OTP MCU chip detecting and burning device of any one of claims 1 to 4, the method comprises:

the device is powered on, and the FPGA chip loads a test algorithm, a test instruction, a firmware program and a chip code to be burned in the data memory; the data storage is connected with the FPGA main control chip, and the FPGA main control chip is installed on the test machine table;

sending an assembly inspection instruction to the at least two paths of chip detection card seats through an interface conversion circuit; the assembly checking instruction is used for detecting the assembly condition of the OTP MCU chip;

6. The method according to claim 5, wherein after the device is powered on, the FPGA main control chip sends a first control instruction to the power management unit, the first power supply unit provides 3.3V power supply voltage, and controls the second power supply unit to provide 5V detection voltage to each chip detection card socket;

after sending an assembly inspection instruction to the chip detection card seat, the method further comprises:

when the chip works normally, receiving an external test instruction, sending a vacancy checking instruction to the chip detection card seat through an interface conversion circuit, and receiving a feedback instruction of the OTP MCU chip; the vacancy checking instruction is used for carrying out vacancy checking on the OTP MCU chip; when the OTP ROM contains all 1 data, indicating that the OTP MCU chip is not burned, otherwise, storing the data in the chip abnormally;

when the empty bit check meets the condition, sending a test code to the chip detection card seat; the test code is used for internal analysis of the OTP MCU chip, so that a state signal and a processing result in a chip interface can be read conveniently through the interface conversion circuit.

7. The method of claim 6, wherein the sequentially polling the chip detection socket through the interface conversion circuit to send a pin inspection command and detect a feedback level comprises:

the chip detection card holder comprises a pin inspection instruction corresponding to the pin serial number of each chip detection card holder through the interface conversion circuit, controls a target IO pin of the OTP MCU chip and outputs low level;

receiving a level signal fed back by a target IO pin, and judging whether the chip is abnormal or not according to a level signal value;

when the level signal value is low level, polling the pin serial number and continuously sending the pin inspection command until all IO pins of the chip are polled; when the level signal is at a high level, the corresponding IO pin is abnormal.

8. The method of claim 7, wherein sending the Bandgap trimming command to the chip detection card socket and continuing to send the Bandgap trimming command based on a difference between a feedback voltage of an ADC detection circuit and a reference voltage comprises:

sending the Bandgap trimming instruction based on the reference voltage to the chip detection card seat through the interface conversion circuit;

receiving the feedback voltage subjected to analog-to-digital conversion through the ADC detection circuit, and judging whether the difference value between the feedback voltage and the reference voltage is greater than an error threshold value or not;

when the difference value of the two is smaller than the error threshold value, indicating that the voltage precision is successfully modified; when the difference value is larger than the error threshold value and the trimming frequency is smaller than the trimming upper limit, the Bandgap trimming instruction is continuously sent according to the difference value until the voltage precision is trimmed to be within the error threshold value, otherwise, the output chip is abnormal; wherein the Bandgap reference voltage is 1.2V.

9. The method of claim 8, wherein sending the OSC trimming command to the chip test socket, and modulating and continuing to send the OSC trimming command according to the feedback signal comprises:

sending the OSC trimming instruction to the chip detection card seat through the interface conversion circuit;

receiving the PWM frequency of a feedback signal, and judging whether the difference value between the PWM frequency and the target frequency is greater than an error threshold value;

when the difference value of the two is smaller than the error threshold value, indicating that the OSC is successfully repaired; and when the difference is greater than the error threshold and the trimming frequency is less than the trimming upper limit, continuing to send the OSC trimming instruction according to the difference until the frequency precision is trimmed to be within the error threshold, otherwise, outputting an abnormal chip.

10. The method of claim 9, wherein the adjusting the power supply voltage of the chip detection card socket and burning the chip code to be burned into the OTP MCU chip comprises:

under the condition of outputting the PWM wave of the target frequency, determining that the OTP MCU chip is normal, sending a second control instruction to the power management unit, and controlling a third power unit to provide 8.5V burning voltage for the chip detection card seat;

reading the generation burning codes in the data memory, and burning each path of OTP MCU chip through a burning interface of the test machine; after the burning is finished, re-reading the burning data and matching the burning data with the substitute burning codes in the data storage to judge whether the burning data is consistent with the substitute burning codes, indicating the chip to burn normally when the judgment result is consistent, and otherwise, prompting through an acousto-optic display unit.