CN111273154A

CN111273154A - Pin multiplexing test trimming system, method, computer device and storage medium

Info

Publication number: CN111273154A
Application number: CN202010070392.4A
Authority: CN
Inventors: 江旭明; 汪恒毅; 朱海刚
Original assignee: Zhejiang Dahua Technology Co Ltd
Current assignee: Zhejiang Dahua Technology Co Ltd
Priority date: 2020-01-21
Filing date: 2020-01-21
Publication date: 2020-06-12

Abstract

The application relates to a test trimming system, a method, computer equipment and a storage medium for pin multiplexing, wherein when a pulse signal is applied to a multiplexing pin, a chip enters a test trimming mode, and a mode selection module inputs the pulse signal and outputs a clock signal to a channel selection module; the channel selection module outputs a channel selection signal to the test module and the trimming module according to the clock signal, and the channel selection signal is used for determining the test channel and the trimming channel; under the condition that the multiplexing pin is suspended, the test module acquires and outputs a parameter item to be tested to the multiplexing pin according to the test channel; according to the test result, under the condition that the trimming position corresponding to the trimming channel needs to be trimmed, inputting a trimming indication signal through a multiplexing pin to burn the trimming position; the method realizes the control of mode selection, test and trimming channel selection, test parameter item output and fuse trimming programming by one multiplexing pin, reduces the cost of the chip and improves the convenience and accuracy of test trimming after the chip is packaged.

Description

Pin multiplexing test trimming system, method, computer device and storage medium

Technical Field

The present application relates to the field of chip technologies, and in particular, to a system and a method for testing and trimming pin multiplexing, a computer device, and a storage medium.

Background

High-precision output chips usually require precise adjustment of critical parameters after the wafers are produced. The trimming is to select and solidify one of a plurality of options built in the chip design according to the tested initial value of the parameter, so that the parameter to be tested meets the standard requirement. The trimming is usually performed in the wafer testing process before packaging, but the testing and the trimming need to use an expensive testing machine, take a long time to perform the testing and the parameter trimming, and have higher cost; secondly, when the repaired wafer is packaged, since the thinning, scribing, bonding, packaging and other processes of the wafer all have certain influence on the physical characteristics of the chip, various repaired parameters may drift. Therefore, in order to ensure that the key parameters of the chip can meet the high-precision requirement, it is very important to select the test and the trimming of the chip after packaging.

In order to facilitate the testing and trimming of chip parameters, a testing and trimming mode is usually set inside the chip, important line nodes and parameters are tested by leading out pins of the chip through the testing mode, and trimming and parameter curing are performed on the basis of the testing. By adopting the test trimming technology after the chip is packaged, the problem of pin multiplexing is inevitably involved in order to not increase extra pins, and the normal application of the chip cannot be influenced on the premise of the test trimming mode, so the problem of selection of the normal working mode and the test trimming mode of the chip can be involved; if a plurality of parameter items need to be tested and trimmed in the test trimming mode, the selection of a test and trimming channel, the output of the parameter item to be tested, the programming control of fuse trimming and the solidification of logic are necessarily required to be realized.

However, in the related art, the pin multiplexing can achieve a limited working mode and the test trimming requires multiple synchronous tests or control signals, which results in high production cost and low accuracy of the test trimming.

Aiming at the problems of poor convenience and low accuracy of test trimming after chip packaging in the related technology, no effective solution is provided at present.

Disclosure of Invention

In view of the foregoing, there is a need to provide a pin multiplexing test trimming system, method, computer device and storage medium.

According to an aspect of the present invention, a pin multiplexing test trimming system is provided, the pin multiplexing test trimming system is integrated on a chip, the system includes a multiplexing pin, a mode selection module, a channel selection module, a test module and a trimming module, in case that a pulse signal is input to the multiplexing pin, the mode selection module inputs the pulse signal, and the mode selection module outputs a clock signal to the channel selection module; the channel selection module outputs a channel selection signal according to the clock signal, the channel selection module outputs the channel selection signal to the test module and the trimming module, the test module determines a test channel according to the channel selection signal, and the trimming module determines a trimming channel according to the channel selection signal; under the condition that the multiplexing pin is suspended, the test module acquires a parameter item to be tested according to the test channel and outputs a test result of the parameter item to be tested to the multiplexing pin; and according to the test result, under the condition that the trimming position corresponding to the trimming channel needs to be trimmed, a trimming indication signal is input into the multiplexing pin.

In one embodiment, the mode selection module further outputs an operation mode selection signal to the chip according to an input signal of the multiplexing pin: under the condition that the multiplexing pin inputs a grounding signal, triggering the Flyback working state of the chip; under the condition that the multiplexing pin is suspended, triggering the working state of the chip Buck Buck; and triggering the test trimming state of the chip under the state that the multiplexing pin inputs the pulse signal.

In one embodiment, the mode selection module is further configured to output a first test trimming enable signal to the channel selection module according to the input signal of the multiplexing pin, and output a second test trimming enable signal to the trimming module; under the condition that the multiplexing pin inputs a pulse signal, the first test trimming enabling signal indicates the channel selection module to output a channel selection signal according to the clock signal, and the second test trimming enabling signal indicates the trimming module to enter a trimming mode; and under the condition that the multiplexing pin is suspended, the first test trimming enabling signal indicates that the channel selection module is in a non-channel selection mode, and the second test trimming enabling signal indicates that the trimming module is in a non-trimming mode.

In one embodiment, the trimming module inputs a chip enable signal, and when both the chip enable signal and the second test trimming enable signal indicate that the trimming module is in a trimming mode, the trimming module trims the trimming bit according to the test result; and the trimming module outputs the trimmed logic signal.

In one embodiment, the test module further inputs the parameter item to be tested of the chip and a test channel preset by the parameter item to be tested, and outputs a test result of the parameter item to be tested corresponding to the test channel according to the test channel.

According to another aspect of the present invention, there is also provided a method for testing and trimming pin multiplexing, the method including: under the condition that a multiplexing pin inputs a pulse signal, a mode selection module receives the pulse signal from the multiplexing pin, outputs a clock signal and sends the clock signal to a channel selection module; the channel selection module gates a test channel and a trimming channel according to the pulse signal; under the condition that the multiplexing pin is suspended, the test module acquires the test result of the test channel and feeds the test result back to the multiplexing pin; and according to the test result, under the condition that the trimming position corresponding to the trimming channel needs to be trimmed, inputting a trimming indication signal from the multiplexing pin, and triggering a trimming module to burn and write the trimming position fuse.

In one embodiment, the method further comprises: the mode selection module outputs a first test trimming enabling signal to the channel selection module according to the input signal of the multiplexing pin, and outputs a second test trimming enabling signal to the trimming module; under the condition that the multiplexing pin inputs a pulse signal, the first test trimming enabling signal indicates the channel selection module to output a channel selection signal according to the clock signal, and the second test trimming enabling signal indicates the trimming module to enter a trimming mode; and under the condition that the multiplexing pin is suspended, the first test trimming enabling signal indicates that the channel selection module is in a non-channel selection mode, and the second test trimming enabling signal indicates that the trimming module is in a non-trimming mode.

In one embodiment, the method further comprises: according to the input signal of the multiplexing pin, the mode selection module triggers different working modes of a chip, and under the condition that the multiplexing pin inputs a grounding signal, the Flyback working state of the chip is triggered; under the condition that the multiplexing pin is suspended, triggering the working state of the chip Buck Buck; and triggering the test trimming state of the chip under the state that the multiplexing pin inputs a pulse signal, wherein the test trimming system is integrated in the chip.

In one embodiment, the method further comprises: after test trimming is finished, a pulse signal is input through the multiplexing pin, the channel selection module gates the highest position, the trimming module inputs a high level signal, the highest position fuse is burned to enable the fuse burning array to be solidified, and the trimming module outputs the solidified logic signal.

In one embodiment, the obtaining, by the test module, the test result of the test channel and feeding the test result back to the multiplexing pin when the multiplexing pin is floating includes: the testing module receives a parameter item to be tested of a chip and a testing channel preset by the parameter item; and receiving the test channel, obtaining a test result of the parameter item corresponding to the test channel according to the test channel, and feeding the test result back to the multiplexing pin, wherein the test trimming system is integrated in the chip.

According to another aspect of the present invention, there is also provided a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the above-mentioned pin multiplexing test trimming method when executing the computer program.

According to another aspect of the present invention, there is also provided a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the above-mentioned pin multiplexing test trimming method.

When the pin multiplexing test trimming system, the method, the computer equipment and the storage medium are used, when a pulse signal is externally added to the multiplexing pin, the chip enters a test trimming mode, the mode selection module inputs the pulse signal, and the mode selection module outputs a clock signal to the channel selection module; the channel selection module outputs a channel selection signal to the test module and the trimming module according to the clock signal, the test module determines a test channel according to the channel selection signal, and the trimming module determines a trimming channel according to the channel selection signal; under the condition that the multiplexing pin is suspended, the test module acquires and outputs a parameter item to be tested to the multiplexing pin according to the test channel; according to the test result, under the condition that the trimming position corresponding to the trimming channel needs to be trimmed, inputting a trimming indication signal through a multiplexing pin to burn the trimming position; the method realizes the mode selection, the test and trimming channel selection, the output of the test parameter items and the control of fuse trimming programming by only using one multiplexing pin, reduces the cost of the chip and improves the convenience and the accuracy of test trimming after the chip is packaged.

Drawings

FIG. 1 is a schematic diagram of a test trimming system for pin multiplexing according to one embodiment of the present invention;

FIG. 2 is a first block diagram illustrating the structure of the mode selection module 120 according to an embodiment of the present invention;

FIG. 3 is a block diagram illustrating a second embodiment of the mode selection module 120;

FIG. 4 is a first schematic diagram of the trimming module 150 according to an embodiment of the invention;

FIG. 5 is a second schematic diagram of the trimming module 150 according to an embodiment of the invention;

FIG. 6 is a schematic diagram of a fuse trimming circuit 154 according to one embodiment of the invention;

FIG. 7 is a schematic diagram of a test module 140 in accordance with one embodiment of the present invention;

FIG. 8 is a schematic circuit diagram of a test module 140 according to an embodiment of the present invention;

FIG. 9 is a first flowchart illustrating a test trimming process for pin multiplexing according to an embodiment of the present invention;

FIG. 10 is a flow chart of a second test trimming for pin multiplexing according to an embodiment of the present invention;

FIG. 11 is a third flowchart of a test trim procedure for pin multiplexing according to an embodiment of the present invention;

FIG. 12 is a flow chart of a test trim for pin multiplexing in accordance with one embodiment of the present invention;

FIG. 13 is a diagram of a system for testing and trimming pin multiplexing in accordance with an embodiment of the present invention;

FIG. 14 is a block diagram of a channel selection module according to an embodiment of the present invention;

FIG. 15 is a digital circuit schematic of a channel selection module according to one embodiment of the present invention;

FIG. 16 is a schematic diagram of the output signals of the channel selection module in accordance with one embodiment of the present invention;

FIG. 17 is a flow chart of a test trim for pin multiplexing in accordance with an embodiment of the present invention;

FIG. 18 is a waveform diagram of a test trimming system for pin multiplexing according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The pin multiplexing test trimming system can be applied to a chip with high-precision output, and can realize multi-mode control of a normal working mode and a test trimming mode only by one multiplexing pin; in the test and repair mode, the multiplexing pin is a pulse signal input end for channel selection, a test output end for a parameter item to be tested and an input end for a fuse programming control signal, so the technical scheme can meet the setting of the test and repair mode of the chip with fewer ports, does not need to add a special port, and reduces the packaging size and the production cost of the chip.

In one embodiment, fig. 1 is a schematic diagram of a pin multiplexing test trimming system according to an embodiment of the present invention, as shown in fig. 1, the pin multiplexing test trimming system is integrated on a chip, the system includes a multiplexing pin 110, a mode selection module 120, a channel selection module 130, a test module 140, and a trimming module 150,

under the condition that the multiplexing pin 110 inputs a pulse signal, the mode selection module 120 instructs the chip to enter a test trimming mode, and outputs a clock signal CLK to enter the channel selection module 130; the channel selection module 130 outputs a channel selection signal C < N-1:0> according to the number of the clock signal detection input pulses, and the channel selection signal C enters the parameter item test module 140 and the trimming module 150 respectively to select a test channel and a trimming channel of a corresponding parameter item; under the condition that the multiplexing pin is suspended, the test module 140 obtains the parameter item to be tested according to the selected test channel, and outputs the test result of the parameter item to be tested to the multiplexing pin 110; judging and determining whether the fuse of the trimming bit corresponding to the trimming channel needs to be programmed based on the initial test result of the parameter item fed back by the multiplexing pin 110, if the fuse needs to be programmed, inputting a trimming indication signal, for example, a long-time high level, by the multiplexing pin 110, triggering the trimming module 150 to program the trimming bit fuse corresponding to gating, and directly testing the parameter value of the parameter item after trimming by suspending the multiplexing pin 110 again; if programming is not needed, the multiplexing pin 110 continues to input a pulse and enters the next test trimming channel.

Whether the trimming is needed or not, all preset parameter items can be output through the multiplexing pin 110, and parameters related to a test channel and a trimming channel which are gated by a pulse signal and input into the multiplexing pin 110 are independent of each other, for example, a parameter item X is tested when the gating channel 1 is preset, a parameter item Y is tested when the gating channel 2 is gated, and the parameter item X which is tested before the trimming and determines that the corresponding fuse bit needs to be programmed is arranged.

The pin multiplexing test and repair system and the setting method thereof are provided to improve the condition that a plurality of pins are required to be multiplexed or a complex pin protection module, a detection module and the like are required in the prior art, realize the control of mode selection, test and repair channel selection, test parameter item output and fuse repair programming by using only one multiplexing pin, reduce the cost of a chip and improve the convenience and the accuracy of test and repair after the chip is packaged. In addition, the multiplexing pin of the pin multiplexing test and repair system inputs pulse signals, and when one pulse signal is input, one test channel and one repair channel are sequentially selected, and simultaneously, the test of related parameters and the judgment of whether fuse programming is needed or not based on the test data of parameter items are realized, if the fuse programming is not needed, the multiplexing pin 110 continues to inject the pulse signals and enters the next selection channel; if the fuse is needed to be burned, the multiplexing pin 110 injects a long-time high level, and the fuse is burned, so that the system can complete the test, trimming and the solidification and locking of trimming results of all the parameter items only by one pulse sequence, the problem that a plurality of paths of synchronous control signals are needed in the prior art is solved, the problem that the test and trimming of all the parameter items can be completed by a plurality of groups of clock sequences in the traditional test and trimming system is solved, the periphery of the test system is simplified, and the test and trimming efficiency is improved.

In one embodiment, the mode selection module 120 further outputs an operation mode selection signal to the chip according to an input signal of the multiplexing pin: under the condition that a multiplexing pin inputs a grounding signal, triggering the Flyback working state of the chip; under the condition that the multiplexing pin is suspended, triggering the working state of the chip Buck Buck; and under the state that the multiplexing pin inputs the pulse signal, triggering the test trimming state of the chip. Preferably, fig. 2 is a schematic structural diagram of the mode selection module 120 according to an embodiment of the present invention, as shown in fig. 2, the mode selection module 120 further inputs an enable signal EN1 for establishing a chip bias voltage and current, inputs a bias voltage VBP and a bias current signal IBP; the operation mode selection signal FYB0_ BUCK1 is also output. The operation mode selection signal FYB0_ BUCK1 is the signal for triggering different operation states of the chip, for example, when the multiplexing pin 110 is grounded, the mode selection module output FYB0_ BUCK1 is 0 for controlling the chip to be in a Flyback operation state; when the multiplexing pin 110 is suspended, the mode selection module outputs FYB0_ BUCK1 ═ 1 for controlling the chip to be in a BUCK working state; when the multiplexing pin 110 inputs a pulse signal, the mode selection module outputs FYB0_ BUCK1 in a pulse state for controlling the chip to be in the test trimming mode, and outputs a clock signal CLK to the channel selection module for testing the selection of the trimming channel. The multiplexing pin needs to integrate various functions under the multi-mode, and needs to realize the selection of a normal working mode and a test trimming mode; when testing the trimming mode, the selection of the testing and trimming channels needs to be realized; outputting and testing the parameter items to be tested in the test mode; the multi-mode control of the normal working mode and the test trimming mode can be realized by one multiplexing pin without an additional multiplexing pin protection module through the scheme, so that the simplicity and convenience of test trimming after chip packaging are improved.

In an embodiment, fig. 3 is a schematic structural diagram of the selection module 120 according to an embodiment of the present invention, as shown in fig. 3, the mode selection module 120 is further configured to output a first test trimming enable signal TT _ EN0 to the channel selection module 130 according to an input signal of the multiplexing pin, and output a second test trimming enable signal TT _ EN1 to the trimming module 150; under the condition that the multiplexing pin 110 inputs a pulse signal, the first test trimming enable signal TT _ EN0 indicates the channel selection module 130 to output a channel selection signal according to the clock signal, and the second test trimming enable signal TT _ EN1 indicates the trimming module 150 to enter the trimming mode; under the condition that the multiplexing pin 110 is floating, the first test trimming enable signal TT _ EN0 indicates that the channel selection module 130 is in the non-channel selection state, and the second test trimming enable signal TT _ EN1 indicates that the trimming module 150 is in the non-trimming mode. For example, when the multiplexing pin 110 is grounded, the mode selection module 120 outputs the first test trimming enable signal TT _ EN0 being equal to 1, the second test trimming mode enable signal TT _ EN1 being equal to 0, and the chip is in a normal operating state; when the multiplexing pin 110 is empty, the mode selection module 120 outputs a first test trimming enable signal TT _ EN0 being equal to 1, a second test trimming enable signal TT _ EN1 being equal to 0, and the chip is in a normal operating state; when the multiplexing pin 110 inputs a pulse signal, the mode selection module 120 outputs a clock signal CLK to the channel selection module 130 for selecting the test trimming channel, and outputs a first test trimming enable signal TT _ EN0 being equal to 0, a second test trimming enable signal TT _ EN1 being equal to 1, and the chip is in the test trimming mode. In this embodiment, the mode selection module 120 triggers different enable signals according to different signals input by the multiplexing pipe 112, so that the channel selection module 130 and the trimming module 150 can execute corresponding working modes according to the enable signals in different modes, thereby more efficiently implementing scheduling and matching of the modules, and improving simplicity and efficiency of testing and trimming.

In an embodiment, fig. 4 is a first schematic diagram of the trimming module 150 according to an embodiment of the invention, as shown in fig. 4, the trimming module 150 further inputs a chip enable signal EN2, and the trimming module 150 trims the trimming bit according to the test result when the chip enable signal EN2 and the second test trimming enable signal TT _ EN1 are both 1 indicating that the trimming module 150 is in the trimming mode; in addition, the trimming module 150 outputs the trimmed logic signal after trimming. Preferably, after trimming is completed, a pulse signal is input through the multiplexing pin 110, the channel selection module 130 gates the highest bit, a long-time high level is input through the maternal and infant pin 112 to blow out the highest bit fuse, all fuse blowing arrays are solidified, after that, the test trimming system can enter the test trimming mode again, but fuse blowing cannot be performed any more, and the test trimming module 150 finally outputs a set of solidified logic levels T < N-1:0 >.

Preferably, fig. 5 is a second schematic diagram of the trimming module 150 according to an embodiment of the invention, and as shown in fig. 5, the trimming module 150 includes a fuse programming control logic 152, a fuse trimming circuit 154, and a trimming logic curing circuit 156. For the fuse programming control logic 152, the fuse programming control logic 152 will enter the trimming mode only when the enable signal EN2 for the normal operation of the chip is equal to 1 and the mode selection module generates the enable signal TT _ EN1 for the test trimming mode is equal to 1; determining which one or more fuses need to be programmed according to the test result of the test module 140 on the initial value of the parameter item and the corresponding trimming and adjusting truth table; FIG. 6 is a schematic diagram of the fuse trimming line 154 according to an embodiment of the invention, and as shown in FIG. 6, the fuse trimming line 154 is a 1-bit fuse programming line, where i is an integer from 0 to N-1, and N is the number of channels. The fuse trimming line 154 inputs a bias current signal IBP; inputting a channel selection signal C of the test trimming mode generated by the channel selection module 130 to 1; a fuse programming control signal TRIM _ EN1 of a long-time high level input to the multiplexing pin MODE is 1; when in a normal test trimming mode, LOCK0 is 1, so that all fuse programming is not influenced; the fuse-programming pull-down tube for the strobe bit is pulled down only if all three logic signals are 1. The current 1:1 of the bias current branch and the fuse branch is mirrored, and when the resistance of an unblown fuse is smaller than R0 set by the bias current branch, the trimming output logic initial value T is 1; when the resistance after the fuse is burned is larger than R0, the trimming output logic T is 0, that is, if the fuse is burned, the trimming output logic level of the channel changes from high level to low level. For the trimming logic solidification circuit 156, only after the highest fuse is gated and burned, LOCK0 is 0, the pull-down pipes of all N-bit burned fuses cannot be pulled down again, the logic level of fuse burning is solidified, the trimming result is locked, and at this time, the trimming module 150 outputs a set of logic level signals T < N-1:0> solidified after fuse burning.

In one embodiment, the test module 140 further inputs a parameter item to be tested of the chip and a test channel preset by the parameter item to be tested, and outputs a test result of the parameter item to be tested corresponding to the test channel according to the test channel. FIG. 7 is a schematic diagram of the testing module 140 according to an embodiment of the invention, as shown in FIG. 7, the testing module 140 inputs N parameter items D < N-1:0> to be tested, and inputs a channel selection signal C < N-1:0> of the testing trimming mode output by the channel selection module; according to the channel selection signal, the to-be-tested parameter item is output to the multiplexing pin 110 through the transmission gate, and the floating multiplexing pin 110 outputs the to-be-tested parameter item. Fig. 8 is a schematic circuit diagram of the test module 140 according to an embodiment of the present invention, where the circuit of the test module of each bit is as shown in fig. 8, where i is an integer from 0 to N-1, when the strobe signal C -1 indicates that the test channel bit is strobed, and the multiplexing pin 110 outputs the parameter item to be tested D at this time in a floating state. Through the test module 140 in this embodiment, not only can the parameter items be tested through the intrinsic pins, but also the parameter items that cannot be directly tested through the intrinsic pins originally can be output through the test mode set in the chip in advance through the multiplexing pins, so that the efficiency and convenience of the test repair system are further improved.

According to another aspect of the present invention, there is further provided a method for testing and trimming pin multiplexing, where fig. 9 is a first flow chart of testing and trimming pin multiplexing according to an embodiment of the present invention, as shown in fig. 9, the method includes:

s910: in the case that the multiplexing pin 110 inputs a pulse signal, the mode selection module 120 receives the pulse signal from the multiplexing pin, outputs a clock signal, and transmits the clock signal to the channel selection module 130;

s920: the channel selection module 130 gates a test channel and a trimming channel according to the pulse signal;

s930: under the condition that the multiplexing pin 110 is suspended, the test module 140 obtains the test result of the test channel and feeds the test result back to the multiplexing pin 110;

s940: according to the test result, when the trimming bit corresponding to the trimming channel needs to be trimmed, the trimming indication signal is input from the multiplexing pin 110, and the trimming module 150 is triggered to write the trimming bit fuse.

In this embodiment, in the case that the multiplexing pin 110 inputs a pulse signal, the mode selection module 120 outputs a clock signal CLK to the channel selection module 130; the channel selection module 130 outputs a channel selection signal C < N-1:0> according to the clock signal, and the channel selection signal C enters the parameter item test module 140 and the trimming module 150 respectively to select a test channel and a trimming channel of a corresponding parameter item; under the condition that the multiplexing pin is suspended, the test module 140 obtains the parameter item to be tested according to the selected test channel, and outputs the test result of the parameter item to be tested to the multiplexing pin 110; judging and determining whether the fuse of the trimming bit corresponding to the trimming channel needs to be programmed based on the initial test result of the parameter item fed back by the multiplexing pin 110, if the fuse needs to be programmed, inputting a trimming indication signal, for example, a long-time high level, by the multiplexing pin 110, triggering the trimming module 150 to program the trimming bit fuse corresponding to gating, and directly testing the parameter value of the parameter item after trimming by suspending the multiplexing pin 110 again; if programming is not needed, the multiplexing pin 110 continues to input a pulse and enters the next test trimming channel. All the parameter items which need or do not need to be modified can be output through the multiplexing pin 110 or directly measured, the testing channel and the modification channel which are gated by the pulse signal and are injected into the multiplexing pin 110 are independent, namely the parameter X can be tested when the channel is selected, but the modified parameter X can be the parameter X of the same channel, or another parameter Y of which the initial value has been tested by the previous channel, for example, if any A, B, C three parameter items need to be tested, and B, C two parameter items need to be modified, the parameter A does not need to be modified, the parameter B has two bit modification, the parameter C only has one bit modification, and the testing modification of the parameter B and the testing modification of the parameter C are independent from each other. In order to fully utilize the channel resources for testing and trimming, the parameter items requiring a plurality of trimming bits are tested first, and then the following arrangement can be adopted: selecting a channel 1, testing the parameter B, and roughly adjusting the parameter B; selecting a channel 2, testing the parameter A, and finely adjusting the parameter B; and selecting a channel 3, testing the parameter C, and trimming the parameter C.

The test and repair method for the pin multiplexing provides a test and repair system and a setting method for the multi-mode pin multiplexing, so that the problems that in the prior art, a plurality of pins are required to be multiplexed, or a complex pin protection module, a detection module and the like are required are solved, the mode selection, the test and repair channel selection, the output of test parameter items and the control of fuse repair programming are realized by using only one multiplexing pin, the cost of a chip is reduced, and the convenience and the accuracy of the test and repair after the chip is packaged are improved.

In one embodiment, the gating of the test channel and the trimming channel by the channel selection module 130 according to the pulse signal includes: the channel selection module 130 outputs a channel selection signal C < N-1:0> according to the number of the clock signal detection input pulses, and respectively enters the parameter item test module 140 and the trimming module 150 for selecting the test channel and the trimming channel of the corresponding parameter item, the multiplexing pin of the pin multiplexing test trimming system inputs a pulse signal, and one bit of the test channel and one bit of the trimming channel are sequentially selected when one pulse signal is input. The traditional channel selection module separately sets the test channel and the trimming channel, when the trigger signal triggers the counter to count, the channel selection module gates all the test channels one by one, and after all the test channels are sequentially gated, the trimming channels are gated one by one, so the traditional channel selection module usually needs to input a plurality of clock sequences to complete the test and trimming of all the parameter items, and when the test trimming items are increased, useless clock signals cause waste of time cost. In the scheme, a channel selection module 130 detects the number of pulses input by a multiplexing pin 110 through a clock signal CLK output by an input mode selection module, gates different test channels and trimming channels according to the number of the input pulses, outputs a group of channel selection signals C < N-1:0>, and respectively enters a parameter item test module and a trimming module to select the test channels and the trimming channels of corresponding parameter items. Only one test trimming trigger control signal is needed, and the multi-path synchronous test or control signal means that a test trimming machine table with higher precision is needed, so that once time delay or deviation exists between the synchronous signal or the control signal, trimming failure can be caused. According to the scheme, one testing and trimming channel is gated by multiplexing pins when one pulse signal is input, and a group of clock signals are not required to be input during channel selection. Therefore, in this embodiment, only one pulse sequence is needed to complete the testing and trimming of all the parameter items, so as to improve the problem of the prior art that multiple paths of synchronous control signals are needed, solve the problem that the traditional testing and trimming system needs multiple groups of clock sequences to complete the testing and trimming of all the parameter items, simplify the periphery of the testing system, and improve the efficiency and accuracy of the testing and trimming.

In an embodiment, fig. 10 is a flow chart of a second test trimming process of pin multiplexing according to an embodiment of the present invention, and as shown in fig. 10, the method for testing trimming of pin multiplexing further includes:

s1010: the mode selection module outputs a first test trimming enable signal to the channel selection module 130 according to the input signal of the multiplexing pin, and outputs a second test trimming enable signal to the trimming module 150:

s1010-a: under the condition that the multiplexing pin 110 inputs the pulse signal, the first test trimming enable signal indicates the channel selection module 130 to output a channel selection signal according to the clock signal, and the second test trimming enable signal indicates the trimming module 150 to enter the trimming mode;

s1010-b: under the condition that the multiplexing pin 110 is floating, the first test trimming enable signal indicates that the channel selection module 130 is in the non-channel selection mode, and the second test trimming enable signal indicates that the trimming module 150 is in the non-trimming mode.

Optionally, in a case where the multiplexing pin 110 is grounded, the first test trimming enable signal indicates that the channel selection module 130 is in the non-channel selection mode, and the second test trimming enable signal indicates that the trimming module 150 is in the non-trimming mode, where the chip is in a normal operating state. By the method in this embodiment, the mode selection module 120 outputs different enable signals to the channel selection module 130 and the trimming module 150 by multiplexing different signals input by the pin 110, thereby further improving the efficiency of testing trimming.

In an embodiment, fig. 11 is a third flow chart of the test trimming for the pin multiplexing according to an embodiment of the present invention, and as shown in fig. 11, the method for the test trimming for the pin multiplexing further includes:

s1110: according to the input signal of the multiplexing pin, the mode selection module triggers different working modes of the chip,

s1110-b: under the condition that the multiplexing pin is suspended, triggering the working state of the chip Buck Buck;

s1110-c: and triggering the test trimming state of the chip under the state that the multiplexing pin inputs the pulse signal, wherein the test trimming system is integrated on the chip.

In addition, under the condition that a grounding signal is input into the multiplexing pin, the Flyback operating state of the chip is triggered; through the scheme, an extra multiplexing pin protection module is not needed, multi-mode control of a normal working mode and a test trimming mode can be realized through one multiplexing pin, and simplicity and convenience of test trimming after chip packaging are improved.

In an embodiment, fig. 12 is a fourth flowchart of the test trimming for pin multiplexing according to an embodiment of the present invention, and as shown in fig. 12, the method for testing trimming for pin multiplexing further includes:

s1210: after the test trimming is completed, a pulse signal is input through the multiplexing pin 110, the channel selection module 130 gates the highest bit, a high level signal is input through the multiplexing pin 110, the highest bit fuse is programmed to solidify the fuse programming array, and the trimming module 150 outputs a solidified logic signal.

By the method in the embodiment, the selection of a normal working mode and a test trimming mode is realized; the selection of a test channel and a trimming channel is realized during the test of the trimming mode; the output and the test of the parameter items to be tested are realized in the test mode; besides the function of programming the fuse in the trimming mode, the method also realizes the solidification and locking of the trimming result, and further improves the simplicity and efficiency of the test trimming method for the pin multiplexing.

In one embodiment, in the case that the multiplexing pin 110 is floating, the test module 140 obtaining the test result of the test channel and feeding the test result back to the multiplexing pin 110 includes: the test module 140 receives a parameter item to be tested of the chip and a test channel preset by the parameter item; the test channel output by the channel selection module 130 is received, the test result of the parameter item corresponding to the test channel is obtained according to the test channel, and the test result is fed back to the multiplexing pin 110, wherein the test trimming system is integrated on the chip. By the method in the embodiment, the parameter items which cannot be directly tested through the intrinsic pins originally can be tested not only through the intrinsic pins but also through the test mode which is preset in the chip, and the parameter items are output through the multiplexing pins through the test mode, so that the efficiency and convenience of the test trimming system are further improved.

In an embodiment, fig. 13 is a schematic diagram of a test trimming system for pin multiplexing according to an embodiment of the present invention, and as shown in fig. 13, the multi-MODE test and trimming system for pin multiplexing includes a power port VCC, a ground port GND, and a pin MODE for multiplexing, where signals of a bias voltage VBP and a bias current IBP are generated inside a chip; the EN1 enable signal is high level, then the internal bias voltage current of the chip is established; the EN2 enable signal is high level, then the chip is in normal working state; both EN1 and EN2 enable signals are generated internally in the chip. The multi-mode pin multiplexing test trimming system includes a multiplexing pin 110, a mode selection module 120, a channel selection module 130, a test module 140 for parameter items, and a trimming module 150 for fuse programming.

The mode selection module 120 inputs a trigger signal of the multiplexing pin 110, inputs an enable signal EN1 established by chip bias voltage and current, and inputs a bias voltage VBP and a bias current signal IBP; outputting a working mode selection signal FYB0_ BUCK1, and outputting enable signals TT _ EN0 and TT _ EN1 of a test trimming mode; and outputting the clock signal CLK in the test trimming mode.

The MODE selection module 120 detects that an input signal of the multiplexing pin MODE triggers different operating MODEs. When the multiplexing pin 110 is grounded, the mode selection module outputs FYB0_ BUCK1 ═ 0 for controlling the chip to be in a Flyback operating state, and the test trimming mode enable signal TT _ EN0 ═ 1/TT _ EN1 ═ 0, the chip is in a normal operating state; when the multiplexing pin 110 is suspended, the mode selection module outputs FYB0_ BUCK1 ═ 1 for controlling the chip to be in a BUCK working state, and the test trimming mode enable signal TT _ EN0 ═ 1/TT _ EN1 ═ 0, so that the chip is in a normal working state; when the multiplexing pin 110 inputs a pulse signal, the mode selection module outputs FYB0_ BUCK1 in a pulse state for controlling the chip to be in the test trimming mode, and outputs a clock signal CLK to the channel selection module for selecting the test trimming channel, and outputs an enable signal TT _ EN0 of the test trimming mode as 0/TT _ EN1 as 1, and the chip is in the test trimming mode.

The traditional channel selection module separately sets the test channel and the trimming channel, when the trigger signal triggers the counter to count, the channel selection module gates all the test channels one by one, and after all the test channels are gated in sequence, the trimming channel is gated one by one. Therefore, the conventional channel selection module usually needs to input a plurality of clock sequences to complete the testing and trimming of all the parameter items. When the test trimming items are increased, useless clock signals cause waste of time cost.

The channel selection module 130 inputs the test trimming enable signal TT _ EN0 output by the mode selection module; the number of pulses input by the multiplexing pin 110 is detected by a clock signal CLK output by the input mode selection module, different test channels and trimming channels are gated according to the number of the input pulses, a group of channel selection signals C < N-1:0> are output and respectively enter the parameter item test module and the trimming module for selecting the test channels and the trimming channels of corresponding parameter items.

Fig. 14 is a schematic structural diagram of a channel selection module according to an embodiment of the present invention, fig. 15 is a schematic digital circuit diagram of a channel selection module according to an embodiment of the present invention, and as shown in fig. 14 and fig. 15, an 8-bit test trimming channel selection module is taken as an example: the channel selection module comprises a reset circuit, a counting circuit and a decoding circuit. The signal TT _ EN0 output by the mode selection module is used as an enabling signal of the channel selection module, and the clock signal CLK output by the mode selection module is used as a clock signal of the channel selection module; when the enable signal TT _ EN0 is in high level, the reset circuit sets the counting circuit and the decoding circuit in initial state, so that each output signal of the channel selection module is set in low level; when the signal TT _ EN0 is at low level, the system enters a test trimming mode, the channel selection module works normally, and the reset line does not affect the state of each output signal of the channel selection module.

When the channel selection module works normally, the rising edge of the clock signal CLK triggers the counting circuit to start counting, the counting circuit outputs a binary numerical value signal, a one-bit high-order channel selection signal ZH and a four-bit low-order channel selection signal Z <3:0> are generated, and finally an 8-bit channel selection signal C <7:0> is generated. Therefore, each time a pulse signal is detected at the multiplexing pin 110, a rising edge of the clock signal CLK is generated, and the gated test channel and the gated trimming channel are shifted by one bit. A channel selection signal determines both a test channel and a trim channel. Thus, it is ensured that the multiplexing pin 110 can complete the test of N parameter items and the trimming of N-bit fuses only by N pulse signals, and fig. 16 is a schematic diagram of an output signal of the channel selection module according to an embodiment of the present invention.

The strobe signal output by the channel selection module 130 is only used as a selection signal for the test channel and the trimming channel, and whether to perform the test or trimming of the channel is determined by the state of the multiplexing pin 110. If the multiplexing pin 110 is suspended at this time, the test result of the parameter item is directly output; judging whether to burn the fuse based on the test result of the parameter item, if so, adding a long-time high level outside the multiplexing pin 110, and burning the trimming bit under the channel; if programming is not required, the multiplexing pin 110 adds a pulse signal to the next test channel and the trimming channel.

After the testing and trimming of all the N parameter items are completed, the multiplexing pin 110 inputs a pulse signal to gate the highest fuse, and if the fuse is programmed, all the fuse programming arrays are solidified. Although the system can enter the test trim mode again, fuse programming cannot be performed again. The trimming module 150 finally outputs a set of solidified logic levels T < N:0>, the initial state of the trimming bit output logic is high level, and the logic after fuse programming is low level.

The test module 140 inputs N parameter items D < N-1:0> to be tested and inputs a channel selection signal C < N-1:0> output by the channel selection module 130; according to the channel selection signal, the to-be-tested parameter items are output to the multiplexing pin 110 through the transmission gate in sequence, and at the moment, the suspended multiplexing pin 110 outputs the to-be-tested parameter items.

The trimming module 150 determines whether the trimming bit or subsequent trimming bits need to be programmed based on the initial value test result for the channel selection module output channel selection signal C < N-1:0> and the multiplexing pin 110 for the parameter item? If programming is not needed, the multiplexing pin 110 continues to input a pulse and enters the next testing and trimming channel; if programming is needed, the multiplexing pin 110 inputs a long-time high level, and the triggered trimming module writes the trimming fuse corresponding to gating. When the fuse at the highest position is selected to be blown, all fuse blowing arrays are solidified, the system can enter the test trimming mode again, but the fuse blowing can not be carried out any more, and the test trimming system finally outputs a group of solidified logic levels T < N-1:0 >.

The test trimming system based on the pin multiplexing provides a main principle of the design of the test trimming system: the resources of each testing channel and each trimming channel are fully utilized, and parameter items which possibly influence other parameters are arranged to be tested and trimmed firstly; testing the parameter items needing to be trimmed as much as possible, and testing the parameter items needing to be trimmed by multiple channels as much as possible; testing and trimming after important parameters are arranged as much as possible; the testing and the trimming under the same channel selection are carried out in sequence, the parameter items are tested firstly, then the trimming is carried out, the testing and the trimming work are carried out independently without mutual influence, and the parameter items tested under the same channel can be trimmed and the parameter items tested by the previous channel can also be trimmed under the gated testing and trimming channel.

According to the above design principle, taking a system for testing 6 trimming channels as an example, 3 parameter items to be tested are a bandgap reference voltage VREF, an oscillation frequency OSC of an oscillator, and a constant voltage threshold VFB, respectively, wherein the bandgap reference voltage determines a reference voltage and a bias current inside a chip by the VREF, and other parameter items are affected, so that the test and the trimming are preferentially performed, and 2 trimming bits need to be arranged according to the initial value distribution of the bandgap reference and the designed trimming step diameter and trimming range; the two parameters of the oscillation frequency OSC and the constant voltage threshold VFB are independent after the bandgap reference voltage is determined, and the oscillation frequency OSC only needs to be tested and does not need to be modified; the constant voltage threshold VFB needs to be adjusted by 2 bits, and the final test adjustment of the constant voltage threshold VFB can be considered. In addition, a trimming lock bit is required, so that a total of 6 test trimming channels are required.

The sequence of test trimming is as follows:

channel 1: testing a band gap reference VREF and roughly adjusting a band gap reference voltage, and testing the band gap reference voltage after rough adjustment;

and (3) a channel 2: testing a band gap reference VREF, finely adjusting a band gap reference voltage, and testing the finely adjusted band gap reference voltage;

and (3) passage: testing the oscillation frequency OSC without trimming;

and (4) passage: testing a constant voltage threshold value VFB, roughly adjusting the constant voltage threshold value, and testing the constant voltage threshold value after rough adjustment;

passage 5: testing a constant voltage threshold value VFB, finely adjusting the constant voltage threshold value, and testing the finely adjusted constant voltage threshold value;

passage 6: reserving a test channel; and programming the highest position of the fuse wire, and solidifying trimming logic and trimming locking.

Fig. 17 is a flow chart of test trimming for pin multiplexing according to an embodiment of the present invention, and as shown in fig. 17, the method for test trimming for pin multiplexing includes:

s1702: the power supply voltage is electrified, and the enable signal is started;

s1704 a: multiplexing a pin MODE and adding a pulse signal, and enabling the chip to enter a testing and trimming MODE;

s1704 b: the multiplexing pin is grounded, and the chip enters a normal Flyback mode;

s1704 c: suspending the multiplexing pin, and enabling the chip to enter a Buck mode;

s1706: testing a band gap reference;

s1708: under the condition that the band gap reference test does not meet the precision, carrying out coarse band gap reference adjustment;

s1710: an oscillation frequency test is carried out, and under the condition that the band gap reference test in S1706 meets the precision, the oscillation frequency test is directly carried out;

s1712: carrying out band gap reference test under the condition that the oscillation frequency test meets the precision; if the accuracy is not satisfied, the flow is directly ended

S1714: performing band gap reference fine adjustment, and ending the process under the condition that the fine adjustment result does not meet the precision;

s1716: performing constant voltage threshold test under the condition that the precision is met after the band gap reference is finely adjusted, and directly adjusting and locking under the condition that the constant voltage threshold test meets the precision;

s1718: under the condition that the constant voltage threshold value test does not meet the precision, performing constant voltage threshold value coarse adjustment, and directly adjusting and locking the precision according to the result of the constant voltage coarse adjustment;

s1720: after the constant voltage threshold value is roughly adjusted, the constant voltage threshold value is tested under the condition that the precision is still not met;

s1722: performing constant-voltage threshold fine adjustment, and ending the process under the condition that the fine adjustment result does not meet the precision;

s1724: entering a reserved test channel under the condition that the fine adjustment result of the constant-pressure threshold meets the precision;

s1726: trimming and locking;

s1728: and ending the flow.

Fig. 18 is a waveform diagram of a test trimming system for pin multiplexing according to an embodiment of the present invention, as shown in fig. 18, the power-on of the chip supply voltage VIN, the start of the external enable signal EN, the enable signal EN1 established by the internal reference voltage bias current, and the waveform of the enable signal EN2 completed by the internal supply voltage under-voltage detection; the pulse waveform injected by the multiplexing pin 110 of the test and repair system is given; a mode selection signal FYB0_ BUCK1 generated by the mode selection block; 6-bit channel selection signals C <5:0> output by the channel selection module; and simultaneously, testing signals of the bandgap reference voltage VREF, the oscillation frequency OSC and the constant voltage threshold VFB tested in the test MODE of the multiplexing pin 110 are also given, wherein the fuse programming signals of the multiplexing pin MODE with the lengthening time and the high level are set in the solidification and locking of the 1 st channel reference voltage coarse tuning and the 4 th channel constant voltage threshold coarse tuning and the 6 th channel trimming.

In theory, the bandgap reference can be adjusted when the oscillation frequency is measured, but actually, in order to directly measure the voltage after the bandgap reference is adjusted, the channel 1 and the channel 2 are used for measuring and adjusting the bandgap reference voltage, and the channel 3 is used for independently measuring the oscillation frequency. The reserved test trimming channel can be skipped directly.

It should be understood that although the various steps in the flowcharts of fig. 9-12 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 9-12 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.

Specific limitations on the pin multiplexing test trimming system can be found in the above definitions of the test and trimming method for pin multiplexing. All or part of each module in the pin multiplexing test trimming method can be realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

It will be appreciated by those skilled in the art that the configurations shown in fig. 1-8 are only block diagrams of some of the configurations relevant to the present disclosure, and do not constitute a limitation on the computing devices to which the present disclosure may be applied, and that a particular computing device may include more or less components than those shown, or combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the computer program, the test trimming method for pin multiplexing is implemented.

In one embodiment, a computer readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, implements the pin multiplexing test trimming system described above.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A testing and trimming system for pin multiplexing is characterized in that the testing and trimming system for pin multiplexing is integrated on a chip and comprises a multiplexing pin, a mode selection module, a channel selection module, a testing module and a trimming module,

under the condition that the multiplexing pin inputs a pulse signal, the mode selection module inputs the pulse signal and outputs a clock signal to the channel selection module;

the channel selection module outputs a channel selection signal according to the clock signal, the channel selection module outputs the channel selection signal to the test module and the trimming module, the test module determines a test channel according to the channel selection signal, and the trimming module determines a trimming channel according to the channel selection signal;

under the condition that the multiplexing pin is suspended, the test module acquires a parameter item to be tested according to the test channel and outputs a test result of the parameter item to be tested to the multiplexing pin;

and according to the test result, under the condition that the trimming position corresponding to the trimming channel needs to be trimmed, a trimming indication signal is input into the multiplexing pin.

2. The pin multiplexing test trimming system of claim 1, wherein the mode selection module further outputs an operation mode selection signal to the chip according to the input signal of the multiplexing pin:

under the condition that the multiplexing pin inputs a grounding signal, triggering the Flyback working state of the chip;

under the condition that the multiplexing pin is suspended, triggering the working state of the chip Buck Buck;

and triggering the test trimming state of the chip under the state that the multiplexing pin inputs the pulse signal.

3. The pin multiplexing test trimming system of claim 1, wherein the mode selection module is further configured to output a first test trimming enable signal to the channel selection module and a second test trimming enable signal to the trimming module according to the input signal of the multiplexing pin;

under the condition that the multiplexing pin inputs a pulse signal, the first test trimming enabling signal indicates the channel selection module to output a channel selection signal according to the clock signal, and the second test trimming enabling signal indicates the trimming module to enter a trimming mode;

and under the condition that the multiplexing pin is suspended, the first test trimming enabling signal indicates that the channel selection module is in a non-channel selection mode, and the second test trimming enabling signal indicates that the trimming module is in a non-trimming mode.

4. The pin multiplexing test trimming system according to claim 3, wherein the trimming module inputs a chip enable signal, and when the chip enable signal and the second test trimming enable signal both indicate that the trimming module is in the trimming mode, the trimming module trims the trimming bit according to the test result; and the trimming module outputs the trimmed logic signal.

5. The pin multiplexing test trimming system according to claim 1, wherein the test module further inputs the parameter items to be tested of the chip and a test channel preset by the parameter items to be tested, and outputs the test result of the parameter items to be tested corresponding to the test channel according to the test channel.

6. A method for testing and trimming pin multiplexing is characterized by comprising the following steps:

under the condition that a multiplexing pin inputs a pulse signal, a mode selection module receives the pulse signal from the multiplexing pin, outputs a clock signal and sends the clock signal to a channel selection module;

the channel selection module gates a test channel and a trimming channel according to the clock signal;

under the condition that the multiplexing pin is suspended, the test module acquires the test result of the test channel and feeds the test result back to the multiplexing pin;

and according to the test result, under the condition that the trimming position corresponding to the trimming channel needs to be trimmed, inputting a trimming indication signal from the multiplexing pin, and triggering a trimming module to burn and write the trimming position fuse.

7. The method of claim 6, wherein the gating of the test channel and the trimming channel by the channel selection module according to the clock signal comprises:

the channel selection module detects the number of pulses input by the multiplexing pin by inputting the clock signal, and gates the test channel and the trimming channel according to the number of input pulses.

8. The method for testing and trimming pin multiplexing according to claim 6, wherein the method further comprises:

the mode selection module outputs a first test trimming enabling signal to the channel selection module according to the input signal of the multiplexing pin, and outputs a second test trimming enabling signal to the trimming module;

9. The method of claim 6, further comprising:

according to the input signal of the multiplexing pin, the mode selection module triggers different working modes of the chip,

and triggering the test trimming state of the chip under the state that the multiplexing pin inputs a pulse signal, wherein the test trimming system is integrated in the chip.

10. The method for testing and trimming pin multiplexing according to claim 6, wherein the method further comprises:

after test trimming is finished, inputting a pulse signal through the multiplexing pin, gating the highest position by the channel selection module, inputting a high level signal through the multiplexing pin, programming the highest position fuse to solidify the fuse programming array, and outputting the solidified logic signal by the trimming module.

11. The method of claim 6, wherein the obtaining the test result of the test channel and feeding back the test result to the multiplexing pin by the test module with the multiplexing pin floating comprises:

the testing module receives a parameter item to be tested of a chip and a testing channel preset by the parameter item;

and receiving the test channel, obtaining a test result of the parameter item corresponding to the test channel according to the test channel, and feeding the test result back to the multiplexing pin, wherein the test trimming system is integrated in the chip.

12. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method according to any of claims 6 to 11 are implemented by the processor when executing the computer program.

13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 6 to 11.