CN103853068B - Test control circuit and corresponding method for chip - Google Patents
Test control circuit and corresponding method for chip Download PDFInfo
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- CN103853068B CN103853068B CN201210528275.3A CN201210528275A CN103853068B CN 103853068 B CN103853068 B CN 103853068B CN 201210528275 A CN201210528275 A CN 201210528275A CN 103853068 B CN103853068 B CN 103853068B
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Abstract
The present invention relates to the test control circuit for chip and corresponding method.Such as, embodiments of the invention provide a kind of test control circuit for chip, and test control circuit is comprised in chip, and includes: the first terminal, is connected to the power supply terminal of chip；Second terminal, is connected in chip the test circuit of electrical characteristics for testing chip；And control module, operation produces at least one test control signal with supply voltage based on the chip received via the first terminal, and tests the operation of circuit with control to test circuit output test control signal via the second terminal.Also disclose the chip comprising this test control circuit and corresponding method.
Description
Technical field
Embodiments of the invention relate generally to circuit field, more particularly, to for chip
Test control circuit and corresponding method.
Background technology
Before chip is packaged and comes into operation, it usually needs the various electrical characteristics to chip
Test, such as the situation such as the resistance of each element, electric capacity, power in test chip.?
Know, in the chips in addition to there is the circuit part realized needed for its conventional func, logical
Often also include one piece for the test circuit that chip is carried out above-mentioned test.Traditionally, chip tool
There is special pin for test control signal being fed to test circuit, in order to control this test
Circuit enters and exits test pattern and perform various test operation.
But, the number of pins of a lot of conventional chips is limited.Such chip only comprises
Less pin, even some chip only have for connecting power supply and two pins on ground.?
In this case, it is difficult to even to chip input test control signal, thus cannot the most just cannot
Effectively control to perform test function to test circuit.
Summary of the invention
In order to solve the problems referred to above of the prior art and other potential problems, the present invention's
Embodiment provides a kind of test control circuit for chip and corresponding method.
In one aspect of the invention, it is provided that a kind of test control circuit for chip.This survey
Examination control circuit is comprised in chip and includes: the first terminal, is connected to described chip
Power supply terminal；Second terminal, the test circuit being connected in described chip, described test circuit
Operate to test the electrical characteristics of described chip；And control module, operation is with based on via described
The supply voltage of described chip that the first terminal receives and produce at least one test control signal,
And via described second terminal to described test circuit output at least one testing and control described
Signal is to control the operation of described test circuit.
In a second aspect of the present invention, it is provided that a kind of chip.This chip includes: power supply terminal,
It is connected to for the power supply for described chip power supply；For testing the survey of the electrical characteristics of described chip
Examination circuit；And the test control circuit of above-outlined.
In a third aspect of the present invention, it is provided that a kind of test control method for chip, described
Test circuit that chip comprises the electrical characteristics for testing described chip and described for controlling
The test control circuit of test circuit.The method includes: via the of described test control circuit
One terminal receives supply voltage from the power supply terminal of described chip；Produce according to described supply voltage
For controlling at least one test control signal of described test circuit；And via described test
Second terminal of control circuit is to described test circuit output at least one testing and control described letter
Number.
By being described below it will be appreciated that utilize embodiments of the invention, it is allowed to according to chip
The information carried in supply voltage generates control information, to control test circuit entrance or to leave survey
Die trial formula and perform various test function.In this way, efficiently solve due to number of pins
The limited inconvenience brought to chip testing of mesh.
Accompanying drawing explanation
By reading detailed description below with reference to accompanying drawing, the embodiment of the present invention above-mentioned and its
His objects, features and advantages will become prone to understand.In the accompanying drawings, with exemplary and unrestricted
The mode of property shows some embodiments of the present invention, wherein:
Fig. 1 shows the schematic block diagram of chip according to an illustrative embodiment of the invention；
Fig. 2 shows chip testing control circuit according to an illustrative embodiment of the invention
Schematic block diagram；
Fig. 3 shows chip testing control circuit according to an illustrative embodiment of the invention
Schematic block diagram；
Fig. 4 shows chip testing control circuit according to an illustrative embodiment of the invention
Schematic block diagram；
Fig. 5 shows the schematic block diagram of chip according to an illustrative embodiment of the invention；
Fig. 6 shows the schematic block diagram of chip according to an illustrative embodiment of the invention；
And
Fig. 7 shows chip testing control method according to an illustrative embodiment of the invention
Indicative flowchart.
In the accompanying drawings, identical label refers to same or analogous element.
Detailed description of the invention
Some exemplary embodiments shown in below with reference to the accompanying drawings describe the former of the present invention
Reason and spirit.Should be appreciated that providing these embodiments is only used to make those skilled in the art
Better understood when and then realize the present invention, and limit the model of the present invention the most by any way
Enclose.
The general thought of the present invention is: the supply voltage that can be received by the power supply terminal of chip
The test control circuit being fed in chip, to allow test control circuit according to supply voltage institute
The information (such as, signal pattern, signal time characteristic etc.) carried to survey in control chip
The operation of examination circuit.Especially, in the case of guaranteeing chip not to be caused damage, can be in order to
Drive with the non-rated operational voltage of this chip and control to test circuit.
Noting, in the following description, term " connects " and refers in any suitable manner by two
Individual object is coupled, including being directly connected to also include being indirectly connected with.
Referring first to Fig. 1, it illustrates chip 100 according to an illustrative embodiment of the invention
Schematic block diagram.As it can be seen, chip 100 includes test control circuit 101, test electricity
Road 102 and functional circuit 103.Test control circuit 101 is connected with test circuit 102,
And operate the operation to control test circuit 102 and state.
Test circuit 102 operates to be surveyed with the various electrical properties to chip 100 and element thereof
Examination.These tests include any being currently known or the test of exploitation in the future, such as, measure chip
In the resistance of various elements, electric capacity, power, fusing, etc..The scope of the present invention is at this
Aspect is unrestricted.Test test function performed by circuit 102 generally encapsulates at chip 100
Complete with the test phase before using.The 26S Proteasome Structure and Function of test circuit 102 is in the art
It is known, does not repeats them here.And, any kind of test circuit 102 all can be with this
Inventive embodiment is used in combination, and the scope of the present invention is not limited in this respect.Functional circuit
103 is the circuit module of the function for realizing chip 100 self.
As it is shown in figure 1, chip 100 includes power supply terminal 104 and ground terminal 105.Power supply
Terminal 104 connects the power supply (VDD) of most chip power supply, and ground terminal is connected to the ground
(VSS).Power supply terminal 104 is connected with test control circuit 101 so that testing and control electricity
Road 101 can receive the supply voltage of chip 100, and in order to control to test the behaviour of circuit 102
Make.
Especially, according to embodiments of the invention, test control circuit 101 operate with in response to
It is in the supply voltage of the non-rated voltage level of chip, and generates at least one test corresponding
Control signal is to control the operation of test circuit 102.Such as, such as the specified electricity of fruit chip 100
Pressure is 5V, but it can tolerate and exceed the voltage less than 10V, then test control circuit
101 operations are to generate test control signal to control based on the supply voltage in the range of 5V-10V
Test circuit 102.Equally, ensure that normal at more than 3.3V such as fruit chip 100
Operation, then the supply voltage in the range of test control circuit 101 operates to utilize 3.3V-5V comes
Generate test control signal to control test circuit 102.In other words, according to the enforcement of the present invention
Example, it is allowed to test control circuit 101 is in response to the supply voltage being in overvoltage or low-pressure state
Control to test the operation of circuit 102.The 26S Proteasome Structure and Function of test control circuit 101 will under
Literary composition describes in detail.
Utilize the structure shown in Fig. 1, it is not necessary to chip 100 have special pin, terminal or
Person's lead-in wire just can conveniently and effectively control to test the work of circuit 102.This is useful,
It is especially true for the chip that number of pins is limited.
Below with reference to Fig. 2, it illustrates test control according to an illustrative embodiment of the invention
The high-level schematic block diagram of circuit 101 processed.As described above, test control circuit 101 quilt
It is included in chip 100.As in figure 2 it is shown, test control circuit 101 includes the first terminal 201
With the second terminal 202.The first terminal 201 is connected to the power supply terminal 104 of chip 100, the
Two-terminal 202 is connected to the test circuit 102 in chip 100.
It addition, test control circuit 101 includes control module 203, its operation with based on via
The supply voltage of the chip 100 that the first terminal 201 receives from chip power terminal 104 and produce
Raw test control signal.Control module 203 also operates with electric to test via the second terminal 202
Road 102 exports this test control signal, in order to control the operation of test circuit 102.Such as,
In response to different supply voltages, control module 203 can produce different test control signals,
Such as to control test circuit 102 to enter test pattern, perform the various electricity to chip 100
The test of characteristic and/or exit test pattern.
According to certain embodiments of the present invention, control module 203 operates with based on chip 100
The signal pattern (pattern) of supply voltage generates corresponding test control signal, thus controls
The operation of test circuit 102.Fig. 3 shows the exemplary embodiment of a this respect.
In the embodiment shown in fig. 3, test control circuit 101 includes comparator 301, its
Including in-phase input end 302, inverting input 303 and outfan 304.As it is shown on figure 3,
In-phase input end 302 is connected to the first terminal 201 of test control circuit 101 (in this instance
Connecting via division module 305, this also will be explained below), inverting input 303 connects
To a reference voltage, and outfan 304 is connected to control module 203.
Reference voltage is predetermined reference voltage.When supply voltage is higher than reference voltage,
Think that the signal logic that supply voltage carries is " high " (logical one)；Otherwise, work as electricity
When source voltage is less than reference voltage, it is believed that the signal logic that supply voltage carries (is patrolled for " low "
Collect " 0 ").Consider a concrete example, it is assumed that test control circuit 101 utilizes 3.3-5V
The supply voltage of this scope controls to test the operation of circuit 102.Such as can be by benchmark electricity
Pressure is chosen as 3.75V.Now, if supply voltage is higher than 3.75V, then comparator 301
The signal logic of outfan 304 output is " 1 "；If supply voltage is less than 3.75V, then than
The signal logic of outfan 304 output of relatively device 301 is " 0 ".In this way, create
The signal waveform of supply voltage, i.e. parsed the pattern of supply voltage.Comparator 304 is grasped
Make the signal pattern of supply voltage is fed to control module 203 via outfan 304, with
Just control module operation produces corresponding testing and control with the pattern according to described supply voltage
Signal.
Note, figure 3 illustrates and an above-described only example, be not intended to limit
Comparator 301 processed and the annexation of miscellaneous part.Such as, in other embodiments, compare
The normal phase input end 302 of device 301 is connectable to reference voltage, and inverting input 303 connects
To the first terminal 201.Now, if supply voltage is higher than reference voltage, then comparator 301
Outfan 304 output signal logic be " 0 "；If supply voltage is less than reference voltage,
Then the signal logic of outfan 304 output of comparator 301 is " 1 ".In other words, according to
Embodiments of the invention, the normal phase input end 302 of comparator 301 is connectable to the first terminal 201
With in reference voltage, inverting input 303 is then connected to the first terminal 201 and ginseng
Examine in voltage another.
Especially, in the embodiment shown in fig. 3, including optional division module 305, its
It is connected to the first terminal 201 of test control circuit 101 and the in-phase input end of comparator 301
With between 302 or inverting input 303 (in this instance, being in-phase input end 302).
The effect of division module 305 is that supply voltage reduces predetermined ratio, after then reducing
Supply voltage is fed to comparator 301.This is done to ensure that comparator 301 safely, have
The operation of effect.Correspondingly, reference voltage should reduce according to identical ratio.
Specifically, as it is shown on figure 3, division module 305 includes the resistor 306 being connected in series
With resistor 307.Resistor 306 is connected to the power end of chip via the first terminal 201
Son 104, thus receive supply voltage；Resistor 307 is connected to the ground VSS.By suitably
The resistance value arranging resistor 306 and 307 can realize voltage divide function.Such as, still consider
Example described above, test control circuit 101 utilizes the power supply electricity of this scope of 3.3V-5V
Pressure controls to test the operation of circuit 102, and reference voltage is selected as 3.75V.Now,
If the ratio of the resistance value of resistor 306 and 307 being set to 1: 2, then at dividing point 308
Normal phase input end 302 from place to comparator 301 feed voltage by be reference voltage three/
One, i.e. 1.25V.Correspondingly, the benchmark of the inverting input 303 of comparator 301 it is fed to
Voltage is adjusted downward to 1.25V the most in proportion.Thus, it is possible to utilize the supply voltage after blood pressure lowering and base
Quasi-voltage resolves the signal pattern that supply voltage carries.
Should be appreciated that division module 305 is optional.In other words, the positive of comparator 301
Input 301 or inverting input 301 can be directly connected to the first terminal 201 thus connect
Receive the supply voltage of chip 100.And, the structure in division module 305 is also only one
Feasible example.Any structure being capable of dividing potential drop/buck functionality all can be with the enforcement of the present invention
Example is used in combination.Those skilled in the art are it is contemplated that resolve supply voltage by means of comparator
The signal pattern carried is only a kind of example, and it is any that other are currently known or develop in the future
Proper technology means all can be used in combination with embodiments of the invention.The scope of the present invention is at these
Aspect is unrestricted.
In response to the signal pattern of supply voltage, control module 203 operates to produce corresponding survey
Examination control signal is to control the operation of test circuit 102.According to embodiments of the invention, permissible
Pre-defined test function corresponding to supply voltage pattern.In other words, at supply voltage pattern
And predetermined mapping can be there is between the operation of test circuit 102 so that control module 203 is grasped
Make to produce test control signal to map according to this type of.
As an example, can limit: the signal pattern " 10010001 " that supply voltage carries
Can correspond to operate " entrance test pattern ".Correspondingly, when test control circuit 101
Control module 203 detects when the signal pattern that supply voltage carries is " 10010001 ", produces
Raw test control signal enters test pattern with order test circuit 102.And for example, supply voltage
The signal pattern " 10010000 " carried can correspond to operate " leaving test pattern ", etc.
Deng.These are merely exemplary, are not intended to limit the scope of the present invention.
In addition to signal pattern based on supply voltage controls to test circuit or as mending
Fill, it is also possible to utilize clock information determine the supply voltage of chip 100 in time-related characteristic,
So that test control circuit 101 produces corresponding test control signal.Fig. 4 shows this respect
An example.
In the embodiment shown in fig. 4, in addition to the first terminal 201 and the second terminal 202,
Test control circuit 101 also includes the 3rd terminal 401, and it is connected to clock source 402.Clock
Source 402 operates to produce clock signal, and clock signal is fed via the 3rd terminal 401
To test control circuit 101.In such embodiments, the control of test control circuit 101
Module 203 operates with based on the chip power voltage received via the first terminal 201, and
The clock signal received via the 3rd terminal 401, and produce described test control signal.
Such as, in certain embodiments, control module 203 can include that pulse width determines mould
Block (not shown), its operation receives from clock source 402 via the 3rd terminal 401 with utilization
Clock signal determines the pulse width information of chip power voltage.Specifically, clock is utilized to believe
Number, pulse width determines the number of the module operation supply voltage pulse to determine appearance per second,
I.e. " pulse frequency ", its inverse is pulse width.For calculating the circuit structure of pulse width
It is to it known in the art, not repeat them here with function.
Alternatively or additionally, control module 203 can include that pulse duty factor determines that module is (not
Illustrate), operate the clock signal received from clock source 402 with utilization via the 3rd terminal 401
Determine the duty cycle information of chip power voltage.Such as, clock signal, pulse duty factor are utilized
Determine that module operation is to determine that positive pulse takies in one section of stream time time is with total
The ratio of time, i.e. dutycycle.It is this for calculating circuit structure and the function of pulse duty factor
Known to field, do not repeat them here.
Control module 203 operates and produces accordingly in order to by this time response of supply voltage
Control signal.For example, it is possible to regulation: if the dutycycle of supply voltage exceedes certain threshold value,
Then instruction test circuit 102 enters test pattern, etc..Those skilled in the art can basis
It is actually needed and flexibly sets reflecting between the time response of supply voltage and corresponding test operation
Penetrate relation.It is appreciated that the time response of supply voltage provides more for controlling test circuit
Abundant means and order semanteme.
Noting, above-described is only several examples.Believe based on clock information and supply voltage
Breath, control module 203 may determine that or calculate the other times characteristic of supply voltage, and not only
It is limited to width and the dutycycle of pulse.
It addition, according to embodiments of the invention, it is internal that clock source 402 may be located at chip 100,
The crystal oscillator (OSC) e.g. comprised in chip 100.Now, test control circuit
The clock letter that 3rd terminal 401 of 101 is connected to this internal clock source and reception is generated by
Number.Fig. 5 shows such embodiment.Alternatively, implement at another shown in Fig. 6
In example, chip 100 has additional terminal 601.Now, the 3rd terminal 401 can be connected to
This additional terminal 601, and via this additional terminal from the clock source 402 outside chip 100
Receive clock signal.The scope of the present invention is not limited in this respect.
Note, above with reference to being not mutual exclusion between the embodiment that each accompanying drawing describes.On the contrary,
Some or all feature in these embodiments can be combined with each other.In other words, the reality of the present invention
Execute example and allow signal pattern based on supply voltage, time response or the combination of the two, produce
Raw for controlling to test the corresponding test control signal of circuit.
Below with reference to Fig. 7, it illustrates chip according to an illustrative embodiment of the invention and survey
The indicative flowchart of examination control method.As it has been described above, chip comprises for testing described chip
Electrical characteristics test circuit and for controlling the test control circuit of described test circuit.Can
To understand, the method shown in Fig. 7 can be by the chip test circuit described above with reference to Fig. 1-Fig. 6
101 perform.
After method starts, in step S701, via the first terminal of described test control circuit
Receive the supply voltage of described chip.
It follows that in step S702, produce according to described supply voltage and be used for controlling to test circuit
At least one test control signal of operation.In some alternative embodiment, this may include that
Utilize a comparator that supply voltage and reference voltage are compared, wherein said comparator
In-phase input end is connected to one in described the first terminal and reference voltage, described comparator
Inverting input is connected to another in described the first terminal and described reference voltage；Based on institute
State and compare the pattern producing described supply voltage；And via the outfan of described comparator to institute
State control module and export the pattern of described supply voltage for producing corresponding testing and control letter
Number.
Alternatively or additionally, in some alternative embodiment, produce according to described supply voltage
At least one test control signal may include that the 3rd terminal via described test control circuit
Clock signal is received from clock source；And produce based on described supply voltage and described clock signal
Described test control signal.Alternatively, produce based on described supply voltage and described clock signal
Described test control signal include following at least one: utilize described clock signal to determine described electricity
The pulse width information of source voltage；And utilize described clock signal to determine described supply voltage
Pulse duty factor information.
According to some alternative embodiment, via the 3rd terminal of described test control circuit from clock
Source receives clock signal and includes when the clock source from described chip internal or outside receives described
Clock signal.
According to some alternative embodiment, it is in institute for controlling to test the supply voltage of circuit operation
State the non-rated voltage level of chip.
It follows that method proceeds to step S703, at this via the of described test control circuit
Two-terminal exports described test control signal to control described test circuit to described test circuit
Operation.Such as, as described above, the signal pattern of chip power voltage can be pre-defined
And/or the order of time response is semantic, in order to drive test circuit to perform corresponding operation.
Method terminates after step S703.
It is appreciated that the method for reference Fig. 7 description is by the test described above with reference to Fig. 1-Fig. 6
Control circuit performs.Thus, each feature described above in association with Fig. 1-Fig. 6 is equally applicable to
The method, does not repeats them here.
It is hereinbefore described some embodiments of the invention.Note, art as used herein
Language is not intended as limit publicity content only for describing specific embodiment.Such as, unless on
The most separately having and express, singulative as used herein "/a kind of " and " being somebody's turn to do " are intended to also include
Plural form.It will also be appreciated that word " includes " specifying when being used in this specification there is statement
Feature, one integral piece, step, operation, unit and/or parts and do not get rid of existence or add one
Individual or multiple other features, one integral piece, step, operation, unit, parts and/or a combination thereof.
Although describe some embodiments of the present invention above with reference to accompanying drawing, but should
Understanding, the present invention is not limited to disclosed specific embodiment.It is contemplated that contain appended power
Various amendments included in the spirit and scope that profit requires and equivalent arrangements.Claims
Scope meet broadest explanation, thus comprise all such amendments and equivalent structure and merit
Energy.
Claims (17)
1., for a test control circuit for chip, described test control circuit is comprised in
In described chip, and include:
The first terminal, is connected to the power supply terminal of described chip；
Second terminal, the test circuit being connected in described chip, described test circuit operation
To test the electrical characteristics of described chip；And
Control module, operation is to connect with via described the first terminal based on to a reference voltage
The comparative result of band pattern supply voltage received and produce at least one test control signal, and
And via described second terminal to described test circuit output at least one testing and control described
Signal is to control the operation of described test circuit.
Test control circuit the most according to claim 1, farther includes:
Comparator, including in-phase input end, inverting input and outfan, described homophase is defeated
Enter to hold be connected in described the first terminal and described reference voltage, described anti-phase input
End be connected in described the first terminal and described reference voltage another, described lead-out terminal
Being connected to described control module, described comparator operations is with by by described band pattern power supply electricity
Pressure and described reference voltage compare and produce the pattern of described band pattern supply voltage, and
And export described band pattern supply voltage via described lead-out terminal to described control module
Pattern,
Wherein said control module operates with the pattern according to described band pattern supply voltage
Produce at least one test control signal described.
Test control circuit the most according to claim 2, farther includes:
Division module, is connected to the described homophase input of described the first terminal and described comparator
Between end or described inverting input, operate to reduce described band pattern electricity according to predetermined ratio
Source voltage, and will reduce after described band pattern supply voltage be fed to described comparator with
Just compare with the described reference voltage reduced according to described predetermined ratio.
Test control circuit the most according to claim 1, farther includes:
3rd terminal, is connected to clock source, and described clock source operates to produce clock signal；
Wherein said control module operates with based on described band pattern supply voltage with via institute
State described clock signal that the 3rd terminal receives from described clock source and described in producing at least one
Individual test control signal.
Test control circuit the most according to claim 4, described control module include with
Descend at least one:
Pulse width determines module, operates to utilize via described in described 3rd terminal reception
Clock signal determines the pulse width information of described band pattern supply voltage；And
Pulse duty factor determines module, operates to utilize the institute via described 3rd terminal reception
State clock signal and determine the pulse duty factor information of described band pattern supply voltage.
Test control circuit the most according to claim 4, wherein said 3rd terminal is even
It is connected to the clock source of described chip internal, or connects via the additional terminal of described chip
Clock source to described chip exterior.
7. according to the test control circuit described in any one of claim 1-6, wherein said control
Molding block operations is to be in the non-specified of described chip in response to described band pattern supply voltage
Voltage levvl and produce at least one test control signal described.
8. a chip, including:
Power supply terminal, is connected to for the power supply for described chip power supply；
For testing the test circuit of the electrical characteristics of described chip；And
According to the test control circuit described in any one of claim 1-7.
Chip the most according to claim 8, farther includes:
Clock source, is connected to described test control circuit, and operates to produce clock signal
And give described test control circuit by described clock signal feeds.
Chip the most according to claim 8, farther includes:
Additional terminal, externally connected clock source and described test control circuit, and operate
Described test control circuit is given with the clock signal feeds that produced by described external clock reference.
11. 1 kinds of methods controlled for chip testing, described chip comprises for testing
State the test circuit of the electrical characteristics of chip and for controlling the test control of described test circuit
Circuit processed, described method includes:
Connect from the power supply terminal of described chip via the first terminal of described test control circuit
Take-up pattern supply voltage；
According to the comparative result generation to a reference voltage with described band pattern supply voltage
For controlling at least one test control signal of described test circuit；And
The second terminal via described test control circuit is described to the output of described test circuit
At least one test control signal.
12. methods according to claim 11, wherein according to a reference voltage with
The comparative result of described band pattern supply voltage produces for controlling described test circuit extremely
A few test control signal includes:
Utilize comparator that described band pattern supply voltage and described reference voltage are compared,
The in-phase input end of described comparator is connected in described the first terminal and described reference voltage
One, and the inverting input of described comparator is connected to described the first terminal and described
Another in reference voltage；
The pattern of described band pattern supply voltage is produced based on described comparison；And
Described band pattern electricity is exported to described control module via the outfan of described comparator
The pattern of source voltage is for producing corresponding test control signal.
13. methods according to claim 12, wherein utilize comparator to described band figure
Case supply voltage and described reference voltage compare and include:
A division module is utilized to reduce described band pattern supply voltage, institute according to predetermined ratio
State division module and be connected to the described in-phase input end of described the first terminal and described comparator
And between in described inverting input；And
Will reduce after described band pattern supply voltage be fed to described comparator in case with by
The described reference voltage reduced according to described predetermined ratio compares.
14. methods according to claim 11, wherein according to a reference voltage with
The comparative result of described band pattern supply voltage produces for controlling described test circuit extremely
A few test control signal includes:
Clock signal is received from clock source via the 3rd terminal of described test control circuit；With
And
At least one test control described is produced based on described supply voltage and described clock signal
Signal processed.
15. methods according to claim 14, wherein based on described supply voltage and institute
State clock signal produce at least one test control signal described include following at least one:
Described clock signal is utilized to determine the pulse width information of described supply voltage；And
Described clock signal is utilized to determine the pulse duty factor information of described supply voltage.
16. methods according to claim 14, wherein via described test control circuit
The 3rd terminal from clock source receive clock signal include:
Clock source from described chip internal or outside receives described clock signal.
17. according to the method described in any one of claim 11-16, wherein said band pattern
Supply voltage is in the non-rated voltage level of described chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210528275.3A CN103853068B (en) | 2012-12-05 | 2012-12-05 | Test control circuit and corresponding method for chip |
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| CN201210528275.3A CN103853068B (en) | 2012-12-05 | 2012-12-05 | Test control circuit and corresponding method for chip |
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| TW202024971A (en) * | 2018-12-26 | 2020-07-01 | 新唐科技股份有限公司 | Automatic chip verification system and the method thereof |
| CN109490761B (en) * | 2019-01-22 | 2024-03-01 | 上海艾为电子技术股份有限公司 | Test mode entering method and system |
| CN116520136B (en) * | 2023-06-07 | 2023-09-22 | 盈力半导体(上海)有限公司 | Control circuit, method and chip for preventing false triggering of test mode |
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| CN203084461U (en) * | 2012-12-05 | 2013-07-24 | 艾尔瓦特集成电路科技（天津）有限公司 | Test control circuit used for chip |
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| JP4740788B2 (en) * | 2006-04-20 | 2011-08-03 | パナソニック株式会社 | Semiconductor integrated circuit |
| CN201035091Y (en) * | 2007-04-13 | 2008-03-12 | 华中科技大学 | Output electric voltage status indication circuit used for electric power chip |
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| CN203084461U (en) * | 2012-12-05 | 2013-07-24 | 艾尔瓦特集成电路科技（天津）有限公司 | Test control circuit used for chip |
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