CN115424653A - FLASH testing device, FLASH testing method and storage medium - Google Patents
FLASH testing device, FLASH testing method and storage medium Download PDFInfo
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- CN115424653A CN115424653A CN202211110178.2A CN202211110178A CN115424653A CN 115424653 A CN115424653 A CN 115424653A CN 202211110178 A CN202211110178 A CN 202211110178A CN 115424653 A CN115424653 A CN 115424653A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1208—Error catch memory
Abstract
The application discloses a FLASH testing device, a FLASH testing method and a storage medium, which relate to the technical field of storage chip testing and comprise the following steps: the FLASH chip testing device comprises a testing seat, a voltage adjusting module, a current collecting module, a read-write control module and a master control module, wherein the testing seat is used for installing a FLASH chip, the voltage adjusting module is electrically connected with the testing seat and is used for adjusting the testing voltage input to the FLASH chip step by step, the current collecting module is electrically connected with the testing seat and is used for collecting the testing current and the standby current generated by the FLASH chip according to the gradually adjusted testing voltage, the read-write control module is electrically connected with the testing seat and is used for writing the stored data into the FLASH chip or reading the stored data out, and the master control module is used for comparing the written data with the read-out data and marking the blocks with inconsistent written data and read-out data in the FLASH chip to generate the bad block information of the FLASH chip. The method and the device can adapt to read-write tests and current tests under different working voltages, and test conditions are enriched.
Description
Technical Field
The present disclosure relates to the field of memory chip testing technologies, and in particular, to a FLASH testing apparatus, a testing method, and a storage medium.
Background
FLASH is widely used in electronic equipment, the interior of FLASH is composed of a plurality of blocks, the stability and the safety of an internal storage block are paid more and more attention by people, an unstable FLASH block is found out, and the unstable FLASH block is marked and is not accessed in the using process, so that the data is prevented from being placed in an unstable storage space, the correctness of the data of the electronic equipment and the stability of a system can be effectively ensured, the use stability of the electronic equipment is ensured, and the service life of the electronic equipment is longer.
The existing FLASH test mainly aims at read-write operation, and involves less work voltage condition test of a FLASH chip, however, deviation may occur in detection of bad blocks under different work voltage conditions, and final FLASH classification is influenced.
Disclosure of Invention
The present application is directed to solving at least one of the problems in the prior art. Therefore, the application provides a FLASH testing device, a testing method and a storage medium, which can adapt to read-write testing and current testing under different working voltages, enrich testing conditions and improve FLASH classification accuracy.
In a first aspect, the present application provides a FLASH testing apparatus, including:
the testing seat is used for installing a FLASH chip;
the voltage adjusting module is electrically connected with the test seat and is used for inputting different test voltages to the FLASH chip;
the current acquisition module is electrically connected with the test seat and is used for acquiring the test current and the standby current of the FLASH chip;
the read-write control module is electrically connected with the test seat and is used for writing storage data into the FLASH chip or reading the storage data out;
the general control module is electrically connected with the voltage regulation module, the current acquisition module and the read-write control module, and the general control module is used for:
controlling the voltage regulating module to input different test voltages to the FLASH chip;
acquiring the test current and the standby current detected by the current detection module under different test voltages;
under different test voltages, generating first bad block information of the FLASH chip according to the written storage data of the read-write control module and the comparison value of the storage data;
and according to the first bad block information and the corresponding test current and standby current, the method is used for grading the quality of the FLASH chip.
The FLASH testing device according to the embodiment of the application has at least the following beneficial effects: the FLASH chip test method comprises the steps of adjusting the test voltage of the FLASH chip step by arranging a voltage adjusting module, enabling the FLASH chip to be tested in various voltage ranges, acquiring the test current and standby current under different test voltage conditions by arranging a current acquisition module, enriching the test data, writing data into or reading data from the FLASH chip by a read-write control module, controlling the work of the voltage adjusting module, the current acquisition module, the read-write control module and other modules by a master control module, comparing the data written into the read-write control module with the read data by the master control module, marking the blocks with inconsistent written data and read data in the FLASH chip, generating the bad block information of the FLASH chip, further enriching the test data by step by adjusting the voltage and detecting the current, and finding out the bad blocks of the FLASH chip by read-write comparison.
According to some embodiments of the present application, the off-line aging test device for a FLASH is placed in a high temperature cabinet when testing is performed, and the high temperature cabinet is used to provide a high temperature test environment for the FLASH chip.
According to some embodiments of the application, the voltage regulation module includes digital potentiometer, step-down module, FLASH testing arrangement still includes power module, power module be used for doing the power supply of total control module, total control module still with digital potentiometer electricity is connected, digital potentiometer's output with the input electricity of step-down module is connected, step-down module's output with the power supply pin electricity of test seat is connected.
According to some embodiments of the present application, the current collection module includes two high-precision current sampling chips, and the two current sampling chips are electrically connected to the standby current interface and the test current interface of the FLASH chip through the test socket, respectively.
According to some embodiments of the application, the digital tube grading device further comprises a display module, wherein the display module comprises a plurality of digital tubes, the digital tubes are electrically connected with the master control module, the master control module is further used for controlling the digital tubes to display the test current value and the standby current value, and the master control module is further used for grading the FLASH chip according to the bad block information of the FLASH chip and displaying the grading result on the digital tubes.
In a second aspect, the present application provides a FLASH testing method applied to the FLASH testing apparatus, where the FLASH testing apparatus includes:
the testing seat is used for installing a FLASH chip;
the voltage adjusting module is electrically connected with the test seat and is used for inputting different test voltages to the FLASH chip;
the current acquisition module is electrically connected with the test seat and is used for acquiring the test current and the standby current of the FLASH chip;
the read-write control module is electrically connected with the test seat and is used for writing storage data into the FLASH chip or reading the storage data out;
the FLASH testing method comprises the following steps:
a preset time interval is taken as a test period, and a driving voltage is provided for a power supply interface of the FLASH chip for testing through the voltage regulation module in each test period; the driving voltage is sequentially increased progressively according to the test times;
in each test period, performing data reading and writing on the FLASH chip through the reading and writing control module, and acquiring the standby current and the test current of the FLASH chip through the current acquisition module;
when the master control module judges that the written data is inconsistent with the read data, generating corresponding bad block information through the master control module; the bad block information comprises position information and quantity information of the bad block on the FLASH chip;
grading the FLASH chip according to the bad block information, the standby current and the test current to generate FLASH grading information;
and outputting the FLASH grading information.
According to some embodiments of the present application, the reading and writing of data to the FLASH chip by the reading and writing control module includes:
writing a section of data into the read-write control module; the section of data is a source file to be referred to;
sequentially writing and reading a test file into and from each page in each block according to the arrangement sequence of the blocks in the FLASH chip, wherein the test file is derived from the source file to be referred to;
according to some embodiments of the present application, when the capacity of the FLASH chip is greater than a preset capacity threshold, performing data reading and writing on the FLASH chip by the reading and writing control module includes:
writing a section of data into the read-write control module; the section of data is a source file to be referred to;
and writing and reading test files in each block in sequence according to the arrangement sequence of the blocks in the FLASH chip, wherein the test files are derived from the source file to be referred.
According to some embodiments of the present application, after the master control module determines that the written data is inconsistent with the read data, the master control module generates corresponding bad block information, and the FLASH test method further includes:
and storing the bad block information in the last test period as final bad block information to be stored in a first block of the FLASH chip.
In a third aspect, the present application provides a computer-readable storage medium, which includes the FLASH testing method described in any one of the embodiments of the second aspect.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
Additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram illustrating the connection of modules of a FLASH testing apparatus according to some embodiments of the present application;
FIG. 2 is a schematic flow chart of a FLASH testing method according to some embodiments of the present application;
fig. 3 is a schematic diagram of a FLASH bad block detection process according to some embodiments of the present application.
The reference numbers are as follows:
a FLASH testing device 100; a test socket 110; a voltage regulation module 120; a current collection module 130; a read-write control module 140; a master control module 150; a display module 160; a USB interface module 170; a power module 180.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it is to be understood that the positional descriptions, such as the directions of up, down, front, rear, left, right, etc., referred to herein are based on the directions or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular direction, be constructed and operated in a particular direction, and thus, should not be construed as limiting the present application.
In the description of the present application, if there are first and second described only for the purpose of distinguishing technical features, it is not understood that relative importance is indicated or implied or that the number of indicated technical features or the precedence of the indicated technical features is implicitly indicated or implied.
In the description of the present application, unless otherwise expressly limited, terms such as set, mounted, connected and the like should be construed broadly, and those skilled in the art can reasonably determine the specific meaning of the terms in the present application by combining the detailed contents of the technical solutions.
Referring to fig. 1, in a first aspect, the present application provides a FLASH testing apparatus, including: the testing seat is used for installing the FLASH chip, and can be installed on a testing frame, meanwhile, the testing seat can be of an ejector pin structure, the voltage adjusting module is electrically connected with the testing seat, and the voltage adjusting module is used for adjusting the testing voltage input to the FLASH chip step by step; the current acquisition module is electrically connected with the test seat and is used for acquiring test current and standby current generated by the FLASH chip according to the test voltage adjusted step by step; the read-write control module is electrically connected with the test seat and is used for writing the storage data into the FLASH chip or reading the storage data out; the general control module is electrically connected with the voltage regulation module, the current acquisition module and the read-write control module, and is used for controlling the voltage regulation module to regulate voltage, controlling the current detection module to detect current, controlling the read-write control module to write data and read data, comparing the written data with the read data, and generating bad block information of the FLASH chip.
Therefore, the test voltage of the FLASH is regulated step by arranging the voltage regulating module, so that the FLASH chip can be tested in various voltage ranges, the test current and the standby current under different test voltage conditions can be collected by arranging the current collecting module, the test data is enriched, meanwhile, the data is written into or read out from the FLASH chip by the read-write control module, the work of the voltage regulating module, the current collecting module, the read-write control module and other modules is controlled by the master control module, the data written into the read-write control module and the read-write control module are compared by the master control module, the blocks with inconsistent written data and read-out data in the FLASH chip are marked, the bad block information of the FLASH chip is generated, further, the test data is enriched by step voltage regulation and current detection, meanwhile, the bad blocks of the FLASH chip are found out by read-write comparison, and the probability that the bad blocks under the specific voltage condition cannot be exposed due to small test points is reduced because of more test voltage points and the test times and conditions are abundant.
It can be understood that the FLASH testing device also comprises a high-temperature cabinet, the high-temperature cabinet is used for providing a high-temperature testing environment for the FLASH chip, and when the FLASH testing is carried out, the FLASH testing device consisting of the testing seat, the voltage adjusting module, the current collecting module, the read-write control module and the master control module is placed in the high-temperature cabinet, so that the voltage and current testing and the read-write testing are carried out under the high-temperature environment. In some embodiments, a power interface is arranged in the high-temperature cabinet,
it can be understood that the voltage regulation module comprises a digital potentiometer and a voltage reduction module, the FLASH testing device further comprises a power supply module, the power supply module is used for supplying power to the master control module, the master control module is further electrically connected with the digital potentiometer, the input end of the output voltage reduction module of the digital potentiometer is electrically connected, and the output end of the voltage reduction module is electrically connected with the power supply pin of the testing seat. The digital potentiometer is equivalent to a variable resistor, and the voltage input into the voltage reduction module can be adjusted by controlling the digital potentiometer through the master control module, so that the power supply voltage input into the FLASH chip is indirectly adjusted through the voltage reduction circuit.
It can be understood that the current acquisition module comprises two high-precision current sampling chips, and the two current sampling chips are respectively and electrically connected with the standby current interface and the test current interface of the FLASH chip through the test socket. In some embodiments, the INA219 is adopted as the current sampling chip, the detection precision can reach 10uA, the detection is accurate, and the performances of the Flash chip under different voltages and temperatures can be well compared, so that the test purpose is realized.
It can be understood that the FLASH test device further comprises a display module, the display module comprises a plurality of nixie tubes, the plurality of nixie tubes are electrically connected with the master control module, the master control module is further used for controlling the nixie tubes to display a test current value and a standby current value, and the master control module is further used for grading the FLASH chip according to the bad block information of the FLASH chip and displaying the grading result on the nixie tubes.
In a second aspect, the present application provides a FLASH test method applied to the FLASH test apparatus of the first aspect, where the FLASH test apparatus includes: the device comprises a test seat, a voltage regulation module, a current acquisition module and a read-write control module, wherein the test seat is used for installing a FLASH chip; the voltage regulating module is electrically connected with the test seat and is used for inputting different test voltages to the FLASH chip; the current acquisition module is electrically connected with the test seat and is used for acquiring the test current and the standby current of the FLASH chip; the read-write control module is electrically connected with the test seat and used for writing storage data into the FLASH chip or reading the storage data out;
the FLASH testing method comprises but is not limited to the following steps:
step S100, respectively providing driving voltage to a power supply interface of the FLASH chip through the voltage regulation module in a plurality of preset time intervals; the time interval is a testing period when FLASH testing is carried out, and the driving voltage is sequentially increased according to the testing times of the FLASH testing;
in some embodiments, the FLASH test device will perform a plurality of complete test procedures, and the supply voltage of the FLASH test chip will be changed after each procedure is completed, taking the application as an example, the initial supply voltage of the FLASH test device is set to 2.7V, and then the supply voltage is increased by 0.3V after each test is completed, so as to finally form a series of test voltage nodes of 2.7V,3.0V,3.3V,3.6V, and each test voltage node will perform a complete FLASH test.
Step S200, reading and writing data of the FLASH chip through the reading and writing control module, and collecting standby current and test current of the FLASH chip through the current collection module;
step S300, comparing the written data with the read data through the master control module, and if the written data is inconsistent with the read data, marking the block area where the data is located and generating bad block information; the bad block information comprises position information and quantity information of the bad block on the FLASH chip;
step S400, grading the FLASH chip according to the bad block data to generate grading information;
in some embodiments, when the detected bad blocks account for 10% of the total blocks of Flash, which indicates that the Flash storage has a great risk, the Flash is marked and processed as a defective product. The proportion requirement of the bad blocks to the total FLASH block number can be reasonably adjusted by a person skilled in the art according to the quality control requirement of the FLASH product, so as to realize different grading requirements.
And step S500, outputting the classification information, the test current and the standby current.
Therefore, by adjusting the power supply voltage of the FLASH step by step, each level of power supply voltage corresponds to a complete FLASH test flow, each complete test flow comprises the detection of the test current and the standby current under the corresponding voltage, and the detection of bad blocks of the written data and the read data is compared, so that the bad block information is generated, the detection time is longer, more data are obtained, the stability of the FLASH under long-time and different working voltages can be reflected, and the FLASH test is more reliable and stable.
It can be understood that, the reading and writing of the data to the FLASH chip by the reading and writing control module includes, but is not limited to, the following steps:
step S210, writing a section of data into the read-write control module; the section of data is a source file to be referred to;
it can be understood that writing data to the read-write control module can be realized by setting a USB interface module in communication connection with the read-write control module, and data is transmitted to the read-write control module through the USB interface module by an upper computer such as a computer, so as to realize a function of writing a piece of data into the read-write control module.
Step S220, writing a test file into each page in each block in sequence according to the arrangement sequence of the blocks in the FLASH chip, wherein the test file is derived from the source file to be referred to;
in step S230, the test file written into each page in each block is read out.
It should be noted that, the internal storage of Flash is performed according to pages and blocks, each Page is 512Byte, one Block is composed of 32 pages, and Flash with different capacity sizes is composed of a corresponding number of blocks, block means, and Page means Page, when data read-write of the Flash chip is performed, a section of data is written in the read-write control module in advance, and is used as an operation template, and the read-write operation is performed on Flash to identify a storage bad Block therein. After the FLASH test device is powered on, when the FLASH function test is executed, the controller module 5 starts to scan the storage space in the FLASH. The controller module 5 operates in a small file mode, typically a data file with a size of 1KB, and according to the number of blocks marked by factory leaving, it detects from the first Block, writes data into each Page (Page) inside the Block, reads out the data, compares the data with the data written for the first time, and if the data are completely consistent, the Page is normal.
In a specific embodiment, the controller module 5 operates a first Page of a first Block of Flash, selects a segment of data stored in advance in the controller module 5, and writes 1 into all storage spaces in the first Page according to a data format of 0xFF, that is, all the pages are high level; sequentially operating, and writing the data into 32 pages in the Block; after the data writing operation is executed, the controller module 5 reads data in the Block, the control module 5 selects a corresponding Page in the Block according to a row and column address mode, reads the data in the Page, compares the Page with the data written in advance one by one, if a certain bit changes, the controller marks Page information with data problems in the 6 th Byte bit of the space area of the first Page of the Block, displays the Page information as a numerical value different from 0xff, and marks the whole Block as a Bad Block (Bad Block) after detecting the data at the position, and transfers the data of the Block to other good blocks. When the controller operates the storage space of the Block with data, after the operation is finished, the whole Block is erased, the written data is formatted, and the space inside the Block is ensured to have no data. All the storage blocks in the Flash are detected through the data writing and reading operations of one Page,
it is understood that step S300 further includes, but is not limited to, the following steps:
step S310, storing the bad block information in the first block of the FLASH chip.
In some embodiments, all storage blocks in Flash are detected through data writing and reading operations of one Page, bad Block information is stored in the first Block of Flash according to a detection result, a Block bad information table (BBT) is established, and good and bad blocks in Flash are managed; in subsequent use, a user firstly detects a bad block chain table of Flash and determines which blocks have problems, so that data is prevented from being written into the bad block chain table, and the storage stability is ensured.
It can be understood that, in the process of detecting bad blocks, especially for large-capacity Flash, the time required for reading and writing data by pages is very long, and the test pressure is increased. In each test system, a large file operation mode is also adopted, one block is directly written and read, then the data of one block is integrally compared, and if the read data is inconsistent with the pre-written data, the whole block is marked as a bad block. The operation of large files is adopted to scan and detect the whole block, so that the method is quick and convenient, and can quickly shorten the test time.
In summary, the present application provides a relatively exemplary FLASH bad block detection process, which includes, but is not limited to, the following steps:
step S110, writing a section of data into the read-write control module as a reference source file;
step S111, addressing the FLASH blocks, and selecting one of the FLASH blocks for operation;
step S112, the read-write control module performs addressing of row addresses and column addresses on the selected blocks, selects pages in the blocks to operate, and writes data into the pages;
step S114, performing a data reading operation after performing a writing operation on the corresponding page, and comparing the data with the source file data;
step S115, according to the comparison result, marking the block corresponding to the page with the error, and repeating the steps S111 to S114 until the detection of the pages corresponding to all the blocks in the FLASH is completed;
step S116, storing the detection result into the first block, and establishing a bad block information management table.
It can be understood that the FLASH testing device comprises a display module, the display module comprises a plurality of nixie tubes, and the grading information, the testing current and the standby current are output, including but not limited to the following steps:
step S510, the classification information, the test current, and the standby current are displayed through a plurality of nixie tubes.
It can be understood that the testing device further comprises a high-temperature cabinet, and the FLASH testing method further comprises the following steps:
putting the FLASH testing device into a high-temperature cabinet;
and carrying out current detection and read-write test on the FLASH chip within the preset high-temperature test time.
It can be understood that the preset high-temperature test time may be the sum of a plurality of preset time intervals mentioned in step S100, and the test can be ended only when the test procedure under all the test voltage nodes is completed and the preset high-temperature test time is reached, at this time, the high-temperature cabinet is opened, and the FLASH test device and the FLASH chip are taken out. By setting the high-temperature test scheme, the bad blocks of the FLASH chip which cannot be exposed at normal temperature are exposed in a high-temperature environment, and the accuracy of FLASH test is further improved.
To sum up, the present application combines the FLASH testing apparatus and the FLASH testing method to exemplarily describe the FLASH testing process:
when the off-line aging test is carried out on Flash, firstly, opening a mounting seat in a Flash testing device, putting a Flash chip to be tested into the mounting seat, and closing the mounting seat after the dimension is checked to be correct; then, the read-write control module is burned and written with firmware, the operation of the step is carried out by using a single test board, the USB interface module 4 is connected to a computer, and the firmware with a test algorithm is burned and written through the operation of an upper computer. Meanwhile, the firmware of the CPU is downloaded into the master control module through a burning line, and after the burning of the firmware is finished, the tested Flash and the whole testing device are placed into a high-temperature aging cabinet for aging testing. The power module 1 is connected to a power interface end of the aging cabinet, is connected with a power supply and supplies power to the FLASH testing device. After the testing device is powered on, the program of the master control module is automatically started, the voltage of the IO port of the Flash is adjusted according to the steps set by the program, and the VCC voltage of the Flash is adjusted from 2.7V,3.0V,3.3V and 3.6V step by step respectively. And starting the Flash test every time the Flash test is regulated. If the master control module regulates the PWM wave of the digital potentiometer, the voltage of a voltage reduction circuit electrically connected with the digital potentiometer is set to be 2.7V; after voltage setting is completed, the master control module sends an instruction to the read-write control module in a serial port communication mode, after the read-write control module receives the instruction of the master control module, an internal test algorithm which is burnt in advance is started, a Flash chip is tested, data is written in a storage space inside the Flash through large file block operation and small file system Page operation, data is read, whether the data are consistent or not is compared, and if the data are different, bad block information is marked. Through the scanning of each space, all the bad block information is finally recorded in the read-write module 5, and the controller module 5 internally allocates a section of space to store the bad block information tables. The whole scanning process is carried out in a high-temperature environment, the testing time is long and can last for 4-8 hours, and the whole process is called as an aging test. In the process that the controller module 5 scans the Flash chip for the bad block, the controller module 5 sends an instruction to the master control module 2 to indicate that the master control module 2 can perform current detection. At the moment, the master control module 2 starts current detection on FLASH, commands are sent to two detection chips in the current detection module 7, a communication mode is carried out by adopting an I2C protocol, the current detection chip INA219 receives instructions, current data in the FLASH aging test process are sampled and calculated, the sampled data are sent to the master control module 2, the master control module carries out statistical processing on the data collected in the current detection module 7, finally, an average value is calculated according to program setting, and at the moment, the master control module displays the current value through a nixie tube in the display module 3. The display module 3 stably displays dynamic numbers in the nixie tube in an afterglow mode. In the Flash aging test, the test device flickers through an indicator lamp to indicate that the test is in progress. After the aging test is finished, the controller module 5 performs the BIN display according to the proportion of the bad blocks according to the detection of the internal storage space of the Flash chip. After the aging detection is completed, the controller module 5 obtains a bad block information table and sends the test result to the master control module 2, the master control module 2 controls the display module 3 to display the test result according to the received data and keeps the display state all the time until the material is taken down manually, the next round of power-on test is carried out, and the display state is recovered to the initial condition. After the aging test is completed, the high-temperature cabinet is manually opened, the testing device is taken to a normal-temperature environment, the testing frame in the Flash testing module 8 is opened, the Flash chip is taken out, and the Flash chip is distinguished according to the displayed BIN grade.
In a third aspect, the present application provides a computer-readable storage medium, where the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions, which are executed by one or more processors, may cause the one or more general control modules to execute the FLASH testing method in the foregoing method embodiments.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
From the above description of embodiments, those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable signals, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable signals, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The embodiments of the present application have been described in detail with reference to the drawings, but the present application is not limited to the embodiments, and various changes can be made without departing from the spirit of the present application within the knowledge of those skilled in the art.
Claims (10)
1. A FLASH test apparatus, comprising:
the testing seat is used for installing a FLASH chip;
the voltage adjusting module is electrically connected with the test seat and is used for inputting different test voltages to the FLASH chip;
the current acquisition module is electrically connected with the test seat and is used for acquiring the test current and the standby current of the FLASH chip;
the read-write control module is electrically connected with the test seat and is used for writing storage data into the FLASH chip or reading the storage data out;
the general control module is electrically connected with the voltage regulation module, the current acquisition module and the read-write control module, and the general control module is used for:
controlling the voltage regulating module to input different test voltages to the FLASH chip;
obtaining the test current and the standby current detected by the current detection module under different test voltages;
under different test voltages, generating first bad block information of the FLASH chip according to the write-in storage data of the read-write control module and the comparison value of the storage data;
and according to the first bad block information and the corresponding test current and standby current, the method is used for grading the quality of the FLASH chip.
2. The FLASH testing device of claim 1, further comprising a high temperature cabinet, wherein the FLASH testing device is placed into the high temperature cabinet during testing, and the high temperature cabinet is configured to provide a high temperature testing environment for the FLASH chip.
3. The FLASH testing device according to claim 1, wherein the voltage regulating module comprises a digital potentiometer, a voltage step-down module, the FLASH testing device further comprises a power module, the power module is used for supplying power to the master control module, the master control module is further electrically connected with the digital potentiometer, the output end of the digital potentiometer is electrically connected with the input end of the voltage step-down module, and the output end of the voltage step-down module is electrically connected with the power supply pin of the testing seat.
4. The FLASH testing device according to claim 1, wherein the current collection module comprises two high-precision current sampling chips, and the two current sampling chips are electrically connected with the standby current interface and the test current interface of the FLASH chip through the test socket respectively.
5. The FLASH testing device according to claim 1, further comprising a display module, wherein the display module comprises a plurality of nixie tubes, the plurality of nixie tubes are electrically connected with the master control module, the master control module is further configured to control the nixie tubes to display the test current value and the standby current value, and the master control module is further configured to grade the FLASH chip according to the bad block information of the FLASH chip and display the grading result on the nixie tubes.
6. A FLASH test method, applied to the FLASH test apparatus, the FLASH test apparatus comprising:
the testing seat is used for installing a FLASH chip;
the voltage adjusting module is electrically connected with the test seat and is used for inputting different test voltages to the FLASH chip;
the current acquisition module is electrically connected with the test seat and is used for acquiring the test current and the standby current of the FLASH chip;
the read-write control module is electrically connected with the test seat and is used for writing storage data into the FLASH chip or reading the storage data out;
the FLASH testing method comprises the following steps:
a preset time interval is taken as a test period, and a driving voltage is provided for a power supply interface of the FLASH chip for testing through the voltage regulation module in each test period; the driving voltage is sequentially increased progressively according to the test times;
in each test period, performing data reading and writing on the FLASH chip through the reading and writing control module, and acquiring the standby current and the test current of the FLASH chip through the current acquisition module;
when the master control module judges that the written data is inconsistent with the read data, generating corresponding bad block information through the master control module; the bad block information comprises position information and quantity information of the bad block on the FLASH chip;
grading the FLASH chip according to the bad block information, the standby current and the test current to generate FLASH grading information;
and outputting the FLASH grading information.
7. The FLASH testing method according to claim 6, wherein the reading and writing of data to the FLASH chip by the reading and writing control module includes:
writing a section of data into the read-write control module; the section of data is a source file to be referred to;
and writing and reading a test file into and from each page in each block in sequence according to the arrangement sequence of the blocks in the FLASH chip, wherein the test file is derived from the source file to be referred to.
8. The FLASH test method according to claim 6, wherein when the capacity of the FLASH chip is greater than a preset capacity threshold, the reading and writing the data of the FLASH chip by the read-write control module comprises:
writing a section of data into the read-write control module; the section of data is a source file to be referred to;
and writing and reading test files in each block in sequence according to the arrangement sequence of the blocks in the FLASH chip, wherein the test files are derived from the source file to be referred.
9. The FLASH testing method according to claim 6, wherein when the master control module determines that the written data is inconsistent with the read data, the master control module generates corresponding bad block information, and the FLASH testing method further comprises:
and storing the bad block information in the last test period as final bad block information to be stored in a first block of the FLASH chip.
10. A computer-readable storage medium, characterized in that it stores computer-executable signals for performing the FLASH testing method according to any of claims 6 to 9.
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| CN202211110178.2A CN115424653A (en) | 2022-09-13 | 2022-09-13 | FLASH testing device, FLASH testing method and storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116581043A (en) * | 2023-04-20 | 2023-08-11 | 深圳市晶存科技有限公司 | Chip classification method, device, electronic equipment and computer readable storage medium |
| CN117330942A (en) * | 2023-11-29 | 2024-01-02 | 珠海市芯动力科技有限公司 | Chip debugging method and related device |
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- 2022-09-13 CN CN202211110178.2A patent/CN115424653A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116581043A (en) * | 2023-04-20 | 2023-08-11 | 深圳市晶存科技有限公司 | Chip classification method, device, electronic equipment and computer readable storage medium |
| CN116581043B (en) * | 2023-04-20 | 2023-12-12 | 深圳市晶存科技有限公司 | Chip classification method, device, electronic equipment and computer readable storage medium |
| CN117330942A (en) * | 2023-11-29 | 2024-01-02 | 珠海市芯动力科技有限公司 | Chip debugging method and related device |
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