CN205506896U

CN205506896U - Oscilloscope circuit

Info

Publication number: CN205506896U
Application number: CN201620231223.3U
Authority: CN
Inventors: 公伟; 郝春华
Original assignee: Qingdao Hantek Electronic Co ltd
Current assignee: Qingdao Hantek Electronic Co ltd
Priority date: 2016-03-24
Filing date: 2016-03-24
Publication date: 2016-08-24
Anticipated expiration: 2026-03-24

Abstract

The utility model provides an oscilloscope circuit, includes computer, USB communication module, FPGA module and analog signal processing module, the computer passes through USB communication module and FPGA module connecting in general, the analog signal processing module include relay control circuit, displacement control circuit and ADC circuit, the analog signal processing module constitute by the four ways that parallels. The utility model has the advantages that: high sample rate: the highest real -time sampling speed of single channel is 1GSPS, the bandwidth is up to 250MHz, measure the passageway for four, can provide the signal source of a 25MHz bandwidth, range of sensitivity is big, power dissipation is reduced. Support the mode of two kinds of differences, support the hot plug, reduce the hardware cost owing to optimized partly functional module, realized the product high performance -price ratio.

Description

Oscillograph circuit

Technical field

This utility model relates to a kind of oscillograph circuit.

Background technology

Virtual oscilloscope is possible not only to realize the function of traditional oscillograph, and has storage, reproduces, analyzes, processes ripple The features such as shape, and volume is little, little power consumption.Virtual oscilloscope uses powerful microcomputer to complete the process of signal With the display of waveform, utilize software engineering to design convenience, board true to nature on screen, carry out the place of various signal Manage, process and analyze, represent measurement results by various different modes (such as data, figure, chart etc.), complete various scale Measuring task.It is few to there is port number in existing virtual oscilloscope, uses functional module many, makes product design of hardware and software the most multiple Miscellaneous, use chip cost to cross the problems such as height.

Summary of the invention

This utility model aims to provide a kind of oscillograph circuit, with solve the employing functional module that prior art exists many, Make the problem that product design of hardware and software is complicated, use chip cost is too high.

The technical solution of the utility model is: a kind of oscillograph circuit, including computer, USB communication module, FPGA module With analog signal processing module, computer is connected with FPGA module routine by USB communication module, described analog signal processing Module includes the SPI#1 of control relay circuit, Bit andits control circuit and adc circuit, control relay circuit and FPGA module Interface connects；Bit andits control circuit is connected with the PWM output interface of FPGA module；The data output clock signal of adc circuit, string Row data line and data displacement clock signal are connected with the SPI#2/5 interface of FPGA module respectively, the data of adc circuit and Clock bus is connected with the I/O interface of FPGA module；It is characterized in that, described analog signal processing module is by four tunnels arranged side by side Composition, the control relay circuit on each road is by the Control attenuator circuit being sequentially connected with, Control AC/DC electricity Road, signal amplifier, voltage/current conversion circuit, single-ended transfer difference circuit composition；The outfan of this single-ended transfer difference circuit with Described adc circuit connects；Respectively it is connected with the outfan of a Bit andits control circuit in one end of this signal amplifier each, this position One of PWM output interface of the input of shifter control circuit and described FPGA module is connected.

Described Control attenuator circuit is made up of the two poles of the earth.

74HC595 chip is used between described FPGA module and control relay circuit.

Described Bit andits control circuit is made up of the integrating circuit being sequentially connected with, follow circuit and amplifying circuit, integration electricity One of PWM output interface of the input on road and FPGA module is connected.

This utility model has the following characteristics that

1. high sampling rate: the highest single pass real-time sampling speed is 1GSPS；

2. bandwidth is up to 250MHz；

3. four Measurement channel；

4. it is provided that the signal source of a 25MHz bandwidth；

5. the range of sensitivity is big, from 2mV/div～10V/div；

6. support USB2.0/1.1 communication；

7. spare interface: product can be realized and expand；

8. reserve software upgrading function module: secondary development and the optimization and upgrading of product can be realized；

The most low in energy consumption: to have only to use USB to power and just can normally work；

10. support two kinds of different mode of operations；

11. support hot plug；

12. reduce hardware cost owing to optimizing part of functions module, it is achieved product high performance-price ratio.

Accompanying drawing explanation

Fig. 1 is overall composition circuit block diagram of the present utility model；

Fig. 2 is the circuit block diagram of the analog signal processing module in Fig. 1；

Fig. 3 is the composition block diagram of the control relay circuit in Fig. 1；

Fig. 4 is the composition block diagram providing displacement voltage circuit in Fig. 2.

Detailed description of the invention

See Fig. 1 and Fig. 2, this utility model one oscillograph circuit, including computer (PC) 1, USB communication module 2, FPGA module 3 and analog signal processing module 4, computer 1 is connected with FPGA module 3 routine by USB communication module 2, described Analog signal processing module 4 include control relay circuit 41, Bit andits control circuit 42 and adc circuit 43, Control Circuit 41 is connected with the SPI#1 interface of FPGA module 3；Bit andits control circuit 42 is connected with the PWM output interface of FPGA module 3； The data output clock signal of adc circuit 43, serial data transmission line and data displacement clock signal respectively with FPGA module 3 SPI#2/5 interface connects, and data and the clock bus of adc circuit 43 are connected with the I/O interface of FPGA module 3.This utility model Analog signal processing module 4 therein is improved.

Described analog signal processing module 4 is made up of four tunnels arranged side by side, and the control relay circuit 41 on each road is by depending on The Control attenuator circuit of secondary connection, Control AC/DC circuit, signal amplifier, voltage/current conversion circuit, Single-ended transfer difference circuit forms；The outfan of this single-ended transfer difference circuit is connected with described adc circuit 43；At this signal each One end of amplifier is respectively connected with the outfan of a Bit andits control circuit 42, and the input of this Bit andits control circuit 42 is with described One of PWM output interface of FPGA module 3 connects.

Described Control attenuator circuit is made up of the two poles of the earth, each road analog signal processing module 4 respectively:

The first via: be that relay 1 controls decay 1-1, relay 2 controls decay 1-2, relay 3 successively from input Control AC/DC coupling circuit (i.e. Control AC/DC circuit, lower same), signal amplifier 1, voltage turn electric current 1(voltage/electricity Stream change-over circuit), single-ended transfer difference (circuit) 1, and one of Bit andits control circuit 42 (offer displacement voltage).

Second tunnel: be that relay 4 controls decay 2-1, relay 5 controls decay 2-2, relay 6 successively from input Control AC/DC coupling circuit, signal amplifier 2, voltage turn electric current 2(voltage/current conversion circuit), single-ended transfer difference (circuit) 2, and the two of Bit andits control circuit 42.

3rd tunnel: be that relay 7 controls decay 3-1, relay 8 controls decay 3-2, relay 9 successively from input Control AC/DC coupling circuit, signal amplifier 3, voltage turn electric current 3(voltage/current conversion circuit), single-ended transfer difference (circuit) 3, and the three of Bit andits control circuit 42.

4th tunnel: be that relay 10 controls decay 4-1, relay 11 controls decay 4-2, relay successively from input 12 control AC/DC coupling circuit, signal amplifier 4, voltage turn electric current 4(voltage/current conversion circuit), single-ended transfer difference (electricity Road) 4, and the four of Bit andits control circuit 42.

See Fig. 3, select American TI Company production between described FPGA module 3 and control relay circuit 41 4 74HC595 chip is designed, and the data bit width of its composition is 32Bit.Purpose of design is to utilize 4 HC595 chips by FPGA The 32Bit serial data being sent to is converted into parallel data and exports to control corresponding control relay circuit.This circuit interface Including Control sequential input interface and Control parallel-by-bit output interface.

Seeing Fig. 4, described Bit andits control circuit 42 is by the integrating circuit being sequentially connected with, follow circuit and amplifying circuit group Becoming, one of PWM output interface of the input of integrating circuit and FPGA module 3 is connected.This offer displacement voltage circuit is by FPGA The impulse wave of 4 tunnel common I/O mouth output frequency fixed duty cycle changes is converted into direct current through integrating circuit；The most again through with After circuit and amplifying circuit, it is superimposed upon above the signal that prepass gathers and uses as offset voltage.Described integrating circuit Not only achieve the function of DAC, also there is the function reducing cost.

Adc circuit 43 of the present utility model use (HMCAD1511 chip, by fpga logic control circuit (SPI#2) and His I/O mouth realizes the selection of gear and channel pattern, compares with other these type of functional modules, originally needs a lot of chips to realize Function, current be only achieved that functional requirement with one piece of this type of ADC chip, make hardware designs seem optimization, brief.

This utility model gear and the division of display: the displayable vertical resolution of liquid crystal display screen is 8div, ADC full width input The vertical resolution that voltage is corresponding is designed by 8div, and (i.e. deflection factor 2mV ~ 10V attenuation multiple is 12 kinds of amplitude gears × 1), with 1-2-5 mode stepping.When vertical deflection coefficient is arranged on different gears, the range of voltage values of display on screen For 2mV～80V, thus the input range of measured signal is also 2mV～80V.And analog-digital converter ADC full scale input range It is the least, accordingly, it would be desirable to measured input signal is done suitable decay and processing and amplifying.

Clock about adc circuit: during the difference being provided mid frequency to be 1GHz by ADF4360 and peripheral circuits thereof Clock signal supply ADC does sampling clock and uses.

Signal bandwidth of the present utility model is 250MHz, and the highest single pass real-time sampling speed is 1GSPS, twin-channel The highest real-time sampling speed is 500MSPS, and the highest real-time sampling speed of 4 passages is 250MSPS.Its major function is by amplitude The measured signal varied in size nurse one's health ADC acceptable within the scope of.

Circuit design of the present utility model has the following characteristics that

(1) in order to solve use functional module is many, make product design of hardware and software the most complicated, use chip cost the most high Problem, mainly solves DAC module high cost, the problem of trigger module redundancy.With the offer displacement voltage circuit of Fig. 4, PWM produces displacement voltage and substitutes the function of DAC, and its operation principle PWM and DAC are two kinds of diverse mode of operations.

(2) few in order to solve port number, increase number of channels and keep the use of whole product the lightest, testing scope Bigger wider, artificial circuit part is made that part adjustment, its analog signal processing module 4 is as in figure 2 it is shown, be mainly real Increase and the optimization of control part thereof of gear selectable range, the raising of sampling rate, the simplification of part of module, gear are showed The optimization increasing and controlling part of selectable range.Improving of sampling rate is mainly come in fact by " adc circuit 43 " in Fig. 1 Existing, this is the biggest from the most existing oscillograph different, and it is no longer necessary to extra selection switch.

The typical design parameter of signal condition passage of the present utility model is:

A. this TV station Virtual Digitizing Oscilloscope is 4 passages, digital oscilloscope probe be located at × 10 attenuation multiple time, oscillography Device band a width of BW=250MHz, it may be assumed that a width of DC～250MHz of band of input signal, the amplitude of input signal is 20mV～800V (VDC+VAC) VP-P；When × 1 attenuation multiple, oscillographic bandwidth is restricted to 6.0MHz, it may be assumed that the band of input signal is a width of DC～6.0MHz, the amplitude of input signal is 2mV～80V(VDC+VAC) VP-P.

B. input impedance is 1M Ω ± 2.0% when being 25pF ± 3pF.

C. regulation probe attenuation ratio.In order to coordinate the attenuation multiple of probe, need to adjust accordingly at channel operation menu Probe ratio attenuation quotient.Probe attenuation quotient is × 1, × 10, × 100 and × 1000.

The most oscillographic maximum real-time sampling speed is 1GSPS, i.e. single channel maximum real-time sampling speed is only 250MSPS (signalling channel switching is realized by HMCAD1511)；About the design of this oscillographic signal maximum sampling rate, refer in detail HMCAD1511 parameter declaration.

E., when this oscilloprobe is × 1, the range of sensitivity, from 2mV～10V, with 1-2-5 mode stepping, is divided into 12 Shelves, i.e. 2mV, 5mV, 10mV, 20mV, 50mV, 100mV, 200mV, 500mV, 1.0V, 2.0 V, 5.0V, 10.0V.

F. arrange bandwidth chahnel to limit.There is 20MHz signal bandwidth limit in order to limit bandwidth, in order to reduce Display noise and unnecessary high frequency signal；20MHz signal bandwidth limits: refer to decline the signal amplitude of 20MHz Frequency point Subtract 3DB.

G. probe compensation signal is 1KHz ± 1.0%, 2V ± 1.0%.

H., passage coupling is set.There is exchange (AC), direct current (DC) and the coupling of ground connection input signal, and use between MCU Parallel port interface etc..

AC couples: refer to decay 10Hz signal below and direct current；DC couples: by all of signal, including direct current and The signal that filled band is wide；GND couples: disconnection input signal is in order to test screen has displayed whether DC offset, with inspection Survey whether 0 volt of level shows correctly.

Claims

1. an oscillograph circuit, including computer, USB communication module, FPGA module and analog signal processing module, computer Being connected with FPGA module routine by USB communication module, described analog signal processing module includes control relay circuit, position Shifter control circuit and adc circuit, control relay circuit is connected with the SPI#1 interface of FPGA module；Bit andits control circuit with The PWM output interface of FPGA module connects；The data output clock signal of adc circuit, serial data transmission line and data displacement Clock signal is connected with the SPI#2/5 interface of FPGA module respectively, the data of adc circuit and clock bus and the I/ of FPGA module O Interface connects；It is characterized in that, described analog signal processing module is made up of four tunnels arranged side by side, the relay control on each road Circuit processed is by the Control attenuator circuit being sequentially connected with, Control AC/DC circuit, signal amplifier, voltage/current Change-over circuit, single-ended transfer difference circuit form；The outfan of this single-ended transfer difference circuit is connected with described adc circuit；Often One end of one this signal amplifier is respectively connected with the outfan of a Bit andits control circuit, the input of this Bit andits control circuit and institute One of PWM output interface of the FPGA module stated connects.

Oscillograph circuit the most according to claim 1, it is characterised in that described Control attenuator circuit is by the two poles of the earth Composition.

Oscillograph circuit the most according to claim 1, it is characterised in that described FPGA module and control relay circuit Between use 74HC595 chip.

Oscillograph circuit the most according to claim 1, it is characterised in that described Bit andits control circuit is by being sequentially connected with Integrating circuit, follow circuit and amplifying circuit composition, one of PWM output interface of the input of integrating circuit and FPGA module is even Connect.