CN205656610U - High performance assembly line ADC frequency domain parameter evaluation system based on soPC - Google Patents

Abstract

The utility model relates to a high performance assembly line ADC frequency domain parameter evaluation system based on soPC, include sample collection and handle soPC, wait to evaluate ADC chip daughter board, graphic interface control end, signal source and clock source. Sample collection and processing soPC utilize the microblaze treater to wait to evaluate the ADC daughter board through the configuration of daughter board interface, utilize asynchronous FIFO module buffer memory to come from the sample of waiting to evaluate ADC chip daughter board, save the memory to DDR3 through the DMA controller with the sample. Wait to evaluate ADC chip daughter board received signal source and input sampled signal and clock signal with the signal conduct that the clock source produced. The sample communicates, receives to the graphic interface control end through serial ports and microblaze treater, accomplishes the aassessment of frequency domain parameter in the graphic interface control end. The utility model discloses a modular method has shortened the frequency domain performance aassessment cycle, has advantage with low costs, convenient operation.

Description

A kind of high-performance pipeline ADC frequency domain parameter based on SoPC assessment system

Technical field

This utility model belongs to integrated circuit testing field, relates to a kind of high-performance pipeline ADC frequency domain parameter based on SoPC Assessment system.

Background technology

Along with microelectric technique and the fast development of Digital Signal Processing, analog-digital converter (Analog-to-digital Converter, ADC) as connecting simulated world and the interface of digital display circuit, its effect is more and more obvious.Wherein high-performance pipeline ADC with The application in signal processing fields such as military radar communications of the feature of its high-speed, high precision is the most extensive；As the core component of system, The frequency domain characteristic of ADC the most directly determines systematic function.But, affected by many extraneous factors such as manufacturing process, Gao Xing The actual parameter performance of energy pipeline ADC is extremely difficult to the ideal value of design, therefore for ensureing that the performance of ADC meets requirement, It is necessary it is carried out Performance Evaluation.

At present, offshore company is all based on greatly special automatization's assessment equipment to the Performance Evaluation of high-performance pipeline ADC, such as PXIe measurement series assessment system, the special ADC performance evaluation system of ADI company of NI company, this type of equipment price is high, Operation complexity, often makes the equipment cost of project and human cost too high, and along with the performance of pipeline ADC constantly promotes, its Performance Evaluation needs assessment system possesses higher disposal ability.Single-chip microcomputer and DSP (Digital Signal Processor) etc. compile Journey device can simplify performance parameter evaluation flow process.The most SCM Based assessment system, its clock frequency is relatively low, it is impossible to full High-performance pipeline ADC speed is fast, resolution is high for foot, produce the feature that sample number is big；DSP possess high speed processing ability, Powerful and interface and communication capacity flexibly, but there is also the weakness such as control is not enough simultaneously, waste computing money valuable for DSP Source.FPGA is because of features such as its clock frequency are fast, control flexibly, interface resource is abundant, it is possible to meet system requirements.Therefore, Build with FPGA as carrier, it is achieved high-performance pipeline ADC performance evaluation system based on SoPC has important practice meaning Justice.

Utility model content

The deficiency existed in view of prior art, the purpose of this utility model aims to provide a kind of high-performance streamline based on SoPC ADC frequency domain parameter assessment system, it is possible to achieve the functions such as data acquisition, data reduction of speed, carrying storage, utilizes modular method The ADC making different index can carry out the frequency domain parameter assessment of reality in a common sample collection and process SoPC.

This utility model is achieved through the following technical solutions:

A kind of high-performance pipeline ADC frequency domain parameter assessment system with SoPC as control core, it is characterised in that: include sample This collection and process SoPC, ADC chip daughter board to be assessed, Graphic Interface Control end, signal source and clock source.Described sample Gather and process SoPC comprise Microblaze processor, serial communication modular, asynchronous FIFO module, dma controller, DDR3 memorizer and daughterboard interface.Described sample collection with process SoPC and be connected with described ADC chip daughter board to be assessed and to carry out Logic control, sample collection and process, be connected with described Graphic Interface Control end to communicate and assess with frequency domain parameter.Described treat Assessment ADC chip daughter board includes ADC chip to be assessed, analog input circuit, clock management circuits and motherboard interface, accepts The signal that signal source and clock source produce is as input sample signal and clock signal.Described Graphic Interface Control end, including serial ports Communication module, parameter evaluation module, data memory module, main realization and described sample collection and the two-way of process SoPC Letter and control.Appraisal procedure is: Microblaze processor configures described ADC chip daughter board to be assessed by daughterboard interface to be carried out Sample collection, utilizes asynchronous FIFO module to cache the sample from described ADC chip daughter board to be assessed, by DMA control Sample is stored to DDR3 memorizer by device, sample is delivered to described Graphic Interface Control end subsequently and carries out parameter evaluation.

Accompanying drawing explanation

Fig. 1 is the structural representation of high-performance pipeline ADC frequency domain parameter based on the SoPC assessment system that this utility model provides Figure.

Fig. 2 is the data storage path schematic diagram that this utility model provides.

Fig. 3 is the ADC chip daughter board high-level schematic functional block diagram to be assessed that this utility model provides.

Fig. 4 is the control estimation flow schematic diagram that this utility model provides.

Fig. 5 is the control end assessment interface schematic diagram that this utility model provides.

Detailed description of the invention

Below in conjunction with concrete accompanying drawing and case study on implementation, the utility model is described in further detail.

Embodiment of the present utility model relates to a kind of high-performance pipeline ADC frequency domain parameter based on SoPC assessment system, as Shown in Fig. 1, this platform at least includes: sample collection and process SoPC, ADC chip daughter board to be assessed, Graphic Interface Control End, signal source and clock source.Specifically comprise the following steps that Microblaze processor configures daughter board to be assessed by daughterboard interface and carries out Sample collection, utilizes asynchronous FIFO module to cache the sample from ADC chip daughter board to be assessed, will by dma controller Sample stores to DDR3 memorizer, sample is delivered to Graphic Interface Control end subsequently and carries out parameter evaluation.

Sample collection described in SoPC and process SoPC comprise Microblaze processor, serial communication modular, asynchronous FIFO mould Block, dma controller, DDR3 memorizer and daughterboard interface.Microblaze processor is applied to Xilinx FPGA Embedded Soft Core, as sample collection and the control core of process SoPC, controls sample collection and place by AXI4 EBI Other parts of reason SoPC, specifically include control ADC chip daughter board to be assessed, for communicating with Graphic Interface Control end, Control asynchronous FIFO module, dma controller, DDR3 memorizer carry out sample storage simultaneously.Daughterboard interface is used for extending sample This collection and the I/O of process SoPC, the motherboard with sample collection and process SoPC and ADC chip daughter board to be assessed connects respectively Mouthful connect, by 68 user-defined single-ended signals or 34 user-defined differential pairs, serial transceiver to, clock structure Become, for supporting that ADC chip daughter board to be assessed is to the data transmission of sample collection and process SoPC.Serial communication modular, adopts Realizing with USB-UART interface, wherein USB port is connected with Graphic Interface Control end, UART and described sample collection and place Reason SoPC is connected, for the communication between Graphic Interface Control end and described sample collection and process SoPC and debugging.SoPC Due to clock frequency during ADC chip daughter board sample collection to be assessed and described sample collection and the AXI4 bus of process SoPC Speed cannot be mated, it is therefore desirable to the sample that asynchronous FIFO module caching high-speed time domain state ADC to be assessed chip daughter board produces To meet AXI4 Bus Speed.Dma controller adapter Microblaze processor in sample collection procedure carries out data transmission, For controlling asynchronous FIFO module to the memory channel of DDR memory, so as to allow the Microblaze processor can be from numerous The data carrying of weight frees；DDR3 memorizer, in addition to providing running space for code, is additionally operable to store ADC to be assessed The sample that chip daughter board produces.Sample is from producing to the path stored as shown in Figure 2: the single-ended analog signal that clock source produces enters Enter analog input circuit and generate analog difference signal, subsequently enter ADC chip to be assessed, carry out output numeral after A/D conversion Differential signal, is combined into final required numerical data after certain delay；After asynchronous FIFO module caches, logical Cross dma controller to send in DDR3 memorizer.Every piece of ADC chip daughter board to be assessed has respective DMA channel, deposits When multiple ADC chip to be assessed, only it is required to be each ADC chip to be assessed and adds respective dedicated channel.

The functional module annexation of described ADC chip daughter board to be assessed is as it is shown on figure 3, comprise ADC chip to be assessed, mould Intend input circuit, clock management circuits；Described ADC chip daughter board to be assessed is by motherboard interface and described sample collection and process SoPC is connected, and receives the signal from signal source and clock source as sampled signal and clock signal；Analog input circuit, as The buffer of ADC chip to be assessed, by the signal generator highly purified single-ended analog signal of filtered rear input, defeated through simulation Export differential signal to ADC chip to be assessed after entering the conversion of circuit, amplification and carry out A/D conversion；Clock management circuits, with ADC chip to be assessed is connected with clock source, provides programmable clock signal for ADC chip to be assessed.

Described Graphic Interface Control end uses Labview exploitation, including serial communication modular, evaluation module, data memory module, For with described sample collection and process SoPC communicate, the collection of data, transmission and Performance Evaluation, its control flow is such as Shown in Fig. 4.Serial communication modular initializes, carry out after relevant communication parameter arranges, now Graphic Interface Control end and described sample This collection starts to communicate with processing SoPC, if receiving described sample collection and processing the ready signal of SoPC, it is possible to Graphical interfaces at Graphic Interface Control end carries out operation subsequently；The concrete interface of Graphic Interface Control end is as it is shown in figure 5, program Before startup, need to arrange the relevant setting of data sampling, including conversion accuracy, sample rate, assessment algorithm etc.；After startup program, Wait that described ADC chip daughter board to be assessed initializes successful information, along with the reception time-domain diagram part of sampled data can show phase Should scheme by sine wave, click on performance evaluating and can complete frequency domain characteristic assessment.

Finally illustrating, above example is only in order to illustrate the technical solution of the utility model and unrestricted, although with reference to preferably This utility model has been described in detail by embodiment, it will be understood by those within the art that, can be to this utility model Technical scheme modify or equivalent, without deviating from objective and the scope of technical solutions of the utility model, it all should be contained Cover in the middle of right of the present utility model.

Claims (1)

1. high-performance pipeline ADC frequency domain parameter based on a SoPC assessment system, it is characterised in that: include sample collection and process SoPC, ADC chip daughter board to be assessed, Graphic Interface Control end, signal source and clock source；

Described sample collection and process SoPC comprise Microblaze processor, serial communication modular, asynchronous FIFO module, dma controller, DDR3 memorizer and daughterboard interface；Described sample collection with process SoPC and be connected with described ADC chip daughter board to be assessed and to carry out logic control, sample collection and process, be connected with described Graphic Interface Control end and communicate and frequency domain parameter assessment；

Described ADC chip daughter board to be assessed includes ADC chip to be assessed, analog input circuit, clock management circuits and motherboard interface, accepts the signal source signal with clock source generation as input sample signal and clock signal；

Described Graphic Interface Control end, including serial communication modular, parameter evaluation module, data memory module, the main two-way communication realizing with described sample collection and processing SoPC and control.