CN1337648A - High-speed real-time image record system - Google Patents

Abstract

The present invention incldues: CCD camera, it can transfer the digital image signal to FIFO memory, time unification signal, it provides unified time synchronous signal for system, can be used for controlling output frame frequency of CCD camera, and its output is connected with CCD camera and FIFO memory; FIFO memory; DSP, used for making real-time compression of digital iamge signal delivered from FIFO memoryp; SCSI protocol processor; used for fetching data compressed by DSP, and transferring them onto the SCSI recording equipment, its input is connected with output of DSP; and SCSI recording equipment for storing digital image signal, it is connected with output end of SCSI protocol processor. The invention can be used for recording high-speed real-time image with high resolution, high frame frequency and large data amount image data.

Description

High-speed real-time image record system

The present invention relates to a kind of high-speed real-time image record system.

Along with the develop rapidly of science and technology, people require to improve constantly for visual information, and image processing becomes one of current the most popular technology already, but does not have high-quality apparatus for picking-up image, and image processing has just become water without a source.

U.S. a company has developed and can write down at a high speed, the equipment of high-quality image data, but costs an arm and a leg.Domestic have universities and colleges of a few family and scientific research institutions also developing, but the result is still uncertain.

In view of above-mentioned, the purpose of this invention is to provide a kind of high-speed real-time image record system that is used to write down high resolving power, high frame frequency, big data quantity pictorial data.

Purpose of the present invention is achieved through the following technical solutions:

A kind of high-speed real-time image record system is characterized in that it comprises:

Ccd video camera is used for pickup image, and it sends digital image signal to push-up storage;

Time system signal, it provides the unified time synchronizing signal for system, and the output frame frequency of control ccd video camera, and its output connects ccd video camera and push-up storage;

Push-up storage is used for the digital image signal that the buffer memory ccd video camera is sent, and its input connects ccd video camera;

Digital signal processor, the digital image signal that is used for push-up storage is sent carries out Real Time Compression, and its input connects push-up storage;

The small computer system interface protocol processor is used to read the data after digital signal processor compresses, and they are dumped on the small computer system interface recording unit, and its input connects the output of digital signal processor;

The small computer system interface recording unit is used to store digital image signal, the output of its connection small computer system interface protocol processor.

The digital image signal that the front end ccd video camera is sent here, through the Real Time Compression of digital signal processor, by the small computer system interface protocol processor, the data recording after compressing to high-speed small-size computer system interface equipment.

In addition, in implementing measure of the present invention:

The output of described ccd video camera can connect differential receiver, this differential receiver becomes the Transistor-Transistor Logic level signal with the conversion of signals of ccd video camera output, the output of this differential receiver connects the input of push-up storage through the crossover voltage device, this crossover voltage device is assembled into the data consistent with the input data line width of push-up storage with the data of differential receiver output, and carries out the level conversion of signal.

Also can comprise the CPLD that control signal is provided to described crossover voltage device, push-up storage, digital signal processor respectively.

The output of described digital signal processor can be through the input of buses isolator connection small computer system interface protocol processor, and this buses isolator is isolated both data bus, address bus.

Described small computer system interface protocol processor can connect the program that is used to deposit the small computer system interface protocol processor storer, be used to deposit the memory of data after the digital signal processor compression.

Also can comprise the CPLD that control signal is provided to described small computer system interface protocol processor, program storage, data-carrier store respectively.

The control input/output terminal of described digital signal processor connects the crossover voltage device that carries out level conversion and signal damping.

Advantage of the present invention is:

Owing to use the CCD gamma camera of high resolving power, high frame frequency that high-quality eikongen is provided, measure level so image quality can reach;

Owing to adopted FIFO to cushion this mode, the real-time data acquisition work of front end and the real time data processing work of rear end fully walked abreast, so improved the efficient of system;

Because the state-of-the-art Digital Signal Processing of utilization,, guaranteed visual quality from the angle of data processing so can impose high-speed real-time processing to pictorial data.

Owing to adopted the best external bus-SCSI bus of current performance,, finished data recording at a high speed so can make full use of its high-speed, high-efficiency characteristics.

Engaging drawings and Examples below elaborates to the present invention.

Fig. 1 is the composition diagram of system of the present invention;

Fig. 2 is the circuit diagram of embodiment.

Narrate some nouns of using in the first narrative for making things convenient in the literary composition.

CCD:Charge Coupled Device, charge-coupled image sensor, the most frequently used a kind of Image sensing integrated circuit since the nineties.

FIFO:First In First Out, push-up storage, widely used a kind of technology is used for buffered data in the image processing field, alleviates the contradiction between big data quantity and the processing power.

DSP:Digital Signal Processor, digital signal processor, a kind of high-speed data process chip of widespread use in most advanced and sophisticated scientific research, the engineering.Its application relates to space flight, medical science, commerce, military affairs, communication, industry, scientific research.

SCSI:Small Computer System Interface, small computer system interface, a kind of high-performance intellectualizing system level interface protocol of widespread use.Its unrivaled advantage is: high-speed, and high-level efficiency.

SE, HVD, LVD:Single-Ended, High Voltage Differential, Low Voltage Differential, single-ended, high pressure difference, low-voltage differential.Be several signal transmission forms of SCSI bus, their electric property has nothing in common with each other.What extensively adopt at present is the double mode transmission mode of SE/LVD.

See also Fig. 1.The present invention is a kind of high-speed real-time image record system, and it comprises:

Ccd video camera 1 is used for pickup image, and it sends digital image signal to FIFO storer 3;

Time system signal 2, it provides the unified time synchronizing signal for system, and the output frame frequency of control ccd video camera 1, and its output connects ccd video camera 1 and FIFO storer 3;

FIFO storer 3 is used for the digital image signal that buffer memory ccd video camera 1 is sent, and its input connects ccd video camera 1;

Digital signal processor DSP 4, the digital image signal that is used for FIFO storer 3 is sent carries out Real Time Compression, and its input connects FIFO storer 3;

SCSI protocol processor 5 is used to read the data after DSP4 compresses, and they are dumped on the SCSI recording unit 6, and its input connects the output of DSP4;

SCSI recording unit 6 is used to store digital image signal, and it connects the output of SCSI protocol processor.

The present invention is used to write down high resolving power, high frame frequency, big data quantity pictorial data, the digital image signal that front end ccd video camera 1 is sent here, through the Real Time Compression of DSP4, by SCSI protocol processor 5, the data recording after compressing to high speed scsi device 6.

See also Fig. 2.In an embodiment of the present invention, total system is the center with DSP, can be divided into two parts: 1. data acquisition interface part, shown in the first half of figure; 2. recording unit interface section is shown in the latter half of figure.

At data acquisition interface part: U2 is external trigger equipment, and it provides unified time synchronizing signal VINIT for register system, and this signal can be controlled the output frame frequency of CCD gamma camera U1, and maximum can arrive for 30 frame/seconds.In the RS-422 differential signal of CCD output, comprise 8 bit data signals and 3 control signal FDV, LDV, PDV, differential signal is converted to the Transistor-Transistor Logic level signal of 5V by differential receiver U3 (DS90C32).8 bit data of Transistor-Transistor Logic level are IMG0～IMG7, they are before sending into FIFO, to be assembled into the ID0～ID31 of 32 bit wides to 8 bit data by U4-U6 (LCX16374, LCX16244),, make full use of the capacity of FIFO with consistent with the input data line width of FIFO.FIFO is 3.3V low-voltage, low energy-consumption electronic device, and therefore, U4-U6 must select crossover voltage (LCX series) device, and their input is the 5V Transistor-Transistor Logic level, and output is the 3.3V level, uses for FIFO.

FIFO storer U9, U10 form the degree of depth and spread, and total depth reaches 256K.Its output data end Q0～Q31 is connected to 4 LINK mouths of DSP (U11-A), high transmission speed with 160M/S, by DMA (Direct Memory Access, direct memory access (DMA)) to on-chip SRAM (the Static Random Access Memory of DSP, static RAM), wait the marquis to handle.All hardware controls signals such as WEN_1/, WCLK_1, REN_2/, L_CLK, PCP0～2 are produced by piece of CPLD (Complex Programmable Logic Device, CPLD) U8.U8 selects the EPM7128 of ALTERA company for use.128 macroelements, aboundresources are contained in its inside.Nuclear operating voltage that the more important thing is it is 5V, and the I/O operating voltage is 3.3V, therefore is well suited for 5V, the 3.3V mixed voltage system of native system.

For the benefit of long Distance Transmission, the information data BCD0 that external system is sent here～BCD7 and clock BCDCLK convert differential signal BCD0-～BCD7-, BCD0+～BCD7+, BCDCLK-, BCDCLK+ to by U12.Differential signal converts TTL signal BDS0～BDS7, BDSCLK to by differential receiver U13 (DS90C32).By U7 (LCX16244) Transistor-Transistor Logic level is converted into 3.3V level signal DS0～DS8, DSCLK then, delivers to the LINK mouth of DSP, read and record in the scsi device by DSP and go.

The recording unit interface section: this part mainly comprises the bus interface of DSP (U11-B) and SCSI protocol controller SYM53C770 (U20).

U16 is the crossover voltage device, and its function is the buffering of level conversion and signal.The Transistor-Transistor Logic level signal of DSP is delivered in the outside, will convert the 3.3V level to through U16 earlier, just can deliver to then on the pin of DSP, to avoid the allowing DSP of 3.3V bear high pressure.In addition, the control signal that DSP sends through the buffering of U16, is delivered to external devices earlier then, helps the trouble free service of DSP.

Because U11 is the 3.3V device, and U20 is the 5V device, so 32 bit data bus DAT0～DAT31,32 bit address bus ADDR0～ADDR31 with U11, by buses isolator U14, U15 (LCX16245), carry out electric going up and in logic isolation with data bus D0～D31, the address bus A0～A31 of U20.SRAM3 (U19) is the static memory IDT71016 of IDT company, and it is the program storage of U20, and the degree of depth is 64K, and (a kind of language of the SCSI of being exclusively used in agreement programming is developed by LSI Logic company to be used to store the SCRIPTS program that the U20 processor will carry out.)。After the system power-up, be responsible for program is loaded among the U19, start U20 then and carry out by DSP.SRAM1 (U18) is the IDT71V416 of IDT company, is used for shared storage.DSP is put into the data after compressing here, and U20 reads these data then, and they are dumped to scsi device.All control signals such as CS_SRAM1/, CS_SRAM3/, SCSI_RST/, BOFF/, SRAM3_A0 are produced by piece of CPLD (U17), and its model is with the U8 that uses in the data acquisition interface.

In addition, U20 can form a LVD scsi system by external difference transceiver (the optional 75LVDM976 of model).Simultaneously, use for the convenience of the user, also can add active terminator chip (the optional DS2118 of model).SCSI bus adopts the WIDE scsi cable of 68 cores, and maximum distance can reach 12m.

Wherein:

1) digital interface of ccd video camera is the output of RS-422 difference, and data clock is 40MHz.Be converted into 5V Transistor-Transistor Logic level signal by differential receiver, use for system.

2) the FIFO buffering is used for buffer memory real-time image data, in order to avoid influence the data processing work of DSP.Like this, finish the work of treatment of last time as DSP after, when reaching next data to be processed, these data in FIFO all set.In native system, because data volume is big, single-stage FIFO seems, and capacity is too small, and the fifo chip that we adopt multi-disc American I DT company to produce carries out degree of depth expansion, to satisfy the requirement of system.

3) DSP has powerful processing power, and the master control of system, the Real Time Compression of data are finished by the SHARC DSP-ADSP21160 of the most significant end of ADI company.The following high-performance of ADSP21160 makes it to take on the important task that this high-speed real-time is handled:

A. high performance 32, super Harvard structure DSP includes 4 groups of independent bus lines, to reach instruction, the I/O (Input/Output, I/O) of access and zero consumption in the time of data;

B. two groups of arithmetic elements independently can be carried out SIMD (Single Instruction Multiple Data, single instruction stream multiple data stream) operation, significantly promote the arithmetic capability of DSP;

C. 4Mbit high capacity dual-port SRAM in the sheet can satisfy general application;

D. the I/O processor can provide powerful I/O ability in the sheet, comprises host interface, serial ports, link port, external bus interface, JTAG mouth:

E.4Giga the addressing capability of the chip external memory of word, and support variable latent period, to adapt to the storer of various friction speeds;

F. powerful multiprocessor ability to communicate, extensibility is strong, can form multi-disc DSP array easily, and superpower processing power is provided.

DSP is the core of total system, and it not only will have high arithmetic capability, and, so that can the high speed acquisition data, its I/O ability is also extremely strong, can obtain excellent performance just both mate.Taken all factors into consideration after these 2, we have selected the ADSP-21160 of U.S. Analog Device company for use.Though the TMSC67X series DSP of American TI Company has higher dominant frequency and arithmetic capability, the bottleneck of its I/O bandwidth has limited its combination property greatly.Before system starts working, carry out initialization by DSP, comprising the register initial value is set, clear FIFO is provided with the bus original state, and initialization SCSI protocol controller SYM53C770 starts SYM53C770.Then, DSP monitors the data among the FIFO, when the data among the FIFO reach a certain amount of after, DSP begins reading of data, compaction algorithms is carried out in beginning in real time, again the data storage after the compression to the public highspeed static memory of SCSI protocol controller in, and notice SCSI protocol controller begins data to the scsi device dump.After these steps were finished, DSP read data to be processed next time again in FIFO.As seen, image data acquisition is dumped to scsi device to the good pictorial data of compression to data, the SCSI protocol controller that FIFO buffer memory, DSP read among the FIFO, and this three can overlap a certain period, promptly reached concurrent working, at this moment, overall system efficiency reaches the highest.

4) SCSI protocol processor: the SYM53C770 of U.S. LSI Logic company provides the transmittability of Ultra Wide SCSI, and peak rate is 40MB/S, and differential interface is arranged, and can form SE easily, HVD, LVD scsi system.

SYM53C770 is a kind of application specific processor, is used as the realization of SCSI agreement specially.It can be easily and the 80X86 series of Intel, the 68K series cpu i/f of Motorola.In the native system, we are set as Intel 80386DX interface mode to it, with interface convenient and DSP.In this manner, the data-bus width that it and DSP hold reaches 32, can reach 100MB/S with the memory data exchange rate.This speed can satisfy the needs of native system.In the scsi device interface end, SYM53C770 includes the FIFO of 96 grades of degree of depth, and can support the synchronous SCSI transmission of maximum 16 grades of skews.

The difference transceiver that we add can allow SYM53C770 be operated in differential mode, to form a LVD scsi system.We have also added terminator, make system can be used as an end of SCSI bus, and need not use external terminator again.

5) SCSI recording unit flexibly

Optional Exabyte Mammoth2 magnetic tape station or SCSI hard disk are as recording unit, to adapt to different needs.

The advantage of tape-shaped medium's is that capacity is big, volume is little, portable, price is honest and clean. But the writing speed of magnetic tape station relatively Slowly, be subject to the impact of environment, in the environment in the big field of travel fatigue, be easier to make magnetic head dirty and affect writing task. For This, we also provide with the possibility of hard disk as recording medium, to improve system flexibility. The advantage of hard disk recording Be that speed is fast, little interference by environment, reliability height. Shortcoming is that price is more expensive, needs shockproof when carrying.

Claims (7)

1. high-speed real-time image record system is characterized in that it comprises:

Ccd video camera is used for pickup image, and it sends digital image signal to push-up storage;

Time system signal, it provides the unified time synchronizing signal for system, and the output frame frequency of control ccd video camera, and its output connects ccd video camera and push-up storage;

Push-up storage is used for the digital image signal that the buffer memory ccd video camera is sent, and its input connects ccd video camera;

Digital signal processor, the digital image signal that is used for push-up storage is sent carries out Real Time Compression, and its input connects push-up storage;

The small computer system interface protocol processor is used to read the data after digital signal processor compresses, and they are dumped on the small computer system interface recording unit, and its input connects the output of digital signal processor;

The small computer system interface recording unit is used to store digital image signal, the output of its connection small computer system interface protocol processor.

2. high-speed real-time image record system as claimed in claim 1 is characterized in that:

The output of described ccd video camera connects differential receiver, this differential receiver becomes the Transistor-Transistor Logic level signal with the conversion of signals of ccd video camera output, the output of this differential receiver connects the input of push-up storage through the crossover voltage device, this crossover voltage device is assembled into the data consistent with the input data line width of push-up storage with the data of differential receiver output, and carries out the level conversion of signal.

3. high-speed real-time image record system as claimed in claim 2 is characterized in that: also comprise the CPLD that control signal is provided to described crossover voltage device, push-up storage, digital signal processor respectively.

4. high-speed real-time image record system as claimed in claim 1 is characterized in that:

The output of described digital signal processor is through the input of buses isolator connection small computer system interface protocol processor, and this buses isolator is isolated both data bus, address bus.

5. high-speed real-time image record system as claimed in claim 1 is characterized in that:

Described small computer system interface protocol processor connect the program that is used to deposit the small computer system interface protocol processor storer, be used to deposit the memory of data after the digital signal processor compression.

6. high-speed real-time image record system as claimed in claim 5 is characterized in that:

Also comprise the CPLD that control signal is provided to described small computer system interface protocol processor, program storage, data-carrier store respectively.

7. high-speed real-time image record system as claimed in claim 1 is characterized in that:

The control input/output terminal of described digital signal processor connects the crossover voltage device that carries out level conversion and signal damping.

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