CN109443557B - Single photon pulse arrival time detection device - Google Patents
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Abstract
The invention discloses a single photon pulse arrival time detection device which comprises a signal acquisition circuit, an FPGA processing module and a storage module; utilize single photon detection device and signal amplification circuit with light signal conversion digital pulse signal, gather it by FPGA processing module, adopt the mode of deserializing to reduce data analysis module's operating frequency when gathering single photon pulse signal, adopt the mode of assembly line to the pulse data who gathers to analyze, multistage circuit handles data simultaneously, realize gathering, analysis, storage go on simultaneously, make the required clock cycle of work shorten greatly, reduce the used time of whole flow, improve efficiency greatly.
Description
Technical Field
The invention relates to a single photon pulse arrival time detection device, which is a device applied to the quantum field for single photon information detection.
Background
Photons are the minimum energy quantum of light, and at present, a single photon arrival time detection device with high resolution is widely applied to the quantum field. In quantum experiments, single photons are often required to be counted in a segmented mode so as to reflect the state of an experimental object, and part of effective information is lost in the segmented counting, so that the arrival time of each single photon is required to be measured precisely, the picosecond-level measurement precision is required, and the stability of a system is required to be good; in an experiment, the flight time of particles is measured often, and then the types of the particles are identified by combining information such as flight tracks of the particles, and to improve the measurement precision, single photons need to be collected, and the flight time of the particles is judged according to the arrival time information of the single photons.
Photons can be converted into electronic pulse signals through Avalanche Photodiodes (APDs), and the arrival time of the single photons is detected through the precise measurement of the pulse signals. In the prior art, the single photon pulse arrival time detection device is realized based on an Application Specific Integrated Circuit (ASIC), and although the measurement precision and the stability of the single photon pulse arrival time detection device designed based on the ASIC meet the requirements, the single photon pulse arrival time detection device has the problems of high cost, long development period and small storage space, and meanwhile, the working mode is solidified, and different settings cannot be carried out according to specific requirements.
Disclosure of Invention
The invention aims to avoid the defects in the prior art, and provides the single photon pulse arrival time detection device based on the FPGA so as to ensure the measurement precision and stability, obtain more flexible design, shorten the development period and reduce the cost.
The invention adopts the following technical scheme for realizing the purpose of the invention:
the invention discloses a single photon pulse arrival time detection device, which comprises a signal acquisition circuit, an FPGA processing module and a storage module; the method is characterized in that: the signal acquisition circuit is provided with a single photon detection device and a signal amplification circuit; the single-photon detection device is used for converting the acquired optical signals into electric signals, and the signal amplification circuit is used for converting the electric signals from the single-photon detection device into digital pulse signals after amplifying the electric signals; the FPGA processing module collects digital pulse signals from the signal amplifying circuit to obtain collected pulse signals, and the arrival time data of the pulse signals are stored in the storage module and finally uploaded to the upper computer.
The single photon pulse arrival time detection device of the invention is also characterized in that: the FPGA processing module comprises a serial-to-parallel module which is used for converting the acquired pulse signals into parallel signals, so that the working frequency of subsequent modules is reduced.
The single photon pulse arrival time detection device of the invention is also characterized in that: the FPGA processing module also comprises a data analysis module, wherein the data analysis module is used for carrying out real-time data processing on the parallel data from the serial-to-parallel module to obtain the arrival time of a pulse signal, and the arrival time of the pulse signal refers to the time corresponding to the pulse rising edge, namely pulse rising edge time data; the data analysis module works in the following mode: setting a threshold value for giving the length of the effective pulse signal, and filtering the interference signal, wherein the signal below the threshold value is invalid; regarding the parallel data output by the serial-to-parallel module, recording the parallel data arriving at each clock as a group of data, and taking front and back groups of data as a basis for judging whether the current group of data contains effective pulse rising edges; for this purpose, the first group of data and the second group of data are stored in a cache; when the third group of data arrives, judging the state of the second group of data; the method is a pipeline mode which is formed by at least three clock cycles when a group of data is judged, so that data caching and data state judgment are carried out simultaneously, and only one clock is needed for judging the data state of each group, thereby improving the data processing efficiency.
The single photon pulse arrival time detection device of the invention is also characterized in that: the FPGA processing module also comprises a storage control module, and the storage control module is used for controlling the read-write state of the storage module so as to store the pulse rising edge time data in the storage module and read the pulse rising edge time data and send the pulse rising edge time data to an upper computer.
The single photon pulse arrival time detection device of the invention is also characterized in that: the FPGA processing module also comprises a master control module, a first FIFO buffer, a second FIFO buffer and a data transmission module;
the master control module is used for receiving a control instruction sent by an upper computer so as to control the running state of the detection device; the first FIFO buffer and the second FIFO buffer are used for isolating clock domains of the storage module and the FPGA processing data module so as to optimize the time sequence of the whole device; the data transmission module is used for realizing communication between the upper computer and the FPGA processing module, transmitting data in the storage module to the upper computer, receiving an instruction transmitted by the upper computer and transmitting the instruction to the master control module.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention is realized based on the programmable device FPGA, the measurement precision and the stability are ensured, simultaneously, the design is flexible, the cost of the FPGA is greatly lower than that of an ASIC, and the development period is greatly shortened; with the improvement of the process level of the FPGA device, the performance difference between the FPGA and the ASIC is gradually reduced, and the realization of a high-precision single photon detection circuit on the FPGA has important significance.
2. The invention is designed based on FPGA, adopts digital acquisition mode, and can adjust the threshold value of the effective signal to enhance the flexibility and reliability of data acquisition;
3. in the invention, a serial-parallel conversion and assembly line mode is adopted when the pulse signals are analyzed, so that the acquisition efficiency and the data processing efficiency are greatly improved.
4. The invention has the advantages of high resolution, high integration level, high efficiency and large storage space.
Description of the drawings:
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a block diagram of another embodiment of the present invention;
FIG. 3 is a schematic diagram of a pipeline in the data analysis module according to the present invention.
Detailed Description
Referring to fig. 1, in the present embodiment, a signal acquisition circuit 1 of a single photon pulse arrival time detection apparatus, an FPGA processing module 2, and a storage module 3 are provided.
As shown in fig. 1, the signal acquisition circuit 1 has a single photon detection device 4 and a signal amplification circuit 5; the single-photon detection device 4 is used for converting the acquired optical signals into electric signals, and the signal amplification circuit 5 is used for converting the electric signals from the single-photon detection device 4 into digital pulse signals after amplifying the electric signals; the FPGA processing module 2 acquires digital pulse signals from the signal amplifying circuit 5 to obtain acquired pulse signals, stores arrival time data of the pulse signals in the storage module 3, and finally uploads the data to the upper computer.
In specific implementation, the corresponding setting also includes:
the FPGA processing module 2 comprises a serial-to-parallel module 6, and the serial-to-parallel module 6 is used for converting the acquired pulse signals into parallel signals, so that the working frequency of a subsequent module is reduced, for example, the sampling frequency of the acquired pulse signals is 1GHz, and the acquired pulse signals are converted into 8 paths of 125MHz parallel signals after being converted into a 1-to-8 serial-to-parallel conversion module. The precision of the FPGA-based design is mainly limited by the maximum working frequency of the FPGA, and the precision can be improved in magnitude on the basis of the working frequency by adopting a serial-to-parallel mode, so that the measurement precision reaches the picosecond level.
The FPGA processing module 2 further comprises a data analysis module 7, the data analysis module 7 is used for carrying out real-time data processing on the parallel data from the serial-to-parallel module 6 to obtain the arrival time of the pulse signal, and the arrival time of the pulse signal refers to the time corresponding to the pulse rising edge, namely pulse rising edge time data;
the data analysis module 7 is set to work in the following manner:
setting a threshold value to set the length of the effective pulse signal for filtering the interference signal, wherein the signal below the threshold value is invalid; regarding the parallel data output by the serial-to-parallel module 6, the parallel data arriving at each clock is recorded as a group of data, and in order to judge whether the current group of data contains effective pulse rising edges, two groups of data before and after are needed as bases; to this end, as shown in fig. 3, the first set of data and the second set of data are stored in a buffer; when the third group of data arrives, judging the state of the second group of data; the method is a pipeline mode which is formed by at least three clock cycles when a group of data is judged, so that data caching and data state judgment are carried out simultaneously, and only one clock is needed for judging the data state of each group, thereby improving the data processing efficiency.
The FPGA processing module also comprises a storage control module 9, and the storage control module 9 is used for controlling the read-write state of the storage module 3 so as to store the pulse rising edge time data in the storage module 3 and read the pulse rising edge time data and send the pulse rising edge time data to an upper computer.
The FPGA processing module 2 further comprises a master control module 12, a first FIFO buffer 8, a second FIFO buffer 10 and a data transmission module 11;
the master control module 12 is used for receiving a control instruction sent by the upper computer so as to control the running state of the detection device; the first FIFO buffer 8 and the second FIFO buffer 10 are used for isolating clock domains of the storage module and the FPGA processing data module so as to optimize the time sequence of the whole device, and the FIFO buffers also have the function of adjusting the bit width of data transmission in the FPGA; the data transmission module 11 realizes communication between the upper computer and the FPGA processing module 2, is used for sending data in the storage module 3 to the upper computer, receiving instructions sent by the upper computer and transmitting the instructions to the master control module 12, and adopts a USB interface for communication between the FPGA and the upper computer.
The storage module 3 is an external storage chip of the FPGA device, the storage resources of the FPGA are less, and the storage space of the device is greatly increased by using the storage module 3.
Fig. 2 shows another embodiment of the present invention, which further includes a data processing module 13 in the FPGA processing module, where the data processing module 13 is located before the data transmission module and is used to count the collected photon arrival time data in different time periods, for example, count that several single photons arrive within every 1 microsecond, and the time period length can be set.
Claims (3)
1. A single photon pulse arrival time detection device comprises a signal acquisition circuit (1), an FPGA processing module (2) and a storage module (3); the method is characterized in that: the signal acquisition circuit (1) is provided with a single photon detection device (4) and a signal amplification circuit (5); the single-photon detection device (4) is used for converting the acquired optical signals into electric signals, and the signal amplification circuit (5) is used for converting the electric signals from the single-photon detection device (4) into digital pulse signals after amplifying the electric signals; the FPGA processing module (2) collects digital pulse signals from the signal amplification circuit (5) to obtain collected pulse signals, stores arrival time data of the pulse signals in the storage module (3), and finally uploads the data to an upper computer;
the FPGA processing module (2) comprises a serial-to-parallel module (6), and the serial-to-parallel module (6) is used for converting the acquired pulse signals into parallel signals so as to reduce the working frequency of subsequent modules; the FPGA processing module (2) further comprises a data analysis module (7), wherein the data analysis module (7) is used for carrying out real-time data processing on parallel data from the serial-to-parallel module (6) to obtain the arrival time of a pulse signal, and the arrival time of the pulse signal refers to the time corresponding to the pulse rising edge, namely pulse rising edge time data; the data analysis module (7) works in the following way: setting a threshold value for giving the length of the effective pulse signal, and filtering the interference signal, wherein the signal below the threshold value is invalid; regarding the parallel data output by the serial-to-parallel module (6), recording the parallel data arriving at each clock as a group of data, and taking front and back groups of data as a basis for judging whether the current group of data contains effective pulse rising edges; for this purpose, the first group of data and the second group of data are stored in a cache; when the third group of data arrives, judging the state of the second group of data; the method is a pipeline mode which is formed by at least three clock cycles when a group of data is judged, so that data caching and data state judgment are carried out simultaneously, and only one clock is needed for judging the data state of each group, thereby improving the data processing efficiency.
2. The single photon pulse arrival time detecting apparatus of claim 1 which is characterized by: the FPGA processing module also comprises a storage control module (9), wherein the storage control module (9) is used for controlling the read-write state of the storage module (3) so as to store the pulse rising edge time data in the storage module (3) and read the pulse rising edge time data and send the pulse rising edge time data to an upper computer.
3. The single photon pulse arrival time detecting apparatus of claim 1 which is characterized by: the FPGA processing module (2) further comprises a master control module (12), a first FIFO buffer (8), a second FIFO buffer (10) and a data transmission module (11); the master control module (12) is used for receiving a control instruction sent by an upper computer so as to control the running state of the detection device; the first FIFO buffer (8) and the second FIFO buffer (10) are used for isolating the clock domains of the storage module and the FPGA processing data module so as to optimize the time sequence of the whole device; the data transmission module (11) is used for realizing communication between the upper computer and the FPGA processing module (2), sending data in the storage module (3) to the upper computer, receiving an instruction sent by the upper computer and transmitting the instruction to the master control module (12).
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