CN203466819U

CN203466819U - FPGA-based simple coincidence system

Info

Publication number: CN203466819U
Application number: CN201320583214.7U
Authority: CN
Inventors: 刘嫔; 邓月明; 王佳和
Original assignee: Central South University
Current assignee: Central South University
Priority date: 2013-09-22
Filing date: 2013-09-22
Publication date: 2014-03-05
Anticipated expiration: 2023-09-22

Abstract

Disclosed in the utility model is an FPGA-based simple coincidence system comprising a high-speed level switching module, an FPGA multi-path signal counting module, a communication interface control module, a clock module and a configuration module. The high-speed level switching module, the FPGA multi-path signal counting module, and the communication interface control module are successively in communication connection. The input terminal of the high-speed level switching module is connected with an external single photon counting detecting instrument; the output terminal of the communication interface control module is connected with an external PC machine; the configuration module is in communication connection with the FPGA multi-path signal counting module; and the clock module is in communication connection with the FPGA multi-path signal counting module and provides a clock signal. The provided FPGA-based simple coincidence system has the following technical effects: defects in flexibility, universality, and configurability and the like of the exiting coincidence system in the high-speed photo communication signal measurement field can be overcome; the life cycle of the kind of system can be prolonged; and the concrete application range is extended.

Description

A kind of simple and easy system that meets based on FPGA

Technical field

The utility model relates to high speed optical communication measuring equipment, particularly a kind of simple and easy system that meets based on FPGA.

Background technology

In high speed optical communication signal measurement field, normally according to its light particle properties, adopt this class opto-electronic conversion electronic system of single photon counting survey meter, then provide the signal of telecommunication to carry out statistical analysis to follow-up electronic metering equipment.Wherein, meeting system is a kind of important statistical analysis device in high speed optical communication, and it can get up to form two parameters or Multivariate analysis system pulse amplitude analysis and time series analysis system connection.Many occur simultaneously or occur in short time interval and have in the dependent event of causal relation, be called and meet event, the electronic system that measurement meets event is called and meets system.

At present the common system that meets, adopts ASIC-based, and life cycle is short, eliminates soon, can not meet the fast-developing requirement of high speed optical communication technology.

Utility model content

In order to solve, to meet at present systems life cycle short, eliminates fast technical problem, and the utility model provides a kind of simple and easy system that meets based on FPGA.

The technical solution of the utility model is that a kind of simple and easy system that meets based on FPGA, comprises high-speed level modular converter, FPGA multiple signals counting module, communications interface control module, clock module and configuration module.Described high-speed level modular converter, FPGA multiple signals counting module and communications interface control module communicate to connect successively, the input of high-speed level modular converter connects outside single photon counting survey meter, the output of communications interface control module connects outer PC, described configuration module communication connection FPGA multiple signals counting module, described clock module communication connection FPGA multiple signals counting module also provides clock signal.

Described a kind of simple and easy system that meets based on FPGA, multiple signals counting module is high speed fpga chip.

Technique effect of the present utility model is, solves the existing system that meets of field of high-speed optical communications in the deficiency of the aspects such as flexibility, versatility, configurability, improves the life cycle of this type systematic, widens concrete range of application.

Accompanying drawing explanation

Fig. 1 is structural representation of the present utility model;

Fig. 2 is the utility model FPGA structural representation.

Embodiment

Referring to Fig. 1, the clock module described in the present embodiment, adopts DS1023 chip to realize, and the clock signal of PLL starting of oscillation is provided for fpga chip on the one hand, is also mainly used on the other hand produce meet acquisition window simultaneously, and this window can be adjusted by FPGA.DS1023 You Liangzhong working mechanism (serial and parallel) is used for loading and postpones to arrange, and these two kinds of mechanism are controlled the level of its P/S pin by FPGA, adopt serial mode setting to meet acquisition window in the utility model.

Communications interface control module described in the present embodiment is FT245, is the integrated circuit of a kind of USB/FIFO, can realize USB to the conversion of eight parallel-by-bit interfaces, and supports synchronous, asynchronous interface pattern, can realize well the communication between PC and FPGA.

High-speed level modular converter described in the present embodiment, conversion speed is more than 100Mbps, adopts ADI company to realize with the four-way chip ADG3257 of ESD protection, be used to provide four-way+5V is converted to 3.3V transfer of data.

Configuration module described in the present embodiment, connects FPGA multiple signals counting module, is used to provide related command byte and data the coincidence counting of FPGA is carried out to initial configuration work.

Referring to Fig. 2, FPGA multiple signals counting module described in the present embodiment, it is the whole pith that meets system, the statistical counting of realization within meeting window, it comprises the parts such as data acquisition and synchronization module, clock interface module, communication interface modules, High Speed Serial module, two-port RAM.

Data acquisition described in the present embodiment and the working method of synchronization module are, when clock module DS1023 has loaded after new parameter, FPGA will monitor the collection request from PC end from communications interface control module FT245, and then determines whether to start to meet collection.Once you begin meet collection, FPGA will monitor the multiplexer channel signal from high-speed level modular converter, while having pulse to occur in multiplex (MUX), FPGA will latch multiple signals state now in two-port RAM, FPGA will correspondingly start two counters simultaneously, one is 60ns timer, and another is 100ms timer.60ns timer is used for removing and latchs, and 100ms timer is used for suspending meeting and gathers and the inner universal asynchronous receiving-transmitting circuit of initialization.When meeting window timer and overflow, FPGA carries out ' or ' computing to the signal latching, and carrys out this signal of buffer memory by a d type flip flop.Meanwhile, once a certain road signal that has in latching changes, FPGA will produce the pulse of a 10ns.FPGA has adopted the d type flip flop of two 100MHz to be used for synchrodata output, adopts 3 d type flip flops to carry out the pulse of buffer memory 10ns.The signal of buffer memory is as the address of two-port RAM, the pulse signal of 10ns will be used as the read-write enable signal of RAM, when the address of two-port RAM changes and when RAM enable signal is state of activation, data in this this address will be as 32 from the input that adds device, another input is constant 1, from the Output rusults that adds device, deposit in again in two-port RAM, with this, reach and meet to various the object that situation is carried out statistical counting.

DS1023 in 4 serial modes connection clock modules of clock interface module employing described in the present embodiment arrange and meet acquisition window, DS1023 adopts level connected in series, the SDO pin of first DS1023 is connected with second DS1023, by that analogy, finally the SDO pin of the 4th is suspended.

Synchronous, asynchronous interface pattern that communication interface modules described in the present embodiment is supported, itself and communications interface control module FT245 collaborative work, can realize the communication between PC and FPGA well.

High Speed Serial module described in the present embodiment is also the important module meeting in system, is used for reading outside high speed signal, and it supports 9600 bauds and two kinds of Transmission bit rates of 15200 bauds, and these two kinds of baud rates are all provided by baud rate generator.If met, gather timer over 100ms, FPGA is by the inner universal asynchronous receiving-transmitting circuit of initialization, and first 8 bit data is sent to two-port RAM, then initialization second period transmits second data to two-port RAM, until the data of 16 counters are all sent out.

Above-described embodiment is Application Example of the present utility model, all within the scope of principle of the present utility model, the modification of making, is equal to replacement etc., within all should being included in protection range of the present utility model.

Claims

1. the simple and easy system that meets based on FPGA, it is characterized in that, comprise high-speed level modular converter, FPGA multiple signals counting module, communications interface control module, clock module and configuration module, described high-speed level modular converter, FPGA multiple signals counting module and communications interface control module communicate to connect successively, the input of high-speed level modular converter connects outside single photon counting survey meter, the output of communications interface control module connects outer PC, described configuration module communication connection FPGA multiple signals counting module, described clock module communication connection FPGA multiple signals counting module also provides clock signal.

2. a kind of simple and easy system that meets based on FPGA according to claim 1, is characterized in that, described FPGA multiple signals counting module is high speed fpga chip.