CN204129729U - Flash memory control system based on DMA transmission - Google Patents

Flash memory control system based on DMA transmission Download PDF

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Publication number
CN204129729U
CN204129729U CN 201420295531 CN201420295531U CN204129729U CN 204129729 U CN204129729 U CN 204129729U CN 201420295531 CN201420295531 CN 201420295531 CN 201420295531 U CN201420295531 U CN 201420295531U CN 204129729 U CN204129729 U CN 204129729U
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flash
flash memory
data
control system
array
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CN 201420295531
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Chinese (zh)
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陈伟
张琳
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苏州润林文化传媒有限公司
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Abstract

The utility model discloses a Flash memory control system based on DMA transmission. The Flash memory control system comprises an FPGA control component, a Flash memory array and a USB interface. The FPGA control component controls the Flash memory array and correctly stores data, and the data stored in the array are uploaded to an upper computer through the USB interface. A DMA controller is adopted for transmitting a command and an address, flow-line memory is achieved, and memory speed is increased. With an FPGA as a control platform, the system has the advantages of being high in real-time performance and speed. According to the design, read-write wait when an embedded processor operates a FLASH array is omitted, the read-write process is simplified, and the overall operation efficiency of the system is improved.

Description

—种基于DMA传输的Flash存储控制系统 - Flash memory types DMA transfer control system based on

技术领域 FIELD

[0001] 本实用新型涉及计算机技术领域,特别涉及一种基于DMA传输的Flash存储控制系统。 [0001] The present invention relates to computer technology, and more particularly relates to a control system based on Flash memory DMA transfer.

背景技术 Background technique

[0002] NAND FLASH由于其存储容量大、体积小、读写速度快、外围电路简单,从而在嵌入式系统中得到了越来越广泛的应用。 [0002] NAND FLASH memory because of its large capacity, small size, read and write speed, a peripheral circuit is simple to obtain a more widely used in embedded systems. 但NAND FLASH的读写操作比较特殊,在读写数据时要先写入操作命令和读写地址,并且在编程时不能对其执行任何操作。 NAND FLASH read and write operations but special, first write operation command and the read address when the read and write data, and programming is not performing any operation. 通常嵌入式处理器采用查询的方式对NAND FLASH进行编程,不仅操作复杂,而且减慢了数据读写的速度。 Usually embedded processor by way of inquiry of NAND FLASH programming, operation not only complicated, but also slows down the data read and write speeds.

[0003] DMA传输,即存储器直接访问,是一种高速的数据传输操作,允许外部设备和存储器之间直接读写数据,不需要CPU干预,达到数据的快速存储。 [0003] DMA transfer, i.e., direct memory access, data transfer is a high-speed operation, allowing direct reading and writing of data between external devices and a memory without CPU intervention, to achieve fast data storage.

实用新型内容 SUMMARY

[0004] 本实用新型目的是:提供一种基于DMA传输的Flash存储控制系统,采用DMA传输实现了对命令和地址的传输,并实现流水线存储过程,加快了存储速度,提高了系统整体运行效率。 [0004] The object of the present invention are: to provide a Flash storage control system based on DMA transfer, using DMA transfer command and to implement the transmission of address and stored streamline process, accelerated storage speed, improve the overall efficiency of the system .

[0005] 本实用新型的技术方案是:一种基于DMA传输的Flash存储控制系统,包括FPGA控制器件、Flash存储阵列和USB接口,所述的FPGA控制器件对Flash存储阵列的控制和数据的正确存储,将阵列中存储的数据通过USB接口上传到上位机。 [0005] The technical solution of the present invention is: A Flash memory DMA transfer based control system, including control means proper FPGA, Flash memory array and a USB interface, the control means of the FPGA control and data storage array of Flash storing the data stored in the array interface to upload to the host computer via USB.

[0006] 进一步的,所述Flash存储阵列中所有FLASH使用相同的控制信号,同一列的FLASH的片选信号相同,但数据通道不同,同一行的FLASH的片选信号不同,而数据通道相同。 [0006] Further, the Flash memory array FLASH same control signal to all using the same column the same FLASH chip select signal, but with different data channels, the different chip select signal FLASH same row, and the same data channel.

[0007] 进一步的,所述的FPGA控制器件通过DMA控制器传输命令和地址按时序释放到数据总线上,对数据进行存储。 [0007] Further, the control means is released by the FPGA DMA controller transfers the command and address on the data bus in a time series, data storage.

[0008] 进一步的,所述的Flash存储阵列采用时分多路复用的方法对数据进行存储。 [0008] Further, the Flash memory array using the method of time division multiplex data storage.

[0009] 进一步的,对FLASH进行存储操作时应先向FLASH写入编程开始命令,然后是五个周期的有效块存储地址和2K字节数据,最后写入结束编程命令。 [0009] Further, when the FLASH memory for the write operation Xianxiang FLASH programming start command, then the valid blocks and a 2K byte data memory address five cycles, the last write command program ends.

[0010] 进一步的,所述的数据存储采用全相关的无效块管理方法。 [0010] Further, the data storage management method using the ineffective block is full correlation.

[0011] 进一步的,所述的全相关的无效块管理方法为首先将无效块的信息缓存于地址FIFO,待数据存储时,由DMA读取,将相同的地址和命令并置在一起,然后通过DMA方式发送到数据总线,最后在每个Flash的I/O 口进行分配。 [0011] Further, the full correlation invalid block management method according to first cache block is invalid information in the FIFO address, when the data to be stored, is read by the DMA, the address and command the same juxtaposition, and transmitted to the data bus through the DMA, the last of the Flash partitioned each I / O port.

[0012] 进一步的,所述的命令和地址通过八选一选择器发送到Flash的1总线上。 [0012] Further, the command and address through the eight selected from a selector 1 is sent to the Flash bus.

[0013] 本实用新型的优点是: [0013] The advantages of the present invention are:

[0014] 采用DMA控制器对命令和地址进行传输,并实现流水线存储过程,加快了存储速度。 [0014] The DMA controller of the command and address are transmitted, and stored streamline the process, to accelerate the storage speed. 并且系统以FPGA为控制平台,具有实时性高,速度快的优点。 FPGA system and the control platform, having high real time, the speed advantage. 此设计免去了嵌入式处理器对FLASH阵列操作时的读写等待,简化读写流程,提高了系统整体运行效率。 This design eliminates the embedded processor array FLASH read and write operation when waiting, reading and writing to simplify processes and improve the overall efficiency of the system.

附图说明 BRIEF DESCRIPTION

[0015] 下面结合附图及实施例对本实用新型作进一步描述: [0015] accompanying drawings and the following examples further describe embodiments of the present invention as:

[0016] 图1是本实用新型一种基于DMA传输的Flash存储控制系统的结构框图; [0016] FIG. 1 is a block diagram showing a configuration of the present invention is based on Flash storage control system of the DMA transfer;

[0017] 图2是本实用新型一种基于DMA传输的Flash存储控制系统的DMA传输命令和地址的结构框图。 [0017] FIG. 2 is a block diagram showing a configuration of the present invention based on DMA transfer commands and addresses Flash memory control system of the DMA transfer.

具体实施方式 detailed description

[0018] 为使本实用新型的目的、技术方案和优点更加清楚明了,下面结合具体实施方式并参照附图,对本实用新型进一步详细说明。 [0018] The object of the present invention, the technical solution and merits thereof more apparent in the following with reference to the drawings and specific embodiments, further detailed description of the new type of utility. 应该理解,这些描述只是示例性的,而并非要限制本实用新型的范围。 It should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. 此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本实用新型的概念。 In the following description, description is omitted for well-known structures and techniques, in order to avoid unnecessarily obscuring the present novel concept and practical.

[0019] 实施例: [0019] Example:

[0020] 该系统包括FPGA控制器件、Flash存储阵列和USB接口,所述的FPGA控制器件对Flash存储阵列的控制和数据的正确存储,将阵列中存储的数据通过USB接口上传到上位机。 [0020] The control system comprises a FPGA device, and the USB interface Flash memory array, FPGA control device according to proper control and data storage Flash memory array, the data array storing uploaded to the host computer interface via USB.

[0021] FPGA: [0021] FPGA:

[0022] 存储控制系统的控制器件,集成度高,功耗低,内部嵌有总线结构灵活,并行处理能力强的软处理器核MICR0BLAZE,并有用户自定义的IP核,可以实现对FLASH阵列的控制和数据的正确存储,而且可以将阵列中存储的数据通过USB接口上传到上位机,进行数据的后期处理。 Control means [0022] The storage control system, high integration, low power consumption, the internal bus structure embedded flexible, strong flexible parallel processing processor core MICR0BLAZE, and have a user-defined IP core, the array can be achieved FLASH proper control and data storage, and may be stored in the data array uploaded to the host computer through the USB interface, the data post-processing. 为了保证Flash的正确操作,必须在操作之前建立无效块信息表。 In order to ensure correct operation of Flash, invalid block information table must be established before the operation. 在对Flash进行读、写或擦除操作之前,应先从FPGA的RAM中读取无效块信息,然后根据无效块信息决定是否对当前块操作。 Before Flash read, write or erase operation, the FPGA RAM should start reading invalid block information, and whether the current block according to the operation information determining the invalid block. 待数据存储时,由DMA读取,然后将相同的地址和命令并置在一起,然后通过DMA方式发送到数据总线,最后在每个Flash的I/O 口进行分配。 When data is to be stored, it is read by the DMA, and the same address and command juxtaposed together, and then transmitted to the data bus through the DMA, the last of the Flash partitioned each I / O port.

[0023] 存储阵列: [0023] The memory array:

[0024] 系统采用4X4 NAND FLASH阵列形式,由SAMSUNG公司的K9NBG08U5A搭建而成,每颗NAND FLASH容量为4G X 8bit,因而整个NAND FLASH容量为64G。 [0024] NAND FLASH 4X4 system uses an array, the structures formed by SAMSUNG's K9NBG08U5A, every single NAND FLASH capacity 4G X 8bit, NAND FLASH and thus the whole capacity of 64G. 在构建FLASH阵列时,所有FLASH使用相同的控制信号,同一列的FLASH的片选信号相同,但数据通道不同,同一行的FLASH的片选信号不同,而数据通道相同。 When building an array of FLASH, FLASH all use the same control signal, the same FLASH chip select signal in the same column, but with different data channels, the different chip select signal FLASH same row, and the same data channel.

[0025] USB 接口: [0025] USB Interface:

[0026] 上位机和存储系统的数据交互通过USB接口进行,上位机将命令和配置信息通过USB接口传入FPGA,使FPGA内部的MICR0BLAZE执行相应的操作。 [0026] The data exchange and storage system host computer via the USB port, the host computer commands and configuration information passed through the USB interface FPGA, so MICR0BLAZE inside the FPGA performs the corresponding operation. 数据回读时通过USB接口将数据传回上位机。 Through the USB interface data back to the host computer when data is read back. 上位机可以是Pc或者是一个嵌入式系统。 PC Pc can be either an embedded system.

[0027] FPGA通过DMA控制器传输命令和地址,DMA方式写命令和地址是用硬件的方法将FLASH阵列编程需要的命令和地址按时序释放到数据总线上,免去了上位机查询时所浪费的时间;流水线操作流程是DMA对FLASH阵列编程阶段等待的时间的利用,提高了存储效率。 [0027] FPGA write command and address through the DMA controller transfers the command and address, the DMA mode is the command and address required for programming an array of FLASH hardware release chronological manner to the data bus, replacing the wasted query the host computer time; pipelining process is the use of the DMA programming phase array FLASH waiting time and improve the storage efficiency.

[0028] 对有效数据的存储操作包括加载阶段和编程阶段,编程阶段期间,FPGA不能对FLASH进行操作,因此对于单片FLASH存储器而言,编程阶段的时间被浪费,不利于达到快速存储。 [0028] The valid data storing operation and programming phase comprises loading phase, during the programming phase, FPGA FLASH can not operate, so for monolithic FLASH memory, the programming stage is a waste of time, is not conducive to achieve fast storage. 为此可采用时分多路复用的方法对数据进行存储,具体实现方式就是首先对第一列的NAND FLASH加载数据,数据加载完后,第一列NAND FLASH随后就将进入自动编程状态,立即再加载第二列NAND FLASH。 The method may be employed for this division multiplexed data storage, a particular implementation of the first NAND FLASH is the first column of data loading, data is finished loading, then the first column of NAND FLASH automatic programming will enter a state immediately and then load the second column of NAND FLASH. 如此循环进行数据加载,直到最后一片加载完成后,再回到第一片。 So the cycle for data loading, after loading is complete until the last one, and then back to the first piece. 这样就充分利用了编程阶段的时间,使存储速度得到提升,此过程也称流水线操作。 This will take advantage of the time programming phase, the memory speed has been improved, this process is also known as pipelining.

[0029] DMA方式写命令和地址: [0029] DMA mode write command and address:

[0030] FLASH片内包含一个页的数据寄存器,编程过程中始终是将存储数据先缓存到数据寄存器,然后再写入存储单元,所以它是基于页的读写,基于块的擦除。 Comprising the [0030] FLASH sheet of one page of data registers, the programming process is always the first cache data store to the data register, and then write the memory cell, so it is based on the page read, erase block basis.

[0031] 对FLASH进行存储操作时应先向FLASH写入编程开始命令,表示写数据的开始;因为在写入地址时列地址需要12根地址线,页地址需要17根地址线,而每次只能向8根线写数据,这样就需要5个时钟周期来写入地址,前两个时钟写入列地址,后三个时钟写入行地址。 [0031] should be of the FLASH memory write operation Xianxiang FLASH programming start command, indicating the start of data writing; because when the column address needs to write address lines 12 address, page address requires 17 address lines, and each 8 can only be written to the data lines, which will require five clock cycles to the write address, write column address before two clocks, three clocks after the write row address. 然后是2K字节数据,最后写入结束编程命令。 Then the 2K-byte data, the last written program end command.

[0032] 用DMA方式传送命令和地址花费的时间低于上位机查询的方式,提高了存储速度。 [0032] The transfer of command and address time spent using DMA mode is less than the PC mode query, improved storage speed. 由于系统FLASH阵列规模小,可以选用全相关的无效块管理方法,其控制简单、算法容易实现。 Since the system is an array of FLASH small, can use full correlation invalid block management method, control is simple, easy to implement algorithm. 无效块的信息事先缓存于地址FIFO,待数据存储时,由DMA读取。 Invalid block information address in the FIFO buffer in advance, when the data to be stored, is read by the DMA. 此外每片NANDFLASH的编程命令码相同,所以对每一列FLASH操作时,每个FLASH 1 口上的数据是相同的。 Further programming each piece NANDFLASH same command code, so when each column FLASH operation, data on each of a FLASH is the same. DMA方式写命令和地址如图2所示,相同的地址和命令先并置在一起,然后通过DMA方式发送到数据总线,最后在每个FLASH的I/O 口进行分配。 DMA mode write command and the address shown in Figure 2, the same address and command to concatenated together, and then transmitted to the data bus through the DMA, the last partitioned FLASH each of I / O port.

[0033] 无效块,即为坏块,由于NAND Flash的工艺不能保证NAND的Memory Array在其生命周期中保持性能的可靠,因此,在NAND的生产中及使用过程中会产生坏块。 [0033] invalid blocks, that is, bad blocks, since the NAND Flash technology can not guarantee to maintain the NAND Memory Array reliable in its life cycle, and therefore, the production and use of NAND process will produce bad blocks.

[0034] 坏块信息存储于flash每一页的spare area区,因此,如果在擦除一个块之前,一定要先check —下spare area区的第6个byte是否是Oxff,如果是Oxff就证明这是一个好块,可以擦除;如果是非OxfT,那么就不能擦除,即不能读写。 [0034] The bad block information is stored in the spare area each flash page region, therefore, if prior to erasing a block, must first check - 6th byte spare area if the area is Oxff, Oxff to prove if it is this is a good block can be erased; if non OxfT, then it can not be erased, i.e. not read or write.

[0035] 图2中的八选一选择器电路的作用是按FLASH的操作时序将包括存储数据、命令、地址放到FLASH的1总线上,通道的选择由DMA控制。 In [0035] FIG. 2 is selected from an eight selector circuit according to the role the operation timing of FLASH memory include data, commands, addresses on bus 1 FLASH, the selected channel by the DMA control. 与此同时,相应的控制信号ALE、CLE、WE等变为有效电平,实现命令、数据、地址的写入。 At the same time, a corresponding control signal ALE, CLE, WE to active level, etc., to achieve a write command, data, address.

[0036] 应当理解的是,本实用新型的上述具体实施方式仅仅用于示例性说明或解释本实用新型的原理,而不构成对本实用新型的限制。 [0036] It should be appreciated that the present invention specific embodiments described above merely for illustrative or explain the principles of the present invention, without limiting practical configuration of the present new pair. 因此,在不偏离本实用新型的精神和范围的情况下所做的任何修改、等同替换、改进等,均应包含在本实用新型的保护范围之内。 Therefore, any modifications without departing from the spirit and scope of the invention made of, equivalent substitutions and improvements should be included within the scope of protection of the present invention. 此外,本实用新型所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。 Further, the present invention fall within the appended claims are intended to cover the scope of this embodiment, and all changes and modifications within the boundary of equivalents of the appended claims and the range boundaries, or request.

Claims (4)

  1. 1.一种基于DMA传输的Flash存储控制系统,其特征在于,包括FPGA控制器件、Flash存储阵列和USB接口,所述的FPGA控制器件对Flash存储阵列进行控制和数据的存储,将阵列中存储的数据通过USB接口上传到上位机,所述Flash存储阵列的数据存储由FPGA控制器件通过DMA控制器传输命令和地址按时序释放到数据总线上对数据进行存储。 A Flash memory DMA transfer based control system, characterized in that the control means comprises a FPGA, Flash memory array and a USB interface, the FPGA control means for controlling storage of data and the Flash memory array, the memory array upload the data interface to the host computer via USB, the data stored in Flash memory array controlled by the FPGA devices chronological released onto the data bus for data storage by the DMA controller transferring commands and addresses.
  2. 2.根据权利要求1所述的基于DMA传输的Flash存储控制系统,其特征在于,所述Flash存储阵列中所有FLASH使用相同的控制信号,同一列的FLASH的片选信号相同,但数据通道不同,同一行的FLASH的片选信号不同,而数据通道相同。 The Flash-based storage control system according to claim 1 DMA transmission, wherein said control signal all Flash FLASH memory array using the same, the same FLASH chip select signal in the same column, but with different data channels different FLASH chip select signal of the same row, the same data channel.
  3. 3.根据权利要求1所述的基于DMA传输的Flash存储控制系统,其特征在于,所述Flash存储阵列为4X4的NAND FLASH阵列。 Flash memory 3. The control system based on DMA transfer according to claim 1, wherein said array is a NAND FLASH Flash memory array of 4X4.
  4. 4.根据权利要求1所述的基于DMA传输的Flash存储控制系统,其特征在于,所述的命令和地址通过八选一选择器发送到Flash的1总线上。 Flash memory 4. The DMA transfer control system based on the claim 1, characterized in that said command and address sent to the bus through eight Flash 1 is selected from a selector.
CN 201420295531 2014-06-05 2014-06-05 Flash memory control system based on DMA transmission CN204129729U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104657296A (en) * 2015-01-30 2015-05-27 西安华芯半导体有限公司 Chip architecture with multiple compatible data interfaces

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104657296A (en) * 2015-01-30 2015-05-27 西安华芯半导体有限公司 Chip architecture with multiple compatible data interfaces
CN104657296B (en) * 2015-01-30 2017-12-26 西安紫光国芯半导体有限公司 Multi-data interface compatible chip architecture

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