KR20070027215A - Dual port ram control method - Google Patents

Abstract

A method for controlling a DPRAM(Dual Port RAM) is provided to implement a FIFO(First Input First Output) function with a small capacity FPGA(Field Programmable Gate Array) by minimizing logic resources in case that the DPRAM is controlled through the FPGA by using HDL(Hardware Description Language). In case that a cell to be written is occurred in a cell pointer counter, the cell is written(S102). It is checked whether the last bit of the cell is written or not(S103). In the case that the cell is completely written, the next cell is written and an address area is jumped(S104). It is checked whether the next pointer counter is used up or not after address jump(S105). In the case that the counter is not used up, a write pointer counter value is output. In the case that the counter is used up, the write pointer counter value is output after a carry is inverted(S106).

Description

Dual port RAM control method

1 is a diagram illustrating an address allocation according to bank division of a DPRAM in the prior art;

FIG. 2 is a diagram showing a counter configuration in a specific bank of a prior art DPRAM.

3 is a flowchart illustrating a method of controlling a conventional DRAM (DPRAM).

FIG. 4 is a diagram illustrating a counter configuration in a specific bank of a dipram for the DPRAM control according to the present invention.

FIG. 5 is a flowchart illustrating a process of a method for controlling a DPRAM according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating an embodiment in which the method for controlling a depiram of the present invention is applied to a board having an Abis interface function in a CDMA2000 1x and EV-DO system.

The present invention relates to a dual port ram (DPRAM), and more particularly, to a pointer for controlling a DPRAM when a FIFO is implemented using a DPRAM in a network node. The present invention relates to a method of controlling the depiram to be implemented through a minimum of logical resources.

DPRAM is a memory in which a write port and a read port are separated, and is suitable for forming a first in first out (FIFO). First-in-first-out (FIFO) implemented with the above-mentioned deep-ramp (DPRAM) requires a technology for controlling the deep-ramp (DPRAM), unlike commercial FIFOs released by chip vendors, mainly VHDL (Very High Speed). Use the Integrated IC (VHISC) hardware description language.

As described above, the control technique may divide the DPRAM into an address area and divide the plurality of banks into banks, thereby implementing n FIFOs.

1 illustrates an address allocation according to bank division of a DPRAM in the prior art.

Suppose the width is m bits, and the address (entry) is divided into n banks of equal size using k private disks (DPRAMs) to form n FIFOs. The address of the first bank is 0 to (k / n) * 1. The address area of the second bank is (k / n) * 1 + 1 to (k / n) * 2, and the address area of the last nth bank is ((k / n) * (n-1) + 1 to k .. The corresponding areas may vary according to the size of the DPRAM and the bank configuration of the user.

FIG. 2 shows a counter configuration in a specific bank of a prior art DPRAM. As a specific bank, bank # 0 is taken as an example.

The address area of bank # 0 is 0 to (k / n) * 1. If the ATM cell is stored in the storage of DPRAM, the ATM cell is composed of 53 bytes, so the first ATM cell is located in the address 0 to 52 of the corresponding bank. The second cell is stored in an area 53 to 104. When an ATM cell is written and read in the DPRAM, each write or read pointer is created and the two pointers are compared and the ATM cells stored in the DPRAM are stored. You can grasp the current situation.

The pointer management in the case of the prior art as described above is as follows.

First, when the first ATM cell is written to (or read from) Bank # 0, a counter is incremented by one counter outside the DPRAM. In addition, the carry bit (CARRY Bit) is placed to control the counter (cyclic counter) operation.

Such a configuration is performed in the same way at the same time in each of the Write and Read ports, and FIG. 2 shows only one port.

3 is a flowchart illustrating a method of controlling a conventional DRAM (DPRAM).

A method of controlling a DPRAM of FIG. 3 illustrates an operation in a specific bank of the DPRAM, and operates in the same procedure in other banks. In the above-described method for controlling a DPRAM, a process is started when the DPRAM and the FPGA for controlling the DPRAM are initialized.

As shown in FIG. 3, the control process of the DPRAM includes a write process by a write function and a read function by a write function for writing data to the DPRAM. Process, and a counter compare process to compare the write pointer and the read pointer.

First, in the writing process by the write function, wait until an ATM cell to write (write) to DPRAM occurs and then generate an ATM cell to write. (S11) ATM cell write is performed (S12).

After that, the byte of the ATM cell to be recorded while writing the bytes of the ATM cell to the DPRAM by ATM cell write is the last byte, that is, the 53rd byte. The acknowledgment is checked, and if it is not the last byte, ATM cell writing is continued (S13).

As a result of the check in S13, when the ATM cell is written in the DPRAM by the ATM cell write, the 53th byte is written and the 53th byte is written, and one ATM cell is written. The write process of the next ATM cell is performed again, and at the same time, a write counter update is performed to increase the write counter by 1 to control the write counter. That is, each write of one ATM cell increments the write counter by one. Here, the write counter is composed of (k / n) -1 counters and 1 bit carry using one logic cell of the FPGA. Each time a cell is written to the bank, the counter is increased by one (S14).

Thereafter, it is determined whether (k / n) -1 counters are exhausted (S15).

As a result of the determination in step S15, if the counter is not exhausted, the process moves to the step S30, and if the counter is exhausted, carry is reversed.

The carry is a bit for circulating the counter when (k / n) -1 counters are exhausted. When the counter is exhausted, the carry is 0. Is reversed from 1 to 1 or from 1 to 0. Therefore, each time the write counter is incremented, it checks whether the counter is (k / n) -1st, otherwise it does not reverse the carry and the counter is (k / n)-. If it is the first time, the write carry is inverted (S16).

In FIG. 3, the read process by the read function is operated simultaneously with the write process by the write function, and the function is to update the read counter after reading the ATM cell and to reverse the carry when the read counter is exhausted. S21 to S26), and the same operation as that of the write function by the write function described above is omitted.

In FIG. 3, after the write function of the DPRAM in steps S11 to S16 and the read function of the DPRAM in steps S21 to S26 are performed, a write pointer corresponding to the counter compare unit may be written. The counter comparison process is performed by passing a write carry, a read pointer, and a read carry. That is, the current state of ATM cells stored in the DPRAM is determined by calculating a write pointer and a write carry, a read pointer, and a read carry (S30). ).

The counter compare process of S30 processes information such as data empty, data full, and programmable full of ATM cells stored in DPRAM. To control DPRAM.

In this case, the data empty indicates that there is no ATM cell written in the corresponding bank of the DPRAM, and the data pool indicates the corresponding bank of the DPRAM. ATM cell is recorded in the memory of the whole area of) and it is not read yet, so there is no memory for ATM cell to be written anymore. It is the state that exceeds the level of defined data pool.

The prior art DPRAM control method as described above performs a write counter update process when one ATM cell is written, wherein the write counter is an FPGA logic resource ( Logic Resource). Therefore, the function of increasing the counter every time an ATM cell is written is performed using a Logic Resource, so that the size of the DPRAM becomes large, or When divided into a number of banks (DPRAMs), the number of counters to be managed increases, so that the waste of logic resources also increases.

Also, in the read function, the corresponding logical resource is wasted as in the write function, so the waste of the resource is doubled and the FPGA logic is enormous. FPGAs are required, and eventually, expensive FPGAs with large capacities are needed to implement the functions.

As described above, the control method of the conventional DPRAM has a larger problem as the size of the DPRAM and the number of banks increase, and in addition, the write counter. (Or a read counter) has to be updated separately each time an ATM cell is written (or read each time), thereby complicating the function implementation.

Accordingly, the present invention is to solve the above-mentioned problems of the prior art, when implementing a FIFO by using a DPRAM in a network node (Network Node), a pointer for controlling the DPRAM (DPRAM) to a minimum logic If you control the DPRAM with HDL through the FPGA by implementing the resource (Logic Resource), a method of controlling the depiram to implement the FIFO function with a small capacity FPGA by minimizing the logic resource. Its purpose is to provide.

The object of the present invention described above is achieved by using the address ADDRESS of the corresponding DPRAM without implementing the counter function of the DPRAM as a separate counter.

That is, the present invention for achieving the above object is a FIFO by a defiram having a depiram and a carry by dividing an address area into a cell pointer counter area and a cell byte counter area. A writing process of writing a cell if it occurs; A write completion determination step of determining whether the last byte of a cell to be written by the writing process is recorded; An address area jumping process of moving to the writing process to perform writing of the next cell and jumping to an address area when writing to one cell is completed as a result of the determination of the write completion determination process; A pointer counter exhaustion determining step of determining whether the pointer counter is exhausted after the address area jump process; A write pointer counter outputting step of outputting a write pointer counter value when the counter is not exhausted as a result of the determination of the pointer counter exhaustion determination process; And a carry control process of inverting the carry and outputting a write pointer counter value when the counter is exhausted as a result of the determination of the pointer counter exhaustion determination process.

Another object of the present invention for achieving the above object is a FIFO by a defiram having a depiram and a carry having an address area divided into a cell pointer counter area and a cell byte counter area. A reading process of reading a cell if it occurs; A read completion determination step of determining whether the last byte of the cell to be read by the read step is read; An address area jump process of reading a next cell and jumping an address area when reading of one cell is completed as a result of the determination of the read completion determination process; A pointer counter exhaustion determining process of determining whether the pointer counter is exhausted after the address area jump process; A read pointer counter outputting step of outputting a read pointer counter value when the counter is not exhausted as a result of the determination of the pointer counter exhaustion determination process; And a carry control process of inverting the carry and outputting the read pointer counter value when the counter is exhausted as a result of the determination of the pointer counter exhaustion determination process.

In the above process, the address area of the depiram has a bank having at least one or more M bit widths in the case of writing, and a write pointer counter is composed of sixth to mth bits, and a cell byte counter. (cell byte counter) is characterized by consisting of the 0 th bit to the fifth bit.

In the above process, the address area of the depiram has at least one or more M bit banks in case of reading, and a read pointer counter is composed of sixth to mth bits, and read or write. The cell byte counter in the defiram for is characterized by consisting of the 0 th bit to the fifth bit.

In the above-described processing, the address area jumping process includes: a bit area jumping process characterized by jumping 12 bits in the address area when one cell has been written or read up to the 52nd bit; And a counter setting step of setting the pointer counter to a counter value after the bit area jump process.

The cell is characterized by being a 53 byte ATM cell.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 4 is a diagram illustrating a counter configuration in a specific bank of the depiram for controlling the DPRAM of the present invention.

As shown in FIG. 4, 53 bytes (from bank # 0 of the DPRAM having a width of M bits and a (k / n) -1 address (entry)) It consists of an ATM cell byte counter for writing an ATM cell of a byte and a pointer counter for managing a pointer.

Since 6 bits (6 powers of 2 = 64) are required to write 53 bytes, bits 0 through 5 of the DPRAM are the ATM cell byte counter. byte counter), and the rest of the sixth bit (bit) to m-th bit (bit) is composed of a pointer counter (pointer counter). A separate carry is configured outside the DPRAM for the cyclic operation of the counter. The above-mentioned carry is composed of one bit each for a write port and a read port, and the operation of the carry is the same as that of the prior art.

FIG. 5 is a flowchart illustrating a process of a method for controlling a DPRAM according to an embodiment of the present invention.

According to an embodiment of the present invention, a method for controlling a dephram (DPRMA) according to an exemplary embodiment of the present invention is illustrated in the description of the method for controlling a dephram (DPRAM) of the prior art of FIG. 3. This is the same procedure as the other banks. When the DPRAM and the FPGA for controlling the DPRAM are initialized, the process starts. The process of controlling the DPRAM is for writing data to the DPRAM. Writing process by Write Function, Reading process by Read Function, and Counter Compare process to compare Write Pointer and Read Pointer It consists of.

Since the write process by the write function and the read process by the read function are operated in the same manner, the process of FIG. 5 will be described on behalf of the write function.

The write function waits until an ATM cell to be written (write) to a DPRAM occurs (S101) and if an ATM cell to write occurs (S11). ATM cell write is performed by performing an ATM cell write process (cell writing process) (S102).

After that, the ATM cell in which the ATM cell is being written while writing the ATM cell to DPRAM by ATM cell write process is the last byte of the ATM cell, If it is not the last byte, it checks whether or not the 53 th byte is used (S103).

On the contrary, when the determination result of step S103 indicates that the byte of the ATM cell written to the DPRAM by ATM cell write is the last byte of the ATM cell, that is, the 53 th byte. When the 53 th byte is written and one ATM cell is used up, the process moves to step S101 to perform the cell writing process of the next ATM cell again and simultaneously performs an address jump (S104). .

The above-mentioned address jump jumps 12 address regions to the 64th bit where the second cell is written when the first cell shown in FIG. 4 is used up to the 52nd bit. Says that. The above 64 th bit is represented by 0000..0001 000000. Here, the write pointer counter is 0000..0001 consisting of the 6th bit to the mth bit, and the cell byte counter is 000000 consisting of the 0th bit to the 5th bit. Therefore, a pointer counter of this address is used as a counter. In other words, a write pointer counter is created in this process.

The above operation is repeated to determine whether the (k / n) -1 pointer counter is exhausted (S105).

If the write pointer counter is not exhausted as a result of the above-described determination in step S105, the write pointer generated in step S104 is output for the counter comparison process. In contrast, when the pointer counter is exhausted as a result of the determination in step S105, the carry is inverted for the circulation of the pointer counter. The carry is a bit for circulating the counter when (k / n) -1 counters are exhausted. When the counter is exhausted, the carry is 0. Is reversed from 1 to 1 or from 1 to 0. Therefore, each time the Write Pointer Counter is incremented, it checks whether the counter is (k / n) -1st, otherwise the counter does not invert Carry, and the counter is (k / n). In step S106, the write carry is inverted (S106).

The write process using the write function for the DPRAM operates as the above process, and the write pointer counter generated during the address jump process is compared with the counter compare process. It outputs for execution and checks whether the carry bit is inverted and performs counter update.

In FIG. 5, the read process by the read function is operated simultaneously with the write process by the write function as in FIG. 3, and the process is performed by reading an ATM cell and then reading a counter allocated to an address area of a DPRAM. Since the pointer is updated and the read counter is exhausted, the operation of inverting the read carry (S111 ˜ S116) is performed in the same manner as the write process by the write function described above, and thus the detailed description thereof will be omitted.

In FIG. 5, after the write function of the DPRAM in steps S101 to S106 and the read function of the DPRAM in steps S111 to S116 are performed, the corresponding write pointer counter is written as a counter compare process. Counter and Read Pointer Counter, and in the Counter Compare process of S120, the Write Pointer Counter and Read Pointer Counter are calculated to calculate the DPRAM. Determine the current state of the ATM cell stored in step (S120).

The counter compare process of S120 processes information such as data empty, data full, and programmable full of ATM cells stored in DPRAM. To provide control of the DPRAM is the same as in the prior art.

Figure 6 is a block diagram of ALPA-B as an embodiment to which the diffiram control method of the present invention is applied. That is, the present invention described above may be applied to a board having an Abis interface function in the CDMA2000 1x and EV-DO systems as shown in FIG. 6.

As an example in which part A of the configuration of ALPA-B of FIG. 6 implements FIFO by using a DPRAM to which the DEPRAM control method of the present invention is applied, the FPGA (LINK_UP) controls the DPRAM. In addition, the depiram control method described in the description of the operation of the present invention may be configured to be included in the FPGA LINK_UP to operate.

The present invention described above can be equally applied to ALPA-I, LICA-I, ALPA-A as well as ALPA-B board.

As described above, the present invention can be implemented in a FPGA having a smaller capacity as it is composed of a minimum of logical resources in configuring a counter of a write port and a read port. It has the effect of lowering the unit cost in implementing the same function FPGA.

In addition, the present invention described above implements a pointer function by utilizing a DPRAM address area without configuring a separate counter, thereby implementing a DPRAM size and a bank ( FPGA can be configured for the depiram control regardless of the number of banks, so the logic resource can be minimized to provide the minimum cost when implementing the FPGA with the same function. do.

Claims (5)

In a FIFO by a defiram having a depiram and a carry divided into an address area and a cell byte counter area, Writing a cell when a cell to be written to the cell pointer counter is generated; A write completion determination step of determining whether the last byte of a cell to be written by the writing process is recorded; An address area jumping process of moving to the writing process to perform writing of the next cell and jumping to an address area when writing to one cell is completed as a result of the determination of the write completion determination process; A pointer counter exhaustion determining step of determining whether the pointer counter is exhausted after the address area jump process; A write pointer counter outputting step of outputting a write pointer counter value when the counter is not exhausted as a result of the determination of the pointer counter exhaustion determination process; And a carry control process of inverting the carry and outputting a write pointer counter value when the counter is exhausted as a result of the determination of the pointer counter exhaustion determination process. In a FIFO by a defiram having a decode and a carry in which an address area is divided into a cell pointer counter area and a cell byte counter area, Reading a cell when a cell to be read is generated by the cell pointer counter; A read completion determination step of determining whether the last byte of the cell read by the read step is read; An address area jump process of reading a next cell and jumping an address area when reading of one cell is completed as a result of the determination of the read completion determination process; A pointer counter exhaustion determining step of determining whether the pointer counter is exhausted after the address area jump process; A read pointer counter outputting step of outputting a read pointer counter value when the counter is not exhausted as a result of the determination of the pointer counter exhaustion determination process; And a carry control process of inverting the carry and outputting the read pointer counter value when the counter is exhausted as a result of the determination of the pointer counter exhaustion determination process. The address area of claim 1 or 2, wherein Has a bank of at least one or more M bit widths, the write and read pointer counters consist of the sixth to mth bits, and the write and read cell byte counters from the zeroth bit. Depiram control method characterized in that consisting of the fifth bit. The method of claim 1 or 2, wherein the address region jumping process is performed by: A bit area jumping process characterized by jumping 12 bits in an address area when one cell is used up or read; And a counter setting step of setting the pointer counter to a counter value after the bit area jump process. The method of claim 1 or 2, wherein the cell is an ATM cell.

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