CN102263884A - Video image processor - Google Patents
Video image processor Download PDFInfo
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- CN102263884A CN102263884A CN2011102117529A CN201110211752A CN102263884A CN 102263884 A CN102263884 A CN 102263884A CN 2011102117529 A CN2011102117529 A CN 2011102117529A CN 201110211752 A CN201110211752 A CN 201110211752A CN 102263884 A CN102263884 A CN 102263884A
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Abstract
The embodiment of the invention discloses a video image processor, comprising a double-interface RAM (random access memory) receiver, a baud rate generator and a double-interface RAM transmitter. The video image processor is used for realizing data serial communication between the video image processor subsystem and a system on an FPGA (field programmable gate array); a UART (universal asynchronous receiver transmitter) serial data transmission protocol is adopted; and a communication transmission baud rate and FPGA system clock frequency are both subjected to parameterization design to satisfy the requirements of the main frequency and the transmission baud rate of different systems. Data to be transmitted and received are separately processed, time for the processor to process data is shortened by the double-interface RAM, and speed for the processor to process video data is improved so as to guarantee the requirement of real-time transmission.
Description
Technical field
The present invention relates to digital home technical field, relate in particular to a kind of video image processor.
Background technology
The research of Digital Image Processing comes from two main application fields: the first is improved image information for the ease of people analyze; It two is for machine is automatically understood view data to be stored, transmits and shows.From the sixties in 20th century so far, digital image processing field has obtained great development.The purpose of early stage image processing is to improve the quality of image, and it is purpose with artificial object with the visual effect of improving the people.In the image processing, input be low-quality image, output be the image that improves after the quality, image processing method commonly used has figure image intensifying, recovery, coding, compression etc.Since the seventies in last century, the computer vision development is rapid, and people are divided into it two levels usually: the image processing of low layer and high-rise image understanding.
The low layer computer vision technique overlaps fully with Digital Image Processing, its treatment step is generally: image is obtained by a transducer (for example TV video camera) and with its digitlization, carry out noise suppressed then, then carry out the figure image intensifying, to strengthen the object features relevant with image understanding.Image segmentation is a following step, and computer is attempted object is separated from background, and they are distinguished each other.
High-rise computer vision depends on knowledge, target and the plan that how to reach these targets.High-rise computer vision attempts to imitate human cognition and the ability of making a strategic decision according to the information that is included in the image.High-rise vision will compare with this model by " truly " of digitized image perception then from the formalization world model of certain form, attempts to find out coupling.When difference displays, just seek part coupling (or sub-goal) and overcome mispairing; Computer turns to the low layer image processing, seeks to be used for the more information of new model.This process is carried out repeatedly, and therefore " understanding " image becomes a cooperation between top-down and bottom-up two processes.Introducing a feedback loop, be that the image processing of low layer is offered the challenge from the partial results of high level, and image understanding process repeatedly should finally converge on the target of the overall situation.The figure image intensifying belongs to the low layer segment of computer vision, refers to by some information in the outstanding image of specific needs, weakens simultaneously or removes some unwanted information processing method.Its main purpose is to make image after the processing concerning certain specific application, and is more suitable than original image.Therefore, the figure image intensifying goes to improve picture quality for certain application purpose, and the result of processing makes image be more suitable for the recognition system of human vision property or machine.The quality of image reinforced effects directly influences the effect of image segmentation and the result of high-rise image understanding.
In video image processing system, such as operations such as image subtractions, the data volume of processing is very big, and is very high to the requirement of processing speed, but algorithm structure is simple relatively, is fit to carry out hardware with FPGA and realizes.The present invention adopts and carry out the image/video processing on FPGA.Because the exploitation of FPGA has very strong flexibility, therefore, can utilize the resource of FPGA, on chip, realize the serial communication function that video image is handled, thereby simplified circuit, dwindled volume, improved reliability, and very big flexibility has been arranged in the use.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of video image processor is provided, can utilize the resource of FPGA, on chip, realize the serial communication function that video image is handled, thereby simplified circuit, dwindled volume, improved reliability, and very big flexibility has been arranged in the use.
A kind of video image processor comprises double nip RAM receiver, Baud rate generator, dual port RAM transmitter; This video image processor is communicated by letter with the data serial between the system in realization video image processor subsystem on the FPGA, adopt the UART serial data transport protocol, Transmission bit rate, the FPGA system clock frequency of communication all adopts the parametrization design, can satisfy different system dominant frequency and Transmission bit rate requirement.
Preferably, subsystem send to receive frame head, postamble, is used for the correctness that judgment data receives; Data format is 0,8 data figure place of a start bit low level, and 1, one serial data of a position of rest high level is 10.
Preferably, be to solve the asynchronous communication problem of serial ports and video image part, adopted and on FPGA, produced docking of dual port RAM realization serial ports and video image processing section; Dual port RAM is exactly the memory of storage data sharing, is equipped with two and overlaps independently address, data and control line, allows two independent CPUs or controller while storage unit access asynchronously, is particularly suitable for the asynchronous high-speed communication between the asynchronous processor; The storage size of dual port RAM and data address figure place all adopt the parametrization design, make the storage size of dual port RAM to adjust according to the practical application needs, have increased flexibility and versatility that serial ports uses.
Preferably, serial ports is when receiving data, and desirable sampled point is the centre in data bit; For bits of serial data is accurately sampled, can carry out segmentation to the data bit time, segments is big more, and then sampled point is the closer to intermediate point, but also increased the expense of system simultaneously; 16 times of time slices have been adopted among the design.
Preferably, the serial ports transmitter adopts dual port RAM to dock with the video image processing section, the video image processing section sends to parallel data in the dual port RAM then, transmitting control signal is under the control of video field sync signal, by the serial ports transmitter parallel data in the dual port RAM is read out, and transfer serial data to and send.
Preferably, the serial ports receiver adopts dual port RAM to dock with the video image processing section, and receiver is converted to parallel data with the serial data that receives and is stored in the dual port RAM.The video image processing section then can be read parallel data and handle when being carried out data processing according to the control port of dual port RAM, and its sense data process is similar with write data process in transmitter.
Beneficial effect of the present invention:
1) by can in transmission course, guaranteeing reliability of data transmission to the video data conversion of handling, be transformed into the parallel transmission of internal system by the serial transmission of outside, effectively improved the processing speed of video data;
2) in this design, effectively shortened time of processor processes data, improved the speed of processor processing video data, thereby guaranteed the requirement of real-time transmission the data separate processes of the data that will send and acceptance and with dual port RAM.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the overall construction drawing of video image processor of the present invention;
Fig. 2 is the structure chart of baud rate generator module in the video image processor of the present invention;
Fig. 3 is the structure chart of the transmitter module of band dual port RAM in the video image processor of the present invention;
Fig. 4 is the structure chart of band dual port RAM receiver module in the video image processor of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
The objective of the invention is in the data serial design of communication that realizes on the FPGA between video image processor subsystem and the system, based on a kind of video image processor, by changing signal transmission form and design parameter, realize the real-time requirement that video and graphic is handled, offer user's system communication more reliably.
A kind of video image processor, general structure comprise double nip RAM receiver, Baud rate generator, dual port RAM transmitter as shown in Figure 1.This video image processor is communicated by letter with the data serial between the system in realization video image processor subsystem on the FPGA, adopt the UART serial data transport protocol, Transmission bit rate, the FPGA system clock frequency of communication all adopts the parametrization design, can satisfy different system dominant frequency and Transmission bit rate requirement.Subsystem send to receive frame head, postamble, is used for the correctness that judgment data receives.Data format is 0,8 data figure place of a start bit low level, and 1, one serial data of a position of rest high level is 10.
Be to solve the asynchronous communication problem of serial ports and video image part, adopted and on FPGA, produced docking of dual port RAM realization serial ports and video image processing section.Dual port RAM is exactly the memory of storage data sharing, is equipped with two and overlaps independently address, data and control line, allows two independent CPUs or controller while storage unit access asynchronously, is particularly suitable for the asynchronous high-speed communication between the asynchronous processor.The storage size of dual port RAM and data address figure place all adopt the parametrization design, make the storage size of dual port RAM to adjust according to the practical application needs, have increased flexibility and versatility that serial ports uses.
In video image is handled, be requirement of real time, one time image processing is finished in the time in a field picture, so the available video field sync signal transmits control signal as the serial ports transmitter.PAL television system regulation, field-scanning period is 50Hz, a two field picture is divided into odd field and even field.
Baud rate generator designs as shown in Figure 2:
Rst_n: systematic reset signal
Clk: system clock frequency
Clk_16x: output baud rate (Transmission bit rate clock frequency 16 times)
Serial ports is when receiving data, and desirable sampled point is the centre in data bit.For bits of serial data is accurately sampled, can carry out segmentation to the data bit time, segments is big more, and then sampled point is the closer to intermediate point, but also increased the expense of system simultaneously.In design is used, 16 times of time slices have been adopted.
The reception of serial ports is to carry out according to identical baud rate with transmission, and the clock frequency that Baud rate generator produces is not the baud rate clock frequency, but 16 times (promptly the width of a transmission position is 16 clk_16x clock cycle) of baud rate clock frequency.Can calculate the baud rate count value according to the baud rate of given system clock frequency and requirement.The supposing the system clock frequency is 40MHz, and the Transmission bit rate of requirement is 115 200b/s, then can produce Counter=(Clk_fequency/ (2*16*Baud_rate))-1, when promptly clk being count down to Counter clk_16x is overturn once.In programming, adopt the parametrization design, can change the baud rate size according to application requirements.
Parameter Clk_frequency=40000000, // system clock frequency 40MHz
Baud_rate=115200, // require Transmission bit rate to be worth 115 200b/s
Counter=(Clk_frequency/ (2*16*Baud_rate))-1, Width=7; // can store the required figure place of binary form of Counter value.
The band dual port RAM transmitter module as shown in Figure 3:
Data_out: serial output
Vs: (video field sync signal) transmits control signal
Cs: the chip selection signal of dual port RAM
Wren: dual port RAM write enable signal
Addr: the address wire of dual port RAM
Data: the data wire of dual port RAM
The serial ports transmitter adopts dual port RAM to dock with the video image processing section, the video image processing section sends to parallel data in the dual port RAM then, under the control of transmit control signal (video field sync signal), by the serial ports transmitter parallel data in the dual port RAM is read out, and transfer serial data to and send.
For simplifying of the control of serial ports transmitter, adopted dual port RAM and transmitter have been accomplished a mode in the module dual port RAM.Therefore, for transmitter, dual port RAM just is equivalent to an internal storage, can directly carry out read-write operation to it, and not need extra memory control port and data transmission interface.
Transmitter arrives from (field sync signal) Vs that transmits control signal, and exports 1 bit data every 16 clk_16x cycles, and order is 1 start bit, 8 bit data positions and 1 position of rest, and data bit is for sending form from the low level to a high position.Transmitter adopts the state machine style to be described, and being divided into is 5 state: idle condition S0, initial state S1, wait state S2, displaced condition S3, halted state S4.
In the state machine transfer process, need a bit register variable to judge whether the data that will send send, only the number byte data in the dual port RAM is sent one time to guarantee a field sync signal.In a single day system resets, and transmitter just enters the S0 state, simultaneously a bit wide is deposited type variable num and puts 0.
Idle condition S0: finish initial work at this state, i.e. register initialize (data that comprise dual port RAM are read address addr_cnt clear 0) to using, and Data_out is exported in serial be changed to high level.When Vs effective (during the field synchronization) and num==0 establishment, enter the S1 state.Between dynamic stage, num is put 0 at Vs, and continue at the S0 state.
Initial state S1: provide start bit low level 0, be about to Data_out and put 0, simultaneously the data of current addr_cnt address are read and deposited in transmission shift register shift_reg from dual port RAM, system enters the S2 state.
Wait state S2: at this state, wait for 16 clk_16x at every turn, that is: guarantee 16 clk_16x clock cycle of width bits of every, comprise the start bit wait, wait for 9 times, wherein, it is 8 times that data bit is waited for.If wait for that number of times in 9 times, then changes the S3 state over to, otherwise, change the S4 state over to.
Displaced condition S3: with shift_reg[0] compose and give Data_out, realize simultaneously from a high position to low bit shift.Enter the S2 state.
Halted state S4: provide position of rest high level 1, be about to Data_out and be changed to high level, and full 16 clk_16x of meter.Then, judge whether with memory[number-1:0] in the data of number byte all export, if do not have, just change the S1 state over to and continue output, otherwise, just enter the S0 idle condition, simultaneously num is put 1.
The band dual port RAM receiver module as shown in Figure 4:
Data_in serial input
The chip selection signal of Cs_rd dual port RAM
The Rd dual port RAM read enable signal
The address wire of addr_rd dual port RAM
The data wire of Data_rd dual port RAM
The serial ports receiver adopts dual port RAM to dock with the video image processing section, and receiver is converted to parallel data with the serial data that receives and is stored in the dual port RAM.The video image processing section then can be read parallel data and handle when being carried out data processing according to the control port of dual port RAM, and its sense data process is similar with write data process in transmitter.
When receiving the start bit of a serial data frame, transfer logical zero to by logic and judge.For fear of the influence of burr (cycle is very short), can access correct start bit signal, the start bit that necessarily requires to receive has at least 1/4 all to be to belong to logical zero can assert that just what receive is start bit.Because the clock frequency that Baud rate generator produces is for receiving 16 times of the serial data baud rate, thus count 4 times just can deburring influence.
Receiver adopts the state machine style to be described, and being divided into is 5 states: initial state S0, delaying state S1, wait state S2, displaced condition S3, halted state S4.
After the system reset,, enter the S0 state to the initialization of register that will use.
Initial state S0: be 0 and keep 4 clk_16x if serial ports is imported Data_in, just judge that start bit signal (low level) arrives, and enters the S1 state.
Delaying state S1: count 4 times clk_16x, add totally 8 times 4 times that the S0 state has been counted.Because the clock clk_16x that receiver adopts is 16 times of baud rate,, then count the centre that can guarantee sampled point at the start bit level 8 times so a serial bit has 16 clk_16x clock cycle.Enter the S2 state.
Wait state S2: count 16 times clk_16x, that is: sampled point is in the centre of next serial bit.Then, judge whether to be shifted 8 times,, then change the S3 state over to if do not have; Otherwise, change the S4 state over to.Displaced condition S3: Data_in is imported in serial compose highest order shift_reg1[7 to the internal displacement register], realize that simultaneously shift_reg1 is from a high position to low bit shift once.Enter the S2 state.Halted state S4: shift_reg is deposited in the dual port RAM.Judge whether that the data number that will need to receive receives, if do not have, then the memory address in dual port RAM adds up automatically, otherwise, the memory address in the dual port RAM clear 0.Enter the S0 state.
Can also separately handle the data that send by add dual processor in processor system in the present invention, the data after the processing are sent into buffer memory and are for further processing, thereby have accelerated the processing speed to video data.
More than a kind of video image processor that the embodiment of the invention provided is described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (6)
1. a video image processor is characterized in that, comprises double nip RAM receiver, Baud rate generator, dual port RAM transmitter; This video image processor is communicated by letter with the data serial between the system in realization video image processor subsystem on the FPGA, adopt the UART serial data transport protocol, Transmission bit rate, the FPGA system clock frequency of communication all adopts the parametrization design, can satisfy different system dominant frequency and Transmission bit rate requirement.
2. video image processor as claimed in claim 1 is characterized in that, subsystem send to receive frame head, postamble, is used for the correctness that judgment data receives; Data format is 0,8 data figure place of a start bit low level, and 1, one serial data of a position of rest high level is 10.
3. video image processor as claimed in claim 1 is characterized in that, be to solve the asynchronous communication problem of serial ports and video image part, has adopted and produce docking of dual port RAM realization serial ports and video image processing section on FPGA; Dual port RAM is exactly the memory of storage data sharing, is equipped with two and overlaps independently address, data and control line, allows two independent CPUs or controller while storage unit access asynchronously, is particularly suitable for the asynchronous high-speed communication between the asynchronous processor; The storage size of dual port RAM and data address figure place all adopt the parametrization design, make the storage size of dual port RAM to adjust according to the practical application needs, have increased flexibility and versatility that serial ports uses.
4. video image processor as claimed in claim 1 is characterized in that, serial ports is when receiving data, and desirable sampled point is the centre in data bit; For bits of serial data is accurately sampled, can carry out segmentation to the data bit time, segments is big more, and then sampled point is the closer to intermediate point, but also increased the expense of system simultaneously; 16 times of time slices have been adopted among the design.
5. video image processor as claimed in claim 1, it is characterized in that, the serial ports transmitter adopts dual port RAM to dock with the video image processing section, the video image processing section sends to parallel data in the dual port RAM then, transmitting control signal is under the control of video field sync signal, by the serial ports transmitter parallel data in the dual port RAM is read out, and transfer serial data to and send.
6. video image processor as claimed in claim 1 is characterized in that, the serial ports receiver adopts dual port RAM to dock with the video image processing section, and receiver is converted to parallel data with the serial data that receives and is stored in the dual port RAM.The video image processing section then can be read parallel data and handle when being carried out data processing according to the control port of dual port RAM, and its sense data process is similar with write data process in transmitter.
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| CN2011102117529A CN102263884A (en) | 2011-07-27 | 2011-07-27 | Video image processor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102802038A (en) * | 2012-07-25 | 2012-11-28 | 华中科技大学 | Binary image template matching system based on parallel bit stream processor |
| CN104581357A (en) * | 2015-01-13 | 2015-04-29 | 成都千牛信息技术有限公司 | Cache logic structure and method suitable for image extraction in FPGA |
| CN110120922A (en) * | 2019-05-14 | 2019-08-13 | 中国核动力研究设计院 | A kind of data interaction Network Management System and method based on FPGA |
-
2011
- 2011-07-27 CN CN2011102117529A patent/CN102263884A/en active Pending
Non-Patent Citations (1)
| Title |
|---|
| 郑勇等: "基于 FPGA 的视频图像处理器的串行通信设计", 《集成电路应用》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102802038A (en) * | 2012-07-25 | 2012-11-28 | 华中科技大学 | Binary image template matching system based on parallel bit stream processor |
| CN104581357A (en) * | 2015-01-13 | 2015-04-29 | 成都千牛信息技术有限公司 | Cache logic structure and method suitable for image extraction in FPGA |
| CN104581357B (en) * | 2015-01-13 | 2018-03-30 | 成都千牛信息技术有限公司 | It is applied to the cache logic method of image contract in FPGA |
| CN110120922A (en) * | 2019-05-14 | 2019-08-13 | 中国核动力研究设计院 | A kind of data interaction Network Management System and method based on FPGA |
| CN110120922B (en) * | 2019-05-14 | 2022-09-20 | 中核控制系统工程有限公司 | FPGA-based data interaction network management system and method |
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Application publication date: 20111130 |