CN104581357B - It is applied to the cache logic method of image contract in FPGA - Google Patents
It is applied to the cache logic method of image contract in FPGA Download PDFInfo
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- CN104581357B CN104581357B CN201510015736.0A CN201510015736A CN104581357B CN 104581357 B CN104581357 B CN 104581357B CN 201510015736 A CN201510015736 A CN 201510015736A CN 104581357 B CN104581357 B CN 104581357B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/433—Content storage operation, e.g. storage operation in response to a pause request, caching operations
- H04N21/4331—Caching operations, e.g. of an advertisement for later insertion during playback
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
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Abstract
The invention discloses the cache logic framework and method for being applied to image contract in FPGA, it is included in one group of Block RAM for being configured to twoport pattern in FPGA, realizes that image write-in logical sum image reads logic；The Block RAM complete view data caching；Described image write-in logic realization view data is by specific format deposit Block RAM；Described image reads logic realization and presses set image output mode, is read from Block RAM with particular order and view data of resequencing, and exports reordered view data, and methods described includes realizing image write-in logical sum image reading logic；Image, which reads logic, includes output full resolution image step, full resolution image step is exported, completes the image sampling point extract function required in vision facilities, while do not reduce bandwidth chahnel, vision facilities processing pressure is reduced, but does not reduce the performance of final output image quality.
Description
Technical field
Patent of the present invention is related to image transmitting logic technology field in vision facilities, specifically, is applied in FPGA
The cache logic framework and method of image contract.
Background technology
Vision facilities, it is that image is obtained by imaging sensor and optical device, and carries out setting for respective image processing
It is standby, such as video camera, industrial camera, it is widely used in all trades and professions.Particularly in industrial processes, considerable production
Line controls by image, monitors production procedure, realizes the production automation, and the quality of production of high-quality.
And image real time transfer is the indispensable function of many vision facilities, most vision facilities is by high performance
Processor realizes the processing function of view data, so require inside vision facilities after obtain image by view data by
The mode specified is to efficiently transmit processor module.
Because conventional images resolution ratio has exceeded the resolution ratio of image algorithm requirement, to consider the processing pressure of processor,
Often require that image resolution ratio sampling to reduce the image processing data amount at processor end.
The content of the invention
It is an object of the invention to provide the cache logic framework and method for being applied to image contract in FPGA, in FPGA
Design carries out the caching method suitable for image contract suitable for the cache logic framework of image contract and with this framework, completes figure
Image sampling point extract function as required in equipment, while bandwidth chahnel is not reduced, vision facilities processing pressure is reduced, but
The performance of final output image quality is not reduced.
The present invention is achieved through the following technical solutions：It is applied to the cache logic framework of image contract in FPGA, including
One group of Block RAM for being configured to twoport pattern in FPGA, realize that image write-in logical sum image reads logic；The Block
RAM completes view data caching；Described image write-in logic realization view data is by specific format deposit Block RAM；It is described
Image reads logic realization and presses set image output mode, is read from Block RAM with particular order and figure of resequencing
As data, and export reordered view data, in FPGA design suitable for image contract cache logic framework and
The caching method suitable for image contract is carried out with this framework, the image sampling point required in vision facilities is completed and extracts work(
Can, while bandwidth chahnel is not reduced, vision facilities processing pressure is reduced, but do not reduce the performance of final output image quality.
Further, the logical architecture, the Block RAM are at least two pieces to better implement the present invention.
Further, the logical architecture, the view data of described image write-in logic are write to better implement the present invention
It is equal with the view data reading bandwidth of image reading logic to enter bandwidth.
It is applied to the cache logic method of image contract in FPGA, at least two pieces are configured inside FPGA has twoport pattern
Block RAM, for completing view data caching, realize that image write-in logical sum image reads logic；Described image writes
Logic completes view data by specific format deposit Block RAM operations；Described image, which reads logic, includes output full resolution
Image step, the output full resolution image step specifically include following steps：
A, from odd samples point source Block RAM and read N number of odd number respectively in even number of samples point source Block RAM and adopt
Sampling point and N number of even number of samples point；
B, N number of odd samples point and N number of even number of samples point are merged into 2*N sampled point output；
C, two pieces of Block RAM reading address is added 1；
D, odd samples point source Block RAM and even number of samples point source Block RAM are exchanged.
Design is applied to the cache logic framework of image contract and is carried out being applied to image contract with this framework in FPGA
Caching method, complete the image sampling point extract function required in vision facilities, while do not reduce bandwidth chahnel, reduce figure
As equipment processing pressure, but the performance of final output image quality is not reduced.
Further, the logical method, described image read logic and also taken out including output to better implement the present invention
Point after image step, it is described output snap shot after image step specifically include following steps：
1）The starting reading address for setting one piece of Block RAM is 0, and it is 1 that one piece of Block RAM, which reads address, in addition；
2）Read N number of sample point data respectively from two pieces of Block RAM；
3）Data will be read goes split to be 2*N sample point data and export by suitable；
4）Two pieces of Block RAM address is added 2 respectively.
Further, the logical method, the specific format deposit Block RAM that press are grasped to better implement the present invention
Work comprises the following steps：
（1）2*N dot image datas are inputted into two pieces of Block RAM；
（2）Input image data is divided into N number of odd samples point and N number of even number of samples point in order；
（3）By in N number of odd samples point deposit odd number point target Block RAM, N number of even number of samples point is stored in even number point
In target Block RAM；
（4）Two pieces of Block RAM deposit address is added 1 respectively；
（5）Exchange odd number point target Block RAM and even number point target Block RAM.
Further, the logical method, the view data of described image write-in logic are write to better implement the present invention
It is equal with the view data reading bandwidth of image reading logic to enter bandwidth.
The present invention compared with prior art, has advantages below and beneficial effect：
（1）The present invention can complete image sampling point extract function required in vision facilities, while not reduce passage band
Width, vision facilities processing pressure is reduced, but do not reduce the performance of final output image quality.
（2）The present invention is using view data input and view data output bandwidth identical design method, effectively to realize
Raw image data is by extraction mode rearrangement write-in internal memory.
（3）The present invention realizes can be according to the image or the image of full resolution that configuration output sampled point extracts.
（4）In the use of the present invention, vision bandwidth keeps constant.
（5）Logic of the present invention is simple, and higher performance can be achieved on FPGA.
Brief description of the drawings
Fig. 1 is the schematic flow sheet that image of the present invention writes logical operation.
Fig. 2 is the schematic flow sheet of output full resolution image step of the present invention.
Fig. 3 be it is of the present invention output snap shot after image step schematic flow sheet.
Fig. 4 is the cache logic block architecture diagram for being applied to image contract in FPGA of the present invention.
Embodiment
The applicant identifies oneself technician in technical field and combines existing known technology, and according to present specification
Content i.e. can be achieved the present invention.
The present invention is described in further detail with reference to embodiment, but the implementation of the present invention is not limited to this.
Embodiment 1：
It is applied to the cache logic framework of image contract in FPGA, as shown in figure 4, being configured to twoport including one group in FPGA
The Block RAM of pattern, realize that image write-in logical sum image reads logic；The Block RAM complete view data caching；
Described image write-in logic realization view data is by specific format deposit Block RAM；Described image reads logic realization and presses institute
Image output mode is set, read from Block RAM with particular order and view data of resequencing, and output through arranging again
The view data of sequence.
Image writes logic, is that view data is stored in into Block RAM by the arrangement mode of design requirement, completes picture number
According to caching.After view data caches, that is, the output of view data is carried out, now reading logic using image completes,
Image read logic processing procedure be：Read and view data of resequencing, and exported with particular order from Block RAM
Reordered view data, the image output after full resolution image output and snap shot will be divided into during output as desired
（The point class image of the sampling of output 1/2）, while will not also reduce bandwidth chahnel when exporting, in FPGA design be applied to image
The cache logic framework of extraction and the caching method for this framework be applied to image contract, are completed required in vision facilities
Image sampling point extract function, while do not reduce bandwidth chahnel, reduce vision facilities processing pressure, but do not reduce final defeated
Go out the performance of picture quality.
Embodiment 2：
The present embodiment is further optimized on the basis of above-described embodiment, further, to better implement the present invention
The logical architecture, as shown in figure 4, the Block RAM are at least two pieces, one of is BUFF # A, and another piece is
BUFF # B。
Image writes logic, is that view data is stored in into Block RAM by the arrangement mode of design requirement, completes picture number
According to caching.In the process of caching of view data, view data is divided into the packet input of multiple fixed bit wides, when receiving
First packet, BUFF # A input logic take out the sampled data deposit BUFF # A of odd point in packet；Meanwhile
BUFF #B input logic takes out the sampled data deposit BUFF # B of even number point in packet.And receive second data
Bao Shi, BUFF # A input logic take out the sampled data deposit BUFF # A of even number point in packet；Meanwhile BUFF # B
Input logic take out the sampled data deposit BUFF #B of odd point in packet.So replace repeating query, finally, BUFF successively
Data in # A are odd even odd even odd-even alternation data, opposite, the data in BUFF # B are very alternate for even odd even odd even
Data.
After view data caches, that is, the output of view data is carried out, now reading logic using image completes, figure
As the processing procedure for reading logic is：Read from Block RAM with particular order and view data of resequencing, and export warp
The view data of rearrangement, the image output after full resolution image output and snap shot will be divided into during output as desired（It is defeated
Go out the point class image of 1/2 sampling）, while bandwidth chahnel will not be also reduced when exporting.
When full resolution image exports, while cached from 2（BUFF # A and BUFF # B）First position take out
The data that data, wherein BUFF # A are taken out correspond to odd point, and the data that BUFF # B take out correspond to even number point, by 2
Data parity cross-combining exports.Simultaneously by 2 cachings（BUFF # A and BUFF # B）Address on current address be incremented by
1, circulate this mode for taking out data and data are taken out from caching, complete full resolution image output.
Image output after snap shot（The point class image of the sampling of output 1/2）When, while from BUFF # A first position
Data are taken out with BUFF # B second position, the data that wherein BUFF # A take out correspond to Part I odd point, BUFF
The data that # B take out correspond to Part I odd point.Simultaneously by 2 cachings（BUFF # A and BUFF # B）Address work as
It is incremented by 2 on preceding address, circulates this mode for taking out data and data are taken out from caching, completes the image output after snap shot.
Embodiment 3：
The present embodiment is further optimized on the basis of any of the above-described embodiment, further, preferably to realize this
The logical architecture is invented, the view data write-in bandwidth of described image write-in logic reads the view data reading of logic with image
It is equal to go out bandwidth.
Embodiment 4：
It is applied to the cache logic method of image contract in FPGA, at least two pieces are configured inside FPGA has twoport pattern
Block RAM, for completing view data caching, realize that image write-in logical sum image reads logic；Described image writes
Logic completes view data by specific format deposit Block RAM operations；Described image, which reads logic, includes output full resolution
Image step, the output full resolution image step specifically include following steps：
A, from odd samples point source Block RAM and read N number of odd number respectively in even number of samples point source Block RAM and adopt
Sampling point and N number of even number of samples point；
B, N number of odd samples point and N number of even number of samples point are merged into 2*N sampled point output；
C, two pieces of Block RAM reading address is added 1；
D, odd samples point source Block RAM and even number of samples point source Block RAM are exchanged.
Design is applied to the cache logic framework of image contract and is carried out being applied to image contract with this framework in FPGA
Caching method, complete the image sampling point extract function required in vision facilities, while do not reduce bandwidth chahnel, reduce figure
As equipment processing pressure, but the performance of final output image quality is not reduced.
Embodiment 5：
The present embodiment is further optimized on the basis of above-described embodiment, further, to better implement the present invention
The logical method, described image, which reads logic, also includes the image step after output snap shot, the image exported after snap shot
Step specifically includes following steps：
1）The starting reading address for setting one piece of Block RAM is 0, and it is 1 that one piece of Block RAM, which reads address, in addition；
2）Read N number of sample point data respectively from two pieces of Block RAM；
3）Data will be read goes split to be 2*N sample point data and export by suitable；
4）Two pieces of Block RAM address is added 2 respectively.
Embodiment 6：
The present embodiment is further optimized on the basis of embodiment 4 or 5, further, to better implement the present invention
The logical method, it is described to comprise the following steps by specific format deposit Block RAM operations：
（1）2*N dot image datas are inputted into two pieces of Block RAM；
（2）Input image data is divided into N number of odd samples point and N number of even number of samples point in order；
（3）By in N number of odd samples point deposit odd number point target Block RAM, N number of even number of samples point is stored in even number point
In target Block RAM；
（4）Two pieces of Block RAM deposit address is added 1 respectively；
（5）Exchange odd number point target Block RAM and even number point target Block RAM.
Embodiment 7：
The present embodiment is further optimized on the basis of embodiment 4, further, described to better implement the present invention
Logical method, the view data write-in bandwidth of described image write-in logic read the view data reading bandwidth phase of logic with image
Deng.
Embodiment 8：
The present embodiment is further optimized on the basis of any of the above-described embodiment, as shown in Figure 1,2,3, 4, is fitted in FPGA
For the cache logic framework and method of image contract, at least two pieces Block RAM with twoport pattern are configured in FPGA
（BUFF # A and BUFF # B）, for completing view data caching, realize that image write-in logical sum image reads logic；1/2
Down-sampled completion odd point output separates with the output of even number point, after image input, by corresponding configuration, obtains the complete of image respectively
Whole odd samples point and sampling even number of samples point, and Coutinuous store, into memory headroom, processor obtains wherein one secondary figure at random
As being handled and determining whether image meets condition.When condition meets, processor is by the odd samples point diagram and idol in internal memory
Number sampling point diagram pieces together a secondary full resolution image and preserved to hard disk.So far, realizing reduces vision facilities processing pressure,
But the performance of final output image quality is not reduced.
Concrete principle and step are as described below：
In the process of caching of view data, view data is divided into the packet input of multiple fixed bit wides, when receiving
First packet, BUFF # A input logic take out the sampled data deposit BUFF # A of odd point in packet；Meanwhile
BUFF #B input logic takes out the sampled data deposit BUFF # B of even number point in packet.And receive second data
Bao Shi, BUFF # A input logic take out the sampled data deposit BUFF # A of even number point in packet；Meanwhile BUFF # B
Input logic take out the sampled data deposit BUFF #B of odd point in packet.So replace repeating query, finally, BUFF successively
Data in # A are odd even odd even odd-even alternation data, opposite, the data in BUFF # B are very alternate for even odd even odd even
Data.
Wherein, " R Address ", represent to read address；" W Address ", represent write address；" 1/2 is down-sampled " module pair
Initial data carries out decimation；1 ' B1 represents logic 1；" Reorder " module is to reading data rearrangement；“1’B0 or
1 ' B1 " represents logic 1 or logical zero.
In the design, odd number（Or even number）Sample the same odd numbers of point source Block RAM（Or even number）Point target Block RAM
Data processing is carried out using same Block RAM, and odd samples point and even number of samples point are to use 2 pieces of Block in turn
RAM, odd point or the special one piece of Block RAM of even number point situation are not present in design.
As shown in figure 1, when the view data of first packet inputs, 2*N dot images are inputted into two pieces of Block RAM
Data, and N is natural number；The abstract segmentation of view data is completed afterwards, and input image data is divided into N number of odd samples point in order
With N number of even number of samples point；N number of odd number dot image data is stored in target area A（BUFF # A）, N number of even number dot image data deposits
Enter target area B（BUFF # B）；Then carry out buffer address to be incremented by, two pieces of Block RAM deposit address is added 1 respectively；
When the view data of second packet inputs, 2*N dot image datas are inputted into two pieces of Block RAM, and N is natural number；
The abstract segmentation of view data is completed afterwards, and input image data is divided into N number of odd samples point and N number of even number of samples point in order；N
Individual even number dot image data is stored in target area B（BUFF # B）, N number of odd number dot image data deposit target area A（BUFF #
A）；Then carry out buffer address to be incremented by, two pieces of Block RAM deposit address is added 1 respectively.
As shown in Fig. 2 during output full resolution image, it is divided into following steps：
A, caching A areas data from the sample survey is read, N number of odd samples point is read from odd samples point source Block RAM；Read
B areas data from the sample survey is cached, N number of even number of samples point is read from even number of samples point source Block RAM；
B, with ABAB ..., form splices data, and N number of odd samples point and N number of even number of samples point are merged into 2*N sampling
Point output；
C, buffer address is incremental, and two pieces of Block RAM reading address is added into 1；
D, odd samples point source Block RAM and even number of samples point source Block RAM are exchanged, carry out data output；
E, caching B areas data from the sample survey is read, N number of even number of samples point is read from even number of samples point source Block RAM；Read
A areas data from the sample survey is cached, N number of odd samples point is read from odd samples point source Block RAM；
F, with ABAB ..., form splices data, and N number of odd samples point and N number of even number of samples point are merged into 2*N sampling
Point output；
G, buffer address is incremental, and two pieces of Block RAM reading address is added into 1；
H, loop-around data exports, circular flow step a, b, c, d, e, f, g.
As shown in figure 3, when exporting the image after snap shot, it is divided into following steps：
One）Caching A areas are set（BUFF # A）Initial address is 0, sets caching B areas（BUFF # B）Initial address is 1；
Two）Caching A areas data from the sample survey is read, reads N number of sample point data；Caching B areas data from the sample survey is read, is read N number of
Sample point data；
Three）With ABAB ..., form splices data, will read data and go split to be 2*N sample point data and export by suitable；
Four）Buffer address is incremented by, and two pieces of Block RAM address is added into 2 respectively；
Five）Data output, circulation step one）, two）, three）, four）.
Present invention design in FPGA carries out being applied to figure suitable for the cache logic framework of image contract and with this framework
As the caching method extracted, the image sampling point extract function required in vision facilities is completed, while does not reduce bandwidth chahnel,
Vision facilities processing pressure is reduced, but does not reduce the performance of final output image quality.
It is described above, be only presently preferred embodiments of the present invention, any formal limitation not done to the present invention, it is every according to
Any simply modification, the equivalent variations made according to the technical spirit of the present invention to above example, each fall within the protection of the present invention
Within the scope of.
Claims (3)
- It is applied to the cache logic method of image contract in 1.FPGA, it is characterised in that：At least two pieces tools are configured inside FPGA There are the Block RAM of twoport pattern, for completing view data caching, realize that image write-in logical sum image reads logic；Institute State image write-in logic and complete view data by specific format deposit Block RAM operations；Described image reads logic including defeated Go out full resolution image step, the output full resolution image step specifically includes following steps：A, N number of odd samples point is read from odd samples point source Block RAM and in even number of samples point source Block RAM respectively With N number of even number of samples point；B, N number of odd samples point and N number of even number of samples point are merged into 2*N sampled point output；C, two pieces of Block RAM reading address is added 1；D, odd samples point source Block RAM and even number of samples point source Block RAM are exchanged；Described image read logic also include output snap shot after image step, it is described output snap shot after image step specifically wrap Include following steps：1）The starting reading address for setting one piece of Block RAM is 0, and it is 1 that one piece of Block RAM, which reads address, in addition；2）Read N number of sample point data respectively from two pieces of Block RAM；3）Data will be read goes split to be 2*N sample point data and export by suitable；4）Two pieces of Block RAM address is added 2 respectively.
- 2. it is applied to the cache logic method of image contract in FPGA according to claim 1, it is characterised in that：It is described to press Specific format deposit Block RAM operations comprise the following steps：（1）2*N dot image datas are inputted into two pieces of Block RAM；（2）Input image data is divided into N number of odd samples point and N number of even number of samples point in order；（3）By in N number of odd samples point deposit odd number point target Block RAM, N number of even number of samples point is stored in even number point target In Block RAM；（4）Two pieces of Block RAM deposit address is added 1 respectively；（5）Exchange odd number point target Block RAM and even number point target Block RAM.
- 3. it is applied to the cache logic method of image contract in FPGA according to claim 1, it is characterised in that：The figure As the view data write-in bandwidth of write-in logic is equal with the view data reading bandwidth of image reading logic.
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| CN105631888B (en) * | 2016-01-22 | 2019-12-13 | 上海厚安信息技术有限公司 | image data background removing processing system and method |
| CN107145457B (en) * | 2017-04-25 | 2019-10-29 | 电子科技大学 | The device and method of multichannel valid data transmission is promoted based on piece RAM |
| CN111610933A (en) * | 2020-05-22 | 2020-09-01 | 芯颖科技有限公司 | Data storage method, device and system based on dynamic update of RAM data |
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| US20030113031A1 (en) * | 1997-04-15 | 2003-06-19 | Wal Gooitzen Siemen Van Der | Parallel pipeline image processing system |
| CN102263884A (en) * | 2011-07-27 | 2011-11-30 | 中山大学 | Video image processor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030113031A1 (en) * | 1997-04-15 | 2003-06-19 | Wal Gooitzen Siemen Van Der | Parallel pipeline image processing system |
| CN102263884A (en) * | 2011-07-27 | 2011-11-30 | 中山大学 | Video image processor |
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