CN104581357A - Cache logic structure and method suitable for image extraction in FPGA - Google Patents
Cache logic structure and method suitable for image extraction in FPGA Download PDFInfo
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- CN104581357A CN104581357A CN201510015736.0A CN201510015736A CN104581357A CN 104581357 A CN104581357 A CN 104581357A CN 201510015736 A CN201510015736 A CN 201510015736A CN 104581357 A CN104581357 A CN 104581357A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/433—Content storage operation, e.g. storage operation in response to a pause request, caching operations
- H04N21/4331—Caching operations, e.g. of an advertisement for later insertion during playback
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
Abstract
The invention discloses a cache logic structure and method suitable for image extraction in FPGA. The cache logic structure and method suitable for the image extraction in the FPGA comprises the steps that image write logic and the image read logic are achieved through a group of double-port mode Block RAM in the FPGA; the Block RAM completes image data cache; the image data is saved in the Block ARM in a specific format through the image write logic; by means of the image read logic, image data is read in a specific order and reordered in the Block RAM according to the set image output mode, and the reordered image data is output; the method includes achieving the image write logic and the image read logic; the image read logic comprises outputting full resolution image steps. According to the cache logic structure and method suitable for the image extraction in the FPGA, image sampling point extraction function needed by an image device is completed without decreasing channel bandwidth, image device processing stress is decreased, and the performance of the quality of the images which are finally output is not lowered.
Description
Technical field
Patent of the present invention relates to image transmitting logic technology field in vision facilities, specifically, is the cache logic framework and the method that are applicable to image contract in FPGA.
Background technology
Vision facilities, be obtain image by imageing sensor and optical device, and carry out the equipment of respective image process, such as video camera, industrial camera, is widely used in all trades and professions.Particularly in industrial processes, considerable production line is controlled by image, is monitored production procedure, realizes the production automation, and the quality of production of high-quality.
And the image real time transfer function that to be many vision facilitiess indispensable, most vision facilities realizes the processing capacity of view data by high performance processor, so just requires that vision facilities is inner, after acquisition image, view data is transferred to processor module efficiently by the mode of specifying.
Because conventional images resolution has exceeded the resolution of image algorithm requirement, for considering the processing pressure of processor, often require image processing data amount image resolution ratio sampling being reduced processor end.
Summary of the invention
The object of the present invention is to provide in FPGA the cache logic framework and method that are applicable to image contract, in FPGA, design is applicable to the cache logic framework of image contract and carries out being applicable to the caching method of image contract with this framework, complete image sampling point extract function required in vision facilities, do not reduce bandwidth chahnel simultaneously, reduce vision facilities processing pressure, but do not reduce the performance of final output image quality.
The present invention is achieved through the following technical solutions: the cache logic framework being applicable to image contract in FPGA, comprises the Block RAM that an assembly in FPGA is set to twoport pattern, realizes image write logic and image reading logic; Described Block RAM completes view data buffer memory; Described image write logic realization view data presses specific format stored in Block RAM; Described image reads logic realization by set image output mode, read with particular order and view data of resequencing from Block RAM, and the view data exported through rearrangement, in FPGA, design is applicable to the cache logic framework of image contract and carries out being applicable to the caching method of image contract with this framework, complete image sampling point extract function required in vision facilities, do not reduce bandwidth chahnel simultaneously, reduce vision facilities processing pressure, but do not reduce the performance of final output image quality.
Further, described logical architecture to better implement the present invention, described Block RAM is at least two pieces.
Further, described logical architecture to better implement the present invention, the view data reading bandwidth that the view data write bandwidth of described image write logic reads logic with image is equal.
Being applicable to the cache logic method of image contract in FPGA, there is FPGA internal configurations at least two pieces the Block RAM of twoport pattern, for completing view data buffer memory, realizing image write logic and image reading logic; Described image write logic completes view data and operates stored in Block RAM by specific format; Described image reads logic and comprises output full resolution image step, and described output full resolution image step specifically comprises the following steps:
A, from odd samples point source Block RAM and in even number of samples point source Block RAM, read N number of odd samples point and N number of even number of samples point respectively;
B, N number of odd samples point and N number of even number of samples point be merged into 2*N sampled point and export;
C, the reading address of two pieces of Block RAM is added 1;
D, exchange odd samples point source Block RAM and even number of samples point source Block RAM.
In FPGA, design is applicable to the cache logic framework of image contract and carries out being applicable to the caching method of image contract with this framework, complete image sampling point extract function required in vision facilities, do not reduce bandwidth chahnel simultaneously, reduce vision facilities processing pressure, but do not reduce the performance of final output image quality.
Further, described logical method to better implement the present invention, described image reading logic also comprises exporting takes out the image step a little, and described output is taken out the image step a little and specifically comprised the following steps:
1) the initial reading address arranging one piece of Block RAM is 0, and it is 1 that other one piece of Block RAM reads address;
2) from two pieces of Block RAM, N number of sampling number certificate is read respectively;
3) split is gone to be 2*N sampling number certificate and to export by suitable sense data;
4) respectively the address of two pieces of Block RAM is added 2.
Further, described logical method to better implement the present invention, described by specific format stored in Block RAM operation comprise the following steps:
(1) in two pieces of Block RAM, 2*N dot image data is inputted;
(2) input image data is divided in order N number of odd samples point and N number of even number of samples point;
(3) by N number of odd samples point stored in odd point target Block RAM, by N number of even number of samples point stored in even number point target Block RAM;
(4) 1 is added by two pieces of Block RAM respectively stored in address;
(5) odd point target Block RAM and even number point target Block RAM is exchanged.
Further, described logical method to better implement the present invention, the view data reading bandwidth that the view data write bandwidth of described image write logic reads logic with image is equal.
The present invention compared with prior art, has the following advantages and beneficial effect:
(1) the present invention can complete image sampling point extract function required in vision facilities, does not reduce bandwidth chahnel simultaneously, reduces vision facilities processing pressure, but does not reduce the performance of final output image quality.
(2) the present invention adopts view data to input the design identical with view data output bandwidth, again arranges in write memory by extraction mode effectively to realize raw image data.
(3) present invention achieves and can export the image of sampled point extraction or the image of full resolution according to configuration.
(4) the present invention in use, and vision bandwidth remains unchanged.
(5) logic of the present invention is simple, and FPGA can realize higher performance.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of image of the present invention write logical operation.
Fig. 2 is the schematic flow sheet of output full resolution image step of the present invention.
Fig. 3 is the schematic flow sheet that the image step is a little taken out in output of the present invention.
Fig. 4 is the cache logic block architecture diagram being applicable to image contract in FPGA of the present invention.
Embodiment
The applicant to identify oneself in technical field technician in conjunction with existing known technology, and can realize the present invention according to the content disclosed in present specification.
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment 1:
Be applicable to the cache logic framework of image contract in FPGA, as shown in Figure 4, comprise the Block RAM that an assembly in FPGA is set to twoport pattern, realize image write logic and image reading logic; Described Block RAM completes view data buffer memory; Described image write logic realization view data presses specific format stored in Block RAM; Described image reads logic realization by set image output mode, reads and view data of resequencing from Block RAM with particular order, and exports the view data through rearrangement.
Image write logic, be by view data by the arrangement mode of designing requirement stored in Block RAM, complete the buffer memory of view data.After view data buffer memory, namely the output of view data is carried out, now utilize image to read logic to complete, the processing procedure that image reads logic is: read with particular order and view data of resequencing from Block RAM, and the view data exported through rearrangement, export being divided into according to demand full resolution image to export and taking out the image a little (the some class image exporting 1/2 sampling) during output, also bandwidth chahnel can not be reduced when exporting simultaneously, in FPGA, design is applicable to the cache logic framework of image contract and carries out being applicable to the caching method of image contract with this framework, complete image sampling point extract function required in vision facilities, do not reduce bandwidth chahnel simultaneously, reduce vision facilities processing pressure, but do not reduce the performance of final output image quality.
Embodiment 2:
The present embodiment is at the enterprising one-step optimization in the basis of above-described embodiment, and further, described logical architecture to better implement the present invention, as shown in Figure 4, described Block RAM is at least two pieces, and wherein one piece is BUFF # A, and another block is BUFF # B.
Image write logic, be by view data by the arrangement mode of designing requirement stored in Block RAM, complete the buffer memory of view data.In the process of caching of view data, view data is divided into the packet of multiple fixing bit wide to input, and when receiving first packet, the input logic of BUFF # A takes out the sampled data of odd point in packet stored in BUFF # A; Meanwhile, the input logic of BUFF #B takes out the sampled data of even number point in packet stored in BUFF # B.And when receiving second packet, the input logic of BUFF # A takes out the sampled data of even number point in packet stored in BUFF # A; Meanwhile, the input logic of BUFF # B takes out the sampled data of odd point in packet stored in BUFF #B.Alternately repeating query so successively, finally, the data in BUFF # A are odd even odd even odd-even alternation data, contrary, and the data in BUFF # B are the data that even odd even odd even very replaces.
After view data buffer memory, namely the output of view data is carried out, now utilize image to read logic to complete, the processing procedure that image reads logic is: read with particular order and view data of resequencing from Block RAM, and the view data exported through rearrangement, export being divided into according to demand full resolution image to export and taking out the image a little (the some class image exporting 1/2 sampling) during output, when exporting, also can not reduce bandwidth chahnel simultaneously.
When full resolution image exports, take out data from first position of 2 buffer memorys (BUFF # A and BUFF # B) simultaneously, the data that wherein BUFF # A takes out correspond to odd point, and the data that BUFF # B takes out correspond to even number point, 2 data odd-even interleavings are merged and export.The address of 2 buffer memorys (BUFF # A and BUFF # B) is increased progressively 1 on current address, this mode of taking out data that circulates takes out data from buffer memory, completes full resolution image and exports simultaneously.
When taking out the output of the image a little (exporting the some class image of 1/2 sampling), take out data from first position of BUFF # A and second position of BUFF # B simultaneously, the wherein corresponding Part I odd point of the data of BUFF # A taking-up, the data that BUFF # B takes out correspond to Part I odd point.The address of 2 buffer memorys (BUFF # A and BUFF # B) is increased progressively 2 on current address, this mode of taking out data that circulates takes out data from buffer memory, completes and takes out the output of the image a little simultaneously.
Embodiment 3:
The present embodiment is at the enterprising one-step optimization in the basis of above-mentioned any embodiment, and further, described logical architecture to better implement the present invention, the view data reading bandwidth that the view data write bandwidth of described image write logic reads logic with image is equal.
Embodiment 4:
Being applicable to the cache logic method of image contract in FPGA, there is FPGA internal configurations at least two pieces the Block RAM of twoport pattern, for completing view data buffer memory, realizing image write logic and image reading logic; Described image write logic completes view data and operates stored in Block RAM by specific format; Described image reads logic and comprises output full resolution image step, and described output full resolution image step specifically comprises the following steps:
A, from odd samples point source Block RAM and in even number of samples point source Block RAM, read N number of odd samples point and N number of even number of samples point respectively;
B, N number of odd samples point and N number of even number of samples point be merged into 2*N sampled point and export;
C, the reading address of two pieces of Block RAM is added 1;
D, exchange odd samples point source Block RAM and even number of samples point source Block RAM.
In FPGA, design is applicable to the cache logic framework of image contract and carries out being applicable to the caching method of image contract with this framework, complete image sampling point extract function required in vision facilities, do not reduce bandwidth chahnel simultaneously, reduce vision facilities processing pressure, but do not reduce the performance of final output image quality.
Embodiment 5:
The present embodiment is at the enterprising one-step optimization in the basis of above-described embodiment, further, described logical method to better implement the present invention, described image reading logic also comprises exporting takes out the image step a little, and described output is taken out the image step a little and specifically comprised the following steps:
1) the initial reading address arranging one piece of Block RAM is 0, and it is 1 that other one piece of Block RAM reads address;
2) from two pieces of Block RAM, N number of sampling number certificate is read respectively;
3) split is gone to be 2*N sampling number certificate and to export by suitable sense data;
4) respectively the address of two pieces of Block RAM is added 2.
Embodiment 6:
The present embodiment is the enterprising one-step optimization in basis in embodiment 4 or 5, further, described logical method to better implement the present invention, described by specific format stored in Block RAM operation comprise the following steps:
(1) in two pieces of Block RAM, 2*N dot image data is inputted;
(2) input image data is divided in order N number of odd samples point and N number of even number of samples point;
(3) by N number of odd samples point stored in odd point target Block RAM, by N number of even number of samples point stored in even number point target Block RAM;
(4) 1 is added by two pieces of Block RAM respectively stored in address;
(5) odd point target Block RAM and even number point target Block RAM is exchanged.
Embodiment 7:
The present embodiment is at the enterprising one-step optimization in the basis of embodiment 4, and further, described logical method to better implement the present invention, the view data reading bandwidth that the view data write bandwidth of described image write logic reads logic with image is equal.
Embodiment 8:
The present embodiment is at the enterprising one-step optimization in the basis of above-mentioned any embodiment, as shown in Figure 1,2,3, 4, cache logic framework and the method for image contract is applicable in FPGA, Block RAM(BUFF # A and BUFF # B that at least two pieces have twoport pattern is configured) in FPGA, for completing view data buffer memory, realize image write logic and image reading logic; The 1/2 down-sampled odd point that completes exports to export with even number point and is separated, after image input, pass through corresponding configuration, obtain complete odd samples point and the sampling even number of samples point of image respectively, and Coutinuous store is in memory headroom, processor obtains a wherein sub-picture at random and carries out processing and determine whether image satisfies condition.When condition meets, the odd samples point diagram in internal memory and even number of samples point diagram are pieced together a secondary full resolution image and are saved to hard disk by processor.So far, achieve and reduce vision facilities processing pressure, but do not reduce the performance of final output image quality.
Concrete principle and step as described below:
In the process of caching of view data, view data is divided into the packet of multiple fixing bit wide to input, and when receiving first packet, the input logic of BUFF # A takes out the sampled data of odd point in packet stored in BUFF # A; Meanwhile, the input logic of BUFF #B takes out the sampled data of even number point in packet stored in BUFF # B.And when receiving second packet, the input logic of BUFF # A takes out the sampled data of even number point in packet stored in BUFF # A; Meanwhile, the input logic of BUFF # B takes out the sampled data of odd point in packet stored in BUFF #B.Alternately repeating query so successively, finally, the data in BUFF # A are odd even odd even odd-even alternation data, contrary, and the data in BUFF # B are the data that even odd even odd even very replaces.
Wherein, " R Address ", represents and reads address; " W Address ", represents write address; " 1/2 is down-sampled " module carries out decimation to initial data; 1 ' B1 presentation logic 1; " Reorder " module is resequenced to sense data; " 1 ' B0 or 1 ' B1 " presentation logic 1 or logical zero.
In the design, odd number (or even number) point source Block RAM same odd number (or even number) the point target Block RAM that samples adopts same Block RAM to carry out data processing, and odd samples point and even number of samples point use 2 pieces of Block RAM in turn, in design, there is not the situation of odd point or the special one piece of Block RAM of even number point.
As shown in Figure 1, when the view data of first packet inputs, in two pieces of Block RAM, input 2*N dot image data, and N is natural number; After complete the abstract segmentation of view data, input image data is divided in order N number of odd samples point and N number of even number of samples point; N number of odd point view data is stored in target area A(BUFF # A), N number of even number dot image data is stored in target area B(BUFF # B); Then carry out buffer address to increase progressively, two pieces of Block RAM are added 1 respectively stored in address; When the view data of second packet inputs, in two pieces of Block RAM, input 2*N dot image data, and N is natural number; After complete the abstract segmentation of view data, input image data is divided in order N number of odd samples point and N number of even number of samples point; N number of even number dot image data is stored in target area B(BUFF # B), N number of odd point view data is stored in target area A(BUFF # A); Then carry out buffer address to increase progressively, two pieces of Block RAM are added 1 respectively stored in address.
As shown in Figure 2, when exporting full resolution image, following steps are divided into:
A, reading buffer memory A district data from the sample survey, read N number of odd samples point from odd samples point source Block RAM; Read buffer memory B district data from the sample survey, from even number of samples point source Block RAM, read N number of even number of samples point;
B, with ABAB ... form splicing data, are merged into 2*N sampled point and export by N number of odd samples point and N number of even number of samples point;
C, buffer address increase progressively, and the reading address of two pieces of Block RAM is added 1;
D, exchange odd samples point source Block RAM and even number of samples point source Block RAM, carry out data output;
E, reading buffer memory B district data from the sample survey, read N number of even number of samples point from even number of samples point source Block RAM; Read buffer memory A district data from the sample survey, from odd samples point source Block RAM, read N number of odd samples point;
F, with ABAB ... form splicing data, are merged into 2*N sampled point and export by N number of odd samples point and N number of even number of samples point;
G, buffer address increase progressively, and the reading address of two pieces of Block RAM is added 1;
H, loop-around data export, circular flow step a, b, c, d, e, f, g.
As shown in Figure 3, when the image is a little taken out in output, following steps are divided into:
One) arranging buffer memory A district (BUFF # A) initial address is 0, and arranging buffer memory B district (BUFF # B) initial address is 1;
Two) read buffer memory A district data from the sample survey, read N number of sampling number certificate; Read buffer memory B district data from the sample survey, read N number of sampling number certificate;
Three) with ABAB ... form splicing data, go split be 2*N sampling number certificate and export by suitable sense data;
Four) buffer address increases progressively, and respectively the address of two pieces of Block RAM is added 2;
Five) data export, circulation step one), two), three), four).
The present invention designs the cache logic framework being applicable to image contract and the caching method carrying out being applicable to image contract with this framework in FPGA, complete image sampling point extract function required in vision facilities, do not reduce bandwidth chahnel simultaneously, reduce vision facilities processing pressure, but do not reduce the performance of final output image quality.
The above is only preferred embodiment of the present invention, and not do any pro forma restriction to the present invention, every any simple modification, equivalent variations done above embodiment according to technical spirit of the present invention, all falls within protection scope of the present invention.
Claims (7)
- Be applicable to the cache logic framework of image contract in 1.FPGA, it is characterized in that: comprise the Block RAM that an assembly in FPGA is set to twoport pattern, realize image write logic and image reading logic; Described Block RAM completes view data buffer memory; Described image write logic realization view data presses specific format stored in Block RAM; Described image reads logic realization by set image output mode, reads and view data of resequencing from Block RAM with particular order, and exports the view data through rearrangement.
- 2. be applicable to the cache logic framework of image contract in FPGA according to claim 1, it is characterized in that: described Block RAM is at least two pieces.
- 3. be applicable to the cache logic framework of image contract in FPGA according to claim 1 and 2, it is characterized in that: the view data reading bandwidth that the view data write bandwidth of described image write logic reads logic with image is equal.
- 4.FPGA be inside applicable to the cache logic method of image contract, it is characterized in that: the Block RAM FPGA internal configurations at least two pieces with twoport pattern, for completing view data buffer memory, realizing image write logic and image reading logic; Described image write logic completes view data and operates stored in Block RAM by specific format; Described image reads logic and comprises output full resolution image step, and described output full resolution image step specifically comprises the following steps:A, from odd samples point source Block RAM and in even number of samples point source Block RAM, read N number of odd samples point and N number of even number of samples point respectively;B, N number of odd samples point and N number of even number of samples point be merged into 2*N sampled point and export;C, the reading address of two pieces of Block RAM is added 1;D, exchange odd samples point source Block RAM and even number of samples point source Block RAM.
- 5. be applicable to the cache logic method of image contract in FPGA according to claim 4, it is characterized in that: described image reading logic also comprises exporting takes out the image step a little, and described output is taken out the image step a little and specifically comprised the following steps:1) the initial reading address arranging one piece of Block RAM is 0, and it is 1 that other one piece of Block RAM reads address;2) from two pieces of Block RAM, N number of sampling number certificate is read respectively;3) split is gone to be 2*N sampling number certificate and to export by suitable sense data;4) respectively the address of two pieces of Block RAM is added 2.
- 6. be applicable to the cache logic method of image contract in the FPGA according to claim 4 or 5, it is characterized in that: described by specific format stored in Block RAM operation comprise the following steps:(1) in two pieces of Block RAM, 2*N dot image data is inputted;(2) input image data is divided in order N number of odd samples point and N number of even number of samples point;(3) by N number of odd samples point stored in odd point target Block RAM, by N number of even number of samples point stored in even number point target Block RAM;(4) 1 is added by two pieces of Block RAM respectively stored in address;(5) odd point target Block RAM and even number point target Block RAM is exchanged.
- 7. be applicable to the cache logic framework of image contract in FPGA according to claim 4, it is characterized in that: the view data reading bandwidth that the view data write bandwidth of described image write logic reads logic with image is equal.
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| CN105611261A (en) * | 2015-12-25 | 2016-05-25 | 北京小鸟科技发展有限责任公司 | Projection method and device based on video buffer and projector |
| CN105631888A (en) * | 2016-01-22 | 2016-06-01 | 上海厚安信息技术有限公司 | Image data background removing processing system and image data background removing processing method |
| CN107145457A (en) * | 2017-04-25 | 2017-09-08 | 电子科技大学 | The device and method of multichannel valid data transmission is lifted based on RAM on piece |
| CN111610933A (en) * | 2020-05-22 | 2020-09-01 | 芯颖科技有限公司 | Data storage method, device and system based on dynamic update of RAM data |
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| US20030113031A1 (en) * | 1997-04-15 | 2003-06-19 | Wal Gooitzen Siemen Van Der | Parallel pipeline image processing system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105611261A (en) * | 2015-12-25 | 2016-05-25 | 北京小鸟科技发展有限责任公司 | Projection method and device based on video buffer and projector |
| CN105631888A (en) * | 2016-01-22 | 2016-06-01 | 上海厚安信息技术有限公司 | Image data background removing processing system and image data background removing processing method |
| CN105631888B (en) * | 2016-01-22 | 2019-12-13 | 上海厚安信息技术有限公司 | image data background removing processing system and method |
| CN107145457A (en) * | 2017-04-25 | 2017-09-08 | 电子科技大学 | The device and method of multichannel valid data transmission is lifted based on RAM on piece |
| CN111610933A (en) * | 2020-05-22 | 2020-09-01 | 芯颖科技有限公司 | Data storage method, device and system based on dynamic update of RAM data |
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