CN104681075B - Storage arrangement and its operating method - Google Patents
Storage arrangement and its operating method Download PDFInfo
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- CN104681075B CN104681075B CN201310624074.8A CN201310624074A CN104681075B CN 104681075 B CN104681075 B CN 104681075B CN 201310624074 A CN201310624074 A CN 201310624074A CN 104681075 B CN104681075 B CN 104681075B
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Abstract
The invention discloses a kind of storage arrangement and its operating method, the operating method of storage arrangement comprises the following steps：Frequency signal is produced, wherein frequency signal includes multiple pulses；Transmit control command and data address；According to the rising edge and falling edge of multiple pulses in frequency signal, control command and data address are captured；According to control command and the memory in data address access storage arrangement.
Description
Technical field
There are double transmission the invention relates to a kind of storage arrangement and its operating method, and in particular to one kind
The storage arrangement of speed and its operating method.
Background technology
In recent years, consumption electronic products (such as：Intelligent mobile phone, tablet PC, digital camera ... etc.) it is quick
Development so that manufacturer also rapidly increases for the demand of storage arrangement.Operationally, storage arrangement is big except that can provide
Beyond the data storage of amount, the transmission speed of storage arrangement will also influence the overall operation of electronic product with read performance.Change
Yan Zhi, storage arrangement have turned into a critical elements in electronic product.Therefore, the transmission speed of storage arrangement how is lifted
Degree or read performance, have been the important topic of storage arrangement in design.
The content of the invention
The present invention provides a kind of storage arrangement and its operating method, is captured using the two edges of the pulse of frequency signal
Control command and data address, and then help to lift the transmission speed and read performance of storage arrangement.
The storage arrangement of the present invention, including memory, frequency generator and controller；Frequency generator is produced including more
The frequency signal of individual pulse；Storage arrangement transmits control command and data address to controller.In addition, controller is according to frequency
The rising edge of multiple pulses in signal captures control command and data address with falling edge, and according to control command and data
Location accesses memory.
On the other hand, the operating method of storage arrangement of the invention comprises the following steps：Produce frequency signal, its intermediate frequency
Rate signal includes multiple pulses；Transmit control command and data address；According to multiple pulses in frequency signal rising edge with
Falling edge, capture control command and data address；According to control command and the memory in data address access storage arrangement.
Based on above-mentioned, the present invention captures control command and data address using the two edges of the pulse of frequency signal, by
This, storage arrangement can transmit control command and data address using double transmission rates, and then help to lift its transmission
Speed and read performance.
For features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Brief description of the drawings
Fig. 1 is the schematic diagram of the storage arrangement according to one embodiment of the invention.
Fig. 2 is the flow chart of the storage arrangement according to one embodiment of the invention.
Fig. 3 is the flow chart of the storage arrangement according to another embodiment of the present invention.
Fig. 4 is illustrating the signal timing diagram of storage arrangement according to one embodiment of the invention.
Fig. 5 is the flow chart of the storage arrangement according to another embodiment of the present invention.
Fig. 6 is illustrating the signal timing diagram of storage arrangement according to another embodiment of the present invention.
【Symbol description】
100：Storage arrangement
110：Memory
120：Frequency generator
130：Controller
140~160：Pin
CSB：Chip select signal
SI/SIO0：The signal that pin 150 is transmitted
SO/SIO1：The signal that pin 160 is transmitted
SCLK：Frequency signal
S210~S240：To illustrate each step of Fig. 2 embodiments
S310、S320：The step of further to illustrate Fig. 3 embodiments
P1~P31：Pulse
CM4：Control command
AD4：Data address
DT4：Memory data
S510~S540：The step of further to illustrate Fig. 5 embodiments
CM41、CM42：The position group of control command
AD41、AD42：The position group of data address
DT41、DT42：The position group of memory data
Embodiment
Fig. 1 is the schematic diagram of the storage arrangement according to one embodiment of the invention.Reference picture 1, storage arrangement 100 include
Memory 110, frequency generator 120 and controller 130, and storage arrangement 100 has multiple pins 140~160.Wherein,
Frequency generator 120 is electrically connected to controller 130, and controller 130 is electrically connected at pin 140~160 and memory 110
Between.
In addition, the pin 140 of storage arrangement 100 is transmitting chip select signal CSB.Wherein, controller 130 can be according to
Enable pattern or forbidden energy pattern are switched to according to chip select signal CSB level.In addition, the pin 150 of storage arrangement 100
For an input/output end port of storage arrangement 100, and to transmit signal SI/SIO0.Similarly, storage arrangement 100
Pin 160 is another input/output end port of storage arrangement 100, and to transmit signal SO/SIO1.Wherein, described letter
Number SI/SIO0 and signal SO/SIO1 can be such as including control command, data address, memory data ....
Fig. 2 is the flow chart of the storage arrangement according to one embodiment of the invention.Below referring to Fig. 1
With Fig. 2.As shown in step S210, frequency generator 120 is producing a frequency signal SCLK.As shown in step S220, storage
Device device 100 can pass through an at least pin and transmit a control command and a data address.That is, storage arrangement 100 can use
The mode of serial transmission is linked up with external device (ED).In addition, as shown in step S230, controller 130 can be according to frequency signal
The rising edge of multiple pulses in SCLK captures control command and data address with falling edge.
Furthermore as shown in step S240, controller 130 will access memory 110 according to control command and data address.
For example, controller 130 can determine to carry out memory 110 specific operation according to control command, such as：Read operation, write
Enter operation ... etc..In addition, controller 130 can choose the memory block in memory 110 according to data address, and then to depositing
The memory block in reservoir 110 carries out the specific operation.For example, controller 130 can be determined to depositing according to control command
Reservoir 110 is read, and then reads out a memory number from the memory block in memory 110 according to data address
According to.In addition, controller 130 can also determine to carry out write operation to memory 110 according to control command, and then according to data
Location writes a data to a memory block of memory 110.
It is noted that be directed to control command and data address, controller 130 be all using pulse two edges (also
That is, rising edge and falling edge) captured.Consequently, it is possible to for the transmission of control command and data address, storage arrangement
100 are all up double transmission rates (double transfer rate), and then help to be lifted its transmission speed with reading effect
Energy.In addition, the switching of the input and output mode with storage arrangement 100, controller 130 also captures using single individual pulse
More than two address bits in more than two command bits or data address into control command, and then can be further
Lift the transmission speed and read performance of storage arrangement 100.
For example, Fig. 3 is the flow chart of the storage arrangement according to another embodiment of the present invention.Fig. 4 is
According to one embodiment of the invention illustrating the signal timing diagram of storage arrangement.Below referring to Fig. 1, Fig. 3 and figure
4。
In one embodiment, storage arrangement 100 can switch to a substance input and output mode.Now, controlled in transmission
In the thin portion flow of order and data address (step S220), as shown in step S310, storage arrangement 100 will transmit through a pin
(such as：Pin 150) sequentially transmit multiple command bits in control command and multiple address bits in data address.In addition,
Capture control command and in the thin portion flow of data address (step S230), as shown in step S320, controller 130 will utilize every
The rising edge and falling edge of one pulse, capture two in two command bits or the multiple address bit in the multiple command bit
Address bit.
For example, in Fig. 4 embodiments, frequency signal SCLK includes pulse P1~P31, and control command CM4 includes 8 lives
Position is made, data address AD4 includes 24 address bits.Operationally, when chip select signal CSB switches to low level, control
Device 130 will switch to enable pattern, and start to capture control command CM4 and data address AD4.Wherein, controller 130 utilizes arteries and veins
Rush P1 and capture the 1st to the 2nd command bit in control command CM4, and using pulse P2 capture in control command CM4 the 3rd to
4th command bit.By that analogy, controller 130 must only utilize 4 pulse P1~P4 with regard to fechtable to having 8 command bits
Control command CM4.
When capture arrive control command CM4 after, controller 130 will then acquisition data address AD 4.Wherein, controller 130
Using the 1st to the 2nd address bit in pulse P5 acquisition datas address AD 4, and using in pulse P6 acquisition datas address AD 4
3rd to the 4th address bit.By that analogy, controller 130 must only utilize 12 pulse P5~P16 with regard to fechtable to 24
The data address AD4 of address bit.
In other words, when storage arrangement 100 switches to substance input and output mode, controller 130 will utilize each
Pulse captures two command bits or two address bits, and then helps to lift the transmission speed of storage arrangement 100.In addition,
In Fig. 4 embodiments, controller 130 can determine to be read memory 110, Jin Ercan according to control command CM4
A memory data DT4 is read out from memory 110 according to data address AD4.Furthermore controller 130 can utilize multiple pulses
The rising edge of (for example, pulse P24~P31) transmits memory data DT4 with falling edge.That is, storage arrangement 100 also may be used
Memory data DT4 is transmitted using double transmission rates.
The pin 160 that memory data DT4 can pass through storage arrangement 100 is sent to external device (ED).In addition, in data
With exporting, storage arrangement 100 can be separated by an interregnum for input.For example, as shown in figure 4, received through pin 150
After control command CM4 and data address AD4, one as long as 8 pulse P17~P24 to be included such as meeting of storage arrangement 100 is empty
During white and then through the output storage data DT4 of pin 160.Wherein, the length of interregnum is to depend on memory device
Put 100 reading frequency.In addition, in practical application, storage arrangement 100 also can followed by export number having received data
According to, and interregnum need not be defined.
Fig. 5 is the flow chart of the storage arrangement according to another embodiment of the present invention.Fig. 6 is according to the present invention
Another embodiment illustrating the signal timing diagram of storage arrangement.Below referring to Fig. 1, Fig. 5 and Fig. 6.
In one embodiment, storage arrangement 100 more can switch to a dual input and output mode.Now, controlled in transmission
In the thin portion flow of system order and data address (step S220), as shown in step S510 and S520, storage arrangement 100 will be saturating
Cross the first pin (such as：Pin 150) sequentially transmit control command in multiple first command bits with it is multiple in data address
First address bit, and the second pin of transmission (such as：Pin 160) sequentially transmit control command in multiple second command bits and number
According to multiple second address bits in address.
In addition, described multiple pulses include multiple command pulses and multiple address pulses.Capturing control command and number
According in the thin portion flow of address (step S230), as shown in step S530 and S540, controller 130 will utilize each command pulse
Rising edge and falling edge, capture two first command bits in the multiple first command bit with the multiple second command bit
Two second command bits, and using the rising edge and falling edge of each address pulse, capture in the multiple first address bit
Two first address bits and two second address bits in the multiple second address bit.
For example, in Fig. 6 embodiments, pulse P1~P2 in frequency signal SCLK can be considered multiple command pulses, and arteries and veins
Rush P3~P8 and can be considered multiple address pulses.In addition, in figure 6, the control command CM4 with 8 command bits is divided into two
Ge Wei groups CM41 and CM42, and position group CM41 and CM42 each includes 4 command bits.Furthermore in figure 6, there are 24
The data address AD4 of address bit is divided into Liang Gewei groups AD41 and AD42, and position group AD41 and AD42 each includes 12
Individual address bit.
Operationally, controller 130 can utilize pulse P1 (that is, command pulse P1) to capture the in the group CM41 of position the 1st
The 1st to 2 command bit into 2 command bits and position group CM42.In addition, controller 130 more using pulse P2 (that is,
Command pulse P2) capture the 3rd to 4 command bit in the group CM41 of position and the 3rd to 4 command bit in position group CM42.
In other words, under dual input and output mode, controller 130 must only utilize 2 pulse P1 and P2 with regard to fechtable to 8 lives
Make the control command CM4 of position.
On the other hand, controller 130 captures the 1st to 2 in the group AD41 of position using pulse P3 (that is, address pulse P3)
The 1st to 2 address bit in individual address bit and position group AD42.In addition, controller 130 can utilize pulse P4 (that is, addresses
Pulse P4) capture position group AD41 in the 3rd to 4 address bit and position group AD42 in the 3rd to 4 address bit.With this
Analogize, controller 130 must only utilize 6 pulse P3~P8 with regard to fechtable to the data address AD4 with 24 address bits.
In other words, when storage arrangement 100 switches to dual input and output mode, controller 130 will utilize each
Pulse captures four command bits or four address bits, and then helps to lift the transmission speed of storage arrangement 100.In addition,
In Fig. 6 embodiments, controller 130 can read out memory data DT4 according to control command CM4 from memory 110, its
Middle memory data DT4 is divided into Liang Gewei groups DT41 and DT42.Furthermore controller 130 can be according to multiple pulse (examples
Such as, pulse P17~P23) carry out traffic bit group DT41 and DT42, and position group DT41 and DT42 can pass through storage arrangement 100
Two pins 150 and 160 be sent to external device (ED).
In summary, the present invention is to capture control command and data address using the two edges of the pulse of frequency signal.
Thereby, storage arrangement can transmit control command and data address using double transmission rates, and then help to lift its biography
Defeated speed and read performance.In addition, storage arrangement also its changeable input and output mode, and then can further be lifted
Its transmission speed and read performance.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any art
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, thus it is of the invention
Protection domain when being defined depending on what appended claims scope was defined.
Claims (10)
1. a kind of storage arrangement, including：
One memory；
One frequency generator, produce the frequency signal for including multiple pulses；And
One controller, the wherein storage arrangement transmit a control command with a data address to the controller, and the controller
Rising edge according to these pulses captures the control command and the data address with falling edge, and according to the control command and the number
According to the address access memory；
Wherein, the controller system using rising edge and the falling edge of single individual pulse capture into control command two or two with
On command bit or data address in two or more address bits.
2. storage arrangement according to claim 1, the wherein storage arrangement have a pin, and the pin to according to
Sequence transmits multiple command bits in the control command and multiple address bits in the data address.
3. storage arrangement according to claim 2, the wherein controller are using the rising edge of these each pulses with
Edge is dropped, captures two command bits in these command bits or the two-address position in these address bits.
4. there is one first pin to be connect with one second for storage arrangement according to claim 1, the wherein storage arrangement
Pin, and first pin is sequentially transmitting multiple the in multiple first command bits in the control command and the data address
One address bit, second pin are more in multiple second command bits in the control command and the data address sequentially to transmit
Individual second address bit.
5. storage arrangement according to claim 4, wherein these pulses include multiple command pulses and multiple address arteries and veins
Punching, the controller capture two first lives in these first command bits using the rising edge of these each command pulses with falling edge
Make two second command bits in position and these second command bits, and the controller using these each address pulses rising edge with
Falling edge, capture two first address bits in these first address bits and two second address bits in these second address bits.
6. a kind of operating method of storage arrangement, including：
A frequency signal is produced, wherein the frequency signal includes multiple pulses；
Transmit a control command and a data address；
According to the rising edge and falling edge of these pulses in the frequency signal, the control command and the data address are captured, its
Middle system using rising edge and the falling edge of single individual pulse capture into control command two or more command bits or
Two or more address bits in data address；And
According to the memory in the control command and the data address access storage arrangement.
7. the operating method of storage arrangement according to claim 6, wherein transmitting the control command and the data address
The step of include：
Through a pin of the storage arrangement, sequentially transmit in the multiple command bits and the data address in the control command
Multiple address bits.
8. the operating method of storage arrangement according to claim 7, wherein according to these pulses in the frequency signal
Rising edge and falling edge, capturing the control command and the step of data address includes：
Using the rising edge and falling edge of these each pulses, two command bits or these address bits in these command bits are captured
In two-address position.
9. the operating method of storage arrangement according to claim 6, wherein transmitting the control command and the data address
The step of include：
Through one first pin of the storage arrangement, multiple first command bits and the data in the control command are sequentially transmitted
Multiple first address bits in address；And
Through one second pin of the storage arrangement, multiple second command bits and the data in the control command are sequentially transmitted
Multiple second address bits in address.
10. the operating method of storage arrangement according to claim 9, wherein these pulses include multiple command pulses with
Multiple address pulses, and according to the rising edge and falling edge of these pulses in the frequency signal, the control command is captured with being somebody's turn to do
The step of data address, includes：
Using the rising edge and falling edge of these each command pulses, capture two first command bits in these first command bits with
Two second command bits in these second command bits；And
Using the rising edge and falling edge of these each address pulses, capture two first address bits in these first address bits with
Two second address bits in these second address bits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310624074.8A CN104681075B (en) | 2013-11-26 | 2013-11-26 | Storage arrangement and its operating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310624074.8A CN104681075B (en) | 2013-11-26 | 2013-11-26 | Storage arrangement and its operating method |
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| CN104681075A CN104681075A (en) | 2015-06-03 |
| CN104681075B true CN104681075B (en) | 2017-11-17 |
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| CN201310624074.8A Active CN104681075B (en) | 2013-11-26 | 2013-11-26 | Storage arrangement and its operating method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111784872B (en) * | 2020-06-30 | 2022-07-26 | 湖南中车时代通信信号有限公司 | Train multi-intersection operation data switching storage device of monitoring record plug-in |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW425546B (en) * | 1998-09-24 | 2001-03-11 | Fujitsu Ltd | Semiconductor memory device and method of controlling the same |
| TW490669B (en) * | 1999-12-16 | 2002-06-11 | Nippon Electric Co | Synchronous double data rate DRAM |
| CN101662448A (en) * | 2009-08-19 | 2010-03-03 | 东南大学 | Wireless communication method of high-speed sampling low-accuracy quantification impulse ultra-wideband |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4024972B2 (en) * | 1999-11-05 | 2007-12-19 | 松下電器産業株式会社 | Semiconductor memory device |
| US7071748B2 (en) * | 2004-04-26 | 2006-07-04 | Atmel Corporation | Charge pump clock for non-volatile memories |
| TWI323409B (en) * | 2006-09-08 | 2010-04-11 | Nanya Technology Corp | Apparatus and related method for controlling switch module in memory by detecting operating frequency of specific signal in memory |
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- 2013-11-26 CN CN201310624074.8A patent/CN104681075B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW425546B (en) * | 1998-09-24 | 2001-03-11 | Fujitsu Ltd | Semiconductor memory device and method of controlling the same |
| TW490669B (en) * | 1999-12-16 | 2002-06-11 | Nippon Electric Co | Synchronous double data rate DRAM |
| CN101662448A (en) * | 2009-08-19 | 2010-03-03 | 东南大学 | Wireless communication method of high-speed sampling low-accuracy quantification impulse ultra-wideband |
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| CN104681075A (en) | 2015-06-03 |
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