CN104681075A - Storage device and operation method thereof - Google Patents
Storage device and operation method thereof Download PDFInfo
- Publication number
- CN104681075A CN104681075A CN201310624074.8A CN201310624074A CN104681075A CN 104681075 A CN104681075 A CN 104681075A CN 201310624074 A CN201310624074 A CN 201310624074A CN 104681075 A CN104681075 A CN 104681075A
- Authority
- CN
- China
- Prior art keywords
- address
- command
- bits
- storage arrangement
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a storage device and an operation method thereof. The operation method comprises the following steps: generating a frequency signal, wherein the frequency signal comprises a plurality of pulses; transmitting a control command and a data address; capturing the control command and the data address according to rising edges and falling edges of the plurality of pulses in the frequency signal; and accessing a storage in the storage device according to the control command and the data address.
Description
Technical field
The invention relates to a kind of storage arrangement and its method of operating, and relate to a kind of storage arrangement and its method of operating with two transfer rate especially.
Background technology
In recent years, consumption electronic products (such as: intelligent mobile phone, flat computer, digital camera ... etc.) fast development, manufacturer is also increased rapidly for the demand of storage arrangement.Operationally, storage arrangement is except can providing a large amount of data storing, and the transmission speed of storage arrangement and read performance also will affect the overall operation of electronic product.In other words, storage arrangement has become a critical elements in electronic product.Therefore, how promoting transmission speed or the read performance of storage arrangement, has been a storage arrangement important topic in design.
Summary of the invention
The invention provides a kind of storage arrangement and its method of operating, utilize the two edges of the pulse of frequency signal to capture control command and data address, and then contribute to the transmission speed and the read performance that promote storage arrangement.
Storage arrangement of the present invention, comprises storer, frequency generator and controller; Frequency generator produces the frequency signal comprising multiple pulse; The order of storage arrangement transfer control and data address are to controller.In addition, rising edge and the falling edge of the multiple pulses in controller foundation frequency signal capture control command and data address, and according to control command and data address access storer.
On the other hand, the method for operating of storage arrangement of the present invention comprises the following steps: to produce frequency signal, and wherein frequency signal comprises multiple pulse; Transfer control order and data address; According to rising edge and the falling edge of the multiple pulses in frequency signal, acquisition control command and data address; According to the storer in control command and data address access storage arrangement.
Based on above-mentioned, the present invention utilizes the two edges of the pulse of frequency signal to capture control command and data address, by this, storage arrangement can utilize two transfer rate to come transfer control order and data address, and then contribute to promoting its transmission speed and read performance.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the storage arrangement according to one embodiment of the invention.
Fig. 2 is the flow chart of the storage arrangement according to one embodiment of the invention.
Fig. 3 is the flow chart of the storage arrangement according to another embodiment of the present invention.
Fig. 4 is the signal timing diagram in order to storage arrangement to be described according to one embodiment of the invention.
Fig. 5 is the flow chart of the storage arrangement according to another embodiment of the present invention.
Fig. 6 is the signal timing diagram in order to storage arrangement to be described according to another embodiment of the present invention.
[symbol description]
100: storage arrangement
110: storer
120: frequency generator
130: controller
140 ~ 160: pin
CSB: chip select signal
SI/SIO0: the signal that pin 150 transmits
SO/SIO1: the signal that pin 160 transmits
SCLK: frequency signal
S210 ~ S240: in order to each step of key diagram 2 embodiment
S310, S320: in order to the step of key diagram 3 embodiment further
P1 ~ P31: pulse
CM4: control command
AD4: data address
DT4: memory data
S510 ~ S540: in order to the step of key diagram 5 embodiment further
CM41, CM42: the position group of control command
AD41, AD42: the position group of data address
DT41, DT42: the position group of memory data
Embodiment
Fig. 1 is the schematic diagram of the storage arrangement according to one embodiment of the invention.With reference to Fig. 1, storage arrangement 100 comprises storer 110, frequency generator 120 and controller 130, and storage arrangement 100 has multiple pin 140 ~ 160.Wherein, frequency generator 120 is electrically connected to controller 130, and controller 130 is electrically connected between pin 140 ~ 160 and storer 110.
In addition, the pin 140 of storage arrangement 100 is in order to transmit chip select signal CSB.Wherein, controller 130 can switch to activation pattern or forbidden energy pattern according to the level of chip select signal CSB.In addition, the pin 150 of storage arrangement 100 is an input/output end port of storage arrangement 100, and in order to transmission signal SI/SIO0.Similarly, the pin 160 of storage arrangement 100 is another input/output end port of storage arrangement 100, and in order to transmission signal SO/SIO1.Wherein, described signal SI/SIO0 and signal SO/SIO1 can such as comprise control command, data address, memory data ... etc.
Fig. 2 is the flow chart of the storage arrangement according to one embodiment of the invention.Below referring to Fig. 1 and Fig. 2.As shown in step S210, frequency generator 120 is in order to produce a frequency signal SCLK.As shown in step S220, storage arrangement 100 can pass through at least one pin and transmits a control command and a data address.That is storage arrangement 100 can adopt the mode of serial transmission to link up with external device (ED).In addition, as shown in step S230, controller 130 can capture control command and data address according to the rising edge of the multiple pulses in frequency signal SCLK and falling edge.
Moreover as shown in step S240, controller 130 will carry out access memory 110 according to control command and data address.Such as, controller 130 can determine to carry out a specific operation to storer 110 according to control command, such as: read operation, write operation ... etc.In addition, controller 130 can choose the memory block in storer 110 according to data address, and then carries out described specific operation to this memory block in storer 110.Such as, controller 130 can determine according to control command to carry out read operation to storer 110, and then reads out a memory data according to data address from the memory block storer 110.In addition, controller 130 also can determine according to control command to carry out write operation to storer 110, and then one data is write to a memory block of storer 110 according to data address.
It is worth mentioning that, for control command and data address, controller 130 is all utilize the two edges (that is, rising edge and falling edge) of pulse to capture.Thus, for the transmission of control command and data address, storage arrangement 100 all can reach two transfer rate (double transfer rate), and then contributes to promoting its transmission speed and read performance.In addition, along with the switching of the input and output mode of storage arrangement 100, controller 130 also can utilize single pulse to capture in control command plural address bit in plural command bit or data address, and then further can promote transmission speed and the read performance of storage arrangement 100.
For example, Fig. 3 is the flow chart of the storage arrangement according to another embodiment of the present invention.Fig. 4 is the signal timing diagram in order to storage arrangement to be described according to one embodiment of the invention.Below referring to Fig. 1, Fig. 3 and Fig. 4.
In one embodiment, storage arrangement 100 can switch to a substance input and output mode.Now, in the thin portion flow process of transfer control order and data address (step S220), as shown in step S310, storage arrangement 100 will through the multiple command bit in a pin (such as: pin 150) sequentially transfer control order and the multiple address bits in data address.In addition, in the thin portion flow process capturing control command and data address (step S230), as shown in step S320, controller 130 will utilize rising edge and the falling edge of each pulse, capture two command bits in described multiple command bit or the position, two-address in described multiple address bit.
Such as, in Fig. 4 embodiment, frequency signal SCLK comprises pulse P1 ~ P31, and control command CM4 comprises 8 command bits, and data address AD4 comprises 24 address bits.Operationally, when chip select signal CSB switches to low level, controller 130 will switch to activation pattern, and start to capture control command CM4 and data address AD4.Wherein, controller 130 utilizes the 1st to the 2nd command bit in pulse P1 acquisition control command CM4, and utilizes the 3rd to the 4th command bit in pulse P2 acquisition control command CM4.By that analogy, controller 130 only must utilize 4 pulse P1 ~ P4 with regard to fechtable to the control command CM4 with 8 command bits.
After acquisition to control command CM4, then acquisition data address AD 4 incited somebody to action by controller 130.Wherein, controller 130 utilizes the 1st to the 2nd address bit in pulse P5 acquisition data address AD 4, and utilizes the 3rd to the 4th address bit in pulse P6 acquisition data address AD 4.By that analogy, controller 130 only must utilize 12 pulse P5 ~ P16 with regard to fechtable to the data address AD4 with 24 address bits.
In other words, when storage arrangement 100 switches to substance input and output mode, controller 130 will utilize each pulse to capture two command bits or two address bits, and then contribute to the transmission speed promoting storage arrangement 100.In addition, in Fig. 4 embodiment, controller 130 can determine to carry out read operation to storer 110 according to control command CM4, and then comparable data address AD 4 reads out a memory data DT4 from storer 110.Moreover controller 130 can utilize the rising edge of multiple pulse (such as, pulse P24 ~ P31) and falling edge to transmit memory data DT4.That is storage arrangement 100 also can utilize two transfer rate to transmit memory data DT4.
Memory data DT4 can be sent to external device (ED) through the pin 160 of storage arrangement 100.In addition, on the constrained input of data, storage arrangement 100 can be separated by an interregnum.Such as, as shown in Figure 4, after receiving control command CM4 and data address AD4 through pin 150, after an interregnum of 8 pulse P17 ~ P24 to be included such as storage arrangement 100 meeting, then through pin 160 output storage data DT4.Wherein, the length of interregnum is the reading frequency depending on storage arrangement 100.In addition, in practical application, storage arrangement 100 also then can export data after receiving data, and need not define interregnum.
Fig. 5 is the flow chart of the storage arrangement according to another embodiment of the present invention.Fig. 6 is the signal timing diagram in order to storage arrangement to be described according to another embodiment of the present invention.Below referring to Fig. 1, Fig. 5 and Fig. 6.
In one embodiment, storage arrangement 100 more can switch to a dual input and output mode.Now, in the thin portion flow process of transfer control order and data address (step S220), as shown in step S510 and S520, storage arrangement 100 will through multiple first command bit in the first pin (such as: pin 150) sequentially transfer control order and multiple first address bits in data address, and through multiple second command bit in the second pin (such as: pin 160) sequentially transfer control order and multiple second address bits in data address.
In addition, described multiple pulses comprise multiple command pulse and multiple address pulse.In the thin portion flow process capturing control command and data address (step S230), as shown in step S530 and S540, controller 130 will utilize rising edge and the falling edge of each command pulse, capture two first command bits in described multiple first command bit and two second command bits in described multiple second command bit, and utilize rising edge and the falling edge of each address pulse, capture two first address bits in described multiple first address bit and two second address bits in described multiple second address bit.
Such as, in Fig. 6 embodiment, the pulse P1 ~ P2 in frequency signal SCLK can be considered multiple command pulse, and pulse P3 ~ P8 can be considered multiple address pulse.In addition, in figure 6, the control command CM4 with 8 command bits is divided into Liang Gewei group CM41 and CM42, and position group CM41 and CM42 comprises 4 command bits separately.Moreover in figure 6, the data address AD4 with 24 address bits is divided into Liang Gewei group AD41 and AD42, and position group AD41 and AD42 comprises 12 address bits separately.
Operationally, controller 130 can utilize pulse P1 (that is, command pulse P1) to capture the 1 to 2 command bit in position group CM41 and the 1 to 2 command bit in position group CM42.In addition, controller 130 more utilizes pulse P2 (that is, command pulse P2) to capture the 3 to 4 command bit in position group CM41 and the 3 to 4 command bit in position group CM42.In other words, under dual input and output mode, controller 130 only must utilize 2 pulse P1 and P2 with regard to fechtable to the control command CM4 with 8 command bits.
On the other hand, controller 130 utilizes pulse P3 (that is, address pulse P3) to capture the 1 to 2 address bit in position group AD41 and the 1 to 2 address bit in position group AD42.In addition, controller 130 can utilize pulse P4 (that is, address pulse P4) to capture the 3 to 4 address bit in position group AD41 and the 3 to 4 address bit in position group AD42.By that analogy, controller 130 only must utilize 6 pulse P3 ~ P8 with regard to fechtable to the data address AD4 with 24 address bits.
In other words, when storage arrangement 100 switches to dual input and output mode, controller 130 will utilize each pulse to capture four command bits or four address bits, and then contribute to the transmission speed promoting storage arrangement 100.In addition, in Fig. 6 embodiment, controller 130 can read out memory data DT4 according to control command CM4 from storer 110, and wherein memory data DT4 is divided into Liang Gewei group DT41 and DT42.Moreover controller 130 can carry out traffic bit group DT41 and DT42 according to multiple pulse (such as, pulse P17 ~ P23), and position group DT41 and DT42 can be sent to external device (ED) through two pins 150 and 160 of storage arrangement 100.
In sum, the present invention utilizes the two edges of the pulse of frequency signal to capture control command and data address.By this, storage arrangement can utilize two transfer rate to come transfer control order and data address, and then contribute to promoting its transmission speed and read performance.In addition, storage arrangement is its input and output mode changeable also, and then can further promote its transmission speed and read performance.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.
Claims (10)
1. a storage arrangement, comprising:
One storer;
One frequency generator, produces the frequency signal comprising multiple pulse; And
One controller, wherein this storage arrangement transmits a control command and a data address to this controller, and this controller captures this control command and this data address according to the rising edge of these pulses and falling edge, and according to this control command and this storer of this data address access.
2. storage arrangement according to claim 1, wherein this storage arrangement has a pin, and this pin is in order to sequentially to transmit the multiple command bit in this control command and the multiple address bits in this data address.
3. storage arrangement according to claim 2, wherein this controller utilizes rising edge and the falling edge of each these pulse, captures two command bits in these command bits or the position, two-address in these address bits.
4. storage arrangement according to claim 1, wherein this storage arrangement has one first pin and one second pin, and this first pin is in order to sequentially to transmit multiple first command bit in this control command and multiple first address bits in this data address, this second pin is in order to sequentially to transmit multiple second command bit in this control command and multiple second address bits in this data address.
5. storage arrangement according to claim 4, wherein these pulses comprise multiple command pulse and multiple address pulse, this controller utilizes the rising edge of each these command pulse and falling edge to capture two first command bits in these first command bits and two second command bits in these the second command bits, and this controller utilizes rising edge and the falling edge of each these address pulse, capture two first address bits in these first address bits and two second address bits in these the second address bits.
6. a method of operating for storage arrangement, comprising:
Produce a frequency signal, wherein this frequency signal comprises multiple pulse;
Transmit a control command and a data address;
According to rising edge and the falling edge of these pulses in this frequency signal, capture this control command and this data address; And
According to the storer in this control command and this storage arrangement of this data address access.
7. the method for operating of storage arrangement according to claim 6, the step wherein transmitting this control command and this data address comprises:
Through a pin of this storage arrangement, sequentially transmit the multiple command bit in this control command and the multiple address bits in this data address.
8. the method for operating of storage arrangement according to claim 7, wherein according to rising edge and the falling edge of these pulses in this frequency signal, the step capturing this control command and this data address comprises:
Utilize rising edge and the falling edge of each these pulse, capture two command bits in these command bits or the position, two-address in these address bits.
9. the method for operating of storage arrangement according to claim 6, the step wherein transmitting this control command and this data address comprises:
Through one first pin of this storage arrangement, sequentially transmit multiple first command bit in this control command and multiple first address bits in this data address; And
Through one second pin of this storage arrangement, sequentially transmit multiple second command bit in this control command and multiple second address bits in this data address.
10. the method for operating of storage arrangement according to claim 9, wherein these pulses comprise multiple command pulse and multiple address pulse, and according to the rising edge of these pulses in this frequency signal and falling edge, the step capturing this control command and this data address comprises:
Utilize rising edge and the falling edge of each these command pulse, capture two first command bits in these first command bits and two second command bits in these the second command bits; And
Utilize rising edge and the falling edge of each these address pulse, capture two first address bits in these first address bits and two second address bits in these the second address bits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310624074.8A CN104681075B (en) | 2013-11-26 | 2013-11-26 | Storage arrangement and its operating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310624074.8A CN104681075B (en) | 2013-11-26 | 2013-11-26 | Storage arrangement and its operating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104681075A true CN104681075A (en) | 2015-06-03 |
| CN104681075B CN104681075B (en) | 2017-11-17 |
Family
ID=53316015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310624074.8A Active CN104681075B (en) | 2013-11-26 | 2013-11-26 | Storage arrangement and its operating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104681075B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111784872A (en) * | 2020-06-30 | 2020-10-16 | 湖南中车时代通信信号有限公司 | Train multi-intersection operation data switching and storing device for monitoring and recording plug-in |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW425546B (en) * | 1998-09-24 | 2001-03-11 | Fujitsu Ltd | Semiconductor memory device and method of controlling the same |
| US6349072B1 (en) * | 1999-11-05 | 2002-02-19 | Matsushita Electric Industrial Co., Ltd. | Random access memory device |
| TW490669B (en) * | 1999-12-16 | 2002-06-11 | Nippon Electric Co | Synchronous double data rate DRAM |
| CN1957530A (en) * | 2004-04-26 | 2007-05-02 | 爱特梅尔股份有限公司 | Charge pump clock for non-volatile memories |
| US20080062781A1 (en) * | 2006-09-08 | 2008-03-13 | Wen-Chang Cheng | Apparatus and related method for controlling switch module in memory by detecting operating frequency of specific signal in memory |
| CN101662448A (en) * | 2009-08-19 | 2010-03-03 | 东南大学 | Wireless communication method of high-speed sampling low-accuracy quantification impulse ultra-wideband |
-
2013
- 2013-11-26 CN CN201310624074.8A patent/CN104681075B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW425546B (en) * | 1998-09-24 | 2001-03-11 | Fujitsu Ltd | Semiconductor memory device and method of controlling the same |
| US6349072B1 (en) * | 1999-11-05 | 2002-02-19 | Matsushita Electric Industrial Co., Ltd. | Random access memory device |
| TW490669B (en) * | 1999-12-16 | 2002-06-11 | Nippon Electric Co | Synchronous double data rate DRAM |
| CN1957530A (en) * | 2004-04-26 | 2007-05-02 | 爱特梅尔股份有限公司 | Charge pump clock for non-volatile memories |
| US20080062781A1 (en) * | 2006-09-08 | 2008-03-13 | Wen-Chang Cheng | Apparatus and related method for controlling switch module in memory by detecting operating frequency of specific signal in memory |
| CN101662448A (en) * | 2009-08-19 | 2010-03-03 | 东南大学 | Wireless communication method of high-speed sampling low-accuracy quantification impulse ultra-wideband |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111784872A (en) * | 2020-06-30 | 2020-10-16 | 湖南中车时代通信信号有限公司 | Train multi-intersection operation data switching and storing device for monitoring and recording plug-in |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104681075B (en) | 2017-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104731746A (en) | Equipment controller device | |
| CN104811643B (en) | Image data high-speed memory system based on SD card array | |
| CN102012879A (en) | High-capacity data acquisition device and data transmission method thereof | |
| CN1971543A (en) | Method and device to realize data read-write control in burst mechanism | |
| CN203858630U (en) | Pcie interface switching device | |
| CN104681075A (en) | Storage device and operation method thereof | |
| CN201936294U (en) | Caching system for high-speed image acquisition system | |
| CN205228473U (en) | Miniature navigational computer based on field programmable gate array | |
| CN201918981U (en) | Dual-phase harvard code bus signal coding-decoding circuit | |
| CN110851393B (en) | USB conversion control board card with Aurora interface and method | |
| CN101813971B (en) | Processor and internal memory thereof | |
| CN202067260U (en) | Buffer memory system for reducing data transmission | |
| CN102110065B (en) | Cache system for reducing data transmission | |
| CN201184970Y (en) | Embedded board for acquiring data of watercraft engine compartment | |
| TWI534831B (en) | Memory device and operation method thereof | |
| CN203745873U (en) | Digital input controller used for Internet of things | |
| CN201435077Y (en) | Circuit structure supporting access of multi-SD card slave device | |
| CN201218843Y (en) | Radar passage expansion apparatus based on USB | |
| CN203376748U (en) | Single-bus receiving logical structure | |
| CN209765488U (en) | SRIO and USB conversion control board card | |
| CN203102307U (en) | Intelligent handheld device | |
| CN102411556A (en) | Processing unit interface for intellectual property (IP) core and automatic generation method thereof | |
| CN202495946U (en) | Bus type communication system of FPGA based on management and control of Internet of things | |
| CN101436172B (en) | Data transmission method and system | |
| CN201229782Y (en) | MP3 music player capable of reading and storing storage card data |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |