TWI534831B - Memory device and operation method thereof - Google Patents

Description

Memory device and its operation method

The present invention relates to a memory device and method of operation thereof, and more particularly to a memory device having a dual transfer rate and method of operation thereof.

In recent years, the rapid development of consumer electronic products (such as smart phones, tablets, digital cameras, etc.) has led to a rapid increase in demand for memory devices. In operation, in addition to providing a large amount of data storage, the memory device's transmission speed and reading performance will also affect the overall operation of the electronic product. In other words, memory devices have become an important component in electronic products. Therefore, how to improve the transmission speed or read performance of the memory device has become an important issue in the design of the memory device.

The invention provides a memory device and a method for operating the same, which utilizes both edges of a pulse of a clock signal to capture control commands and data addresses, thereby helping to improve the transmission speed and read performance of the memory device.

The memory device of the invention comprises a memory, a clock generator and a control Device. The clock generator generates a clock signal comprising a plurality of pulses. The memory device transmits control commands and data addresses to the controller. In addition, the controller retrieves the control command and the data address according to the rising edge and the falling edge of the plurality of pulses in the clock signal, and accesses the memory according to the control command and the data address.

In another aspect, the method of operating a memory device of the present invention includes the following steps. A clock signal is generated, wherein the clock signal includes a plurality of pulses. Transfer control commands and data addresses. The control command and the data address are retrieved according to the rising edge and the falling edge of the plurality of pulses in the clock signal. The memory in the memory device is accessed according to the control command and the data address.

Based on the above, the present invention utilizes both edges of the pulse of the clock signal to retrieve control commands and data addresses. Thereby, the memory device will be able to transmit control commands and data addresses using dual transmission rates, thereby helping to improve its transmission speed and read performance.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧ memory device

110‧‧‧ memory

120‧‧‧ clock generator

130‧‧‧ Controller

140~160‧‧‧ pins

CSB‧‧‧ wafer selection signal

Signal transmitted by SI/SIO0‧‧‧ pin 150

Signal transmitted by SO/SIO1‧‧‧ pin 160

SCLK‧‧‧ clock signal

S210~S240‧‧‧ to illustrate the steps of the embodiment of Fig. 2

S310, S320‧‧‧ for further explaining the steps of the embodiment of FIG.

P1~P31‧‧‧pulse

CM4‧‧‧ control order

AD4‧‧‧ data address

DT4‧‧‧ memory data

S510~S540‧‧‧ for further explaining the steps of the embodiment of FIG.

Bit group of CM41, CM42‧‧‧ control commands

Bit group of AD41, AD42‧‧‧ data address

Bit group of DT41, DT42‧‧‧ memory data

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.

2 is a flow chart of a method of operating a memory device in accordance with an embodiment of the present invention.

3 is a flow chart of an operation method of a memory device according to another embodiment of the present invention; Figure.

4 is a timing diagram of signals used to describe a memory device in accordance with an embodiment of the invention.

FIG. 5 is a flow chart of a method of operating a memory device in accordance with another embodiment of the present invention.

FIG. 6 is a timing diagram of signals for explaining a memory device according to another embodiment of the present invention.

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention. Referring to FIG. 1, the memory device 100 includes a memory 110, a clock generator 120, and a controller 130, and the memory device 100 has a plurality of pins 140-160. The clock generator 120 is electrically connected to the controller 130, and the controller 130 is electrically connected between the pins 140-160 and the memory 110.

In addition, the pin 140 of the memory device 100 is used to transmit the wafer selection signal CSB. The controller 130 switches to the enable mode or the disable mode according to the level of the chip selection signal CSB. In addition, the pin 150 of the memory device 100 is an input/output port of the memory device 100 and is used to transmit the signal SI/SIO0. Similarly, the pin 160 of the memory device 100 is another input/output port of the memory device 100 and is used to transmit the signal SO/SIO1. The signal SI/SIO0 and the signal SO/SIO1 may include, for example, a control command, a data address, a memory data, and the like.

2 is a flow chart of an operation method of a memory device according to an embodiment of the invention Cheng Tu. Please refer to FIG. 1 and FIG. 2 at the same time. As shown in step S210, the clock generator 120 is configured to generate a clock signal SCLK. As shown in step S220, the memory device 100 can transmit a control command and a data address through at least one pin. That is, the memory device 100 can communicate with an external device by means of serial transmission. In addition, as shown in step S230, the controller 130 retrieves the control command and the data address according to the rising edge and the falling edge of the plurality of pulses in the clock signal SCLK.

Moreover, as shown in step S240, the controller 130 will access the memory 110 according to the control command and the data address. For example, the controller 130 may decide to perform a specific operation on the memory 110 according to the control command, for example, a read operation, a write operation, and the like. In addition, the controller 130 selects a memory block in the memory 110 according to the data address, and performs the specific operation on the memory block in the memory 110. For example, the controller 130 may determine to read the memory 110 according to the control command, and then read a memory data from a memory block in the memory 110 according to the data address. In addition, the controller 130 may also perform a write operation on the memory 110 according to the control command, and then write a data to a memory block of the memory 110 according to the data address.

It is worth mentioning that for the control command and the data address, the controller 130 uses the two edges of the pulse (ie, the rising edge and the falling edge) to perform the capturing. In this way, for the transmission of the control command and the data address, the memory device 100 can achieve a double transfer rate, thereby helping to improve its transmission speed and read performance. In addition, with the switching of the input and output modes of the memory device 100, the controller 130 can also capture more than two lives in the control command by using a single pulse. The bit rate or more than two address bits in the data address can further improve the transmission speed and read performance of the memory device 100.

For example, FIG. 3 is a flow chart of a method of operating a memory device in accordance with another embodiment of the present invention. 4 is a timing diagram of signals used to describe a memory device in accordance with an embodiment of the invention. Please refer to FIG. 1, FIG. 3 and FIG. 4 at the same time.

In an embodiment, the memory device 100 can be switched to a single input/output mode. At this time, on the detailed flow of transmitting the control command and the data address (step S220), as shown in step S310, the memory device 100 will sequentially transmit the control commands through a pin (for example, the pin 150). Command bit and multiple address bits in the data address. In addition, on the detailed flow of capturing the control command and the data address (step S230), as shown in step S320, the controller 130 will utilize the rising edge and the falling edge of each pulse to retrieve the plurality of command bits. The two command bits in the middle or the two bit bits in the plurality of address bits.

For example, in the embodiment of FIG. 4, the clock signal SCLK includes pulses P1 P P31, and the control command CM4 includes 8 command bits, and the data address AD4 includes 24 address bits. In operation, when the wafer select signal CSB is switched to the low level, the controller 130 will switch to the enable mode and begin to retrieve the control command CM4 and the data address AD4. The controller 130 uses the pulse P1 to capture the first to second command bits in the control command CM4, and uses the pulse P2 to capture the third to fourth command bits in the control command CM4. By analogy, the controller 130 only needs to use the four pulses P1~P4 to retrieve the control command CM4 having 8 command bits.

After the control command CM4 is retrieved, the controller 130 will continue to draw funds. Material address AD4. The controller 130 uses the pulse P5 to capture the first to second address bits in the data address AD4, and uses the pulse P6 to retrieve the third to fourth address bits in the data address AD4. By analogy, the controller 130 only needs to use the 12 pulses P5~P16 to retrieve the data address AD4 with 24 address bits.

In other words, when the memory device 100 switches to the single input/output mode, the controller 130 will use two pulses or two address bits for each pulse, thereby contributing to the improvement of the memory device 100. transfer speed. In addition, in the embodiment of FIG. 4, the controller 130 determines to read the memory 110 according to the control command CM4, and further reads a memory data DT4 from the memory 110 with reference to the data address AD4. Furthermore, the controller 130 transmits the memory data DT4 using the rising edge and the falling edge of a plurality of pulses (for example, the pulses P24 to P31). That is, the memory device 100 can also transfer the memory data DT4 using the dual transfer rate.

The memory data DT4 is transmitted to the external device through the pin 160 of the memory device 100. In addition, the memory device 100 can be separated by a blank period on the input and output of the data. For example, as shown in FIG. 4, after receiving the control command CM14 and the data address AD4 through the transparent pin 150, the memory device 100 waits for a blank period including 8 pulses P17~P24, and then transmits the pin. 160 output memory data DT4. The length of the blank period depends on the reading frequency of the memory device 100. In addition, in practical applications, the memory device 100 can also output data after receiving the data without defining a blank period.

FIG. 5 is a flow chart of a method of operating a memory device in accordance with another embodiment of the present invention. 6 is a diagram for explaining a memory device according to another embodiment of the present invention. Signal timing diagram. Please refer to FIG. 1, FIG. 5 and FIG. 6 at the same time.

In an embodiment, the memory device 100 is further switchable to a dual input/output mode. At this time, on the detailed flow of transmitting the control command and the data address (step S220), as shown in steps S510 and S520, the memory device 100 will sequentially transmit the control command through the first pin (for example, the pin 150). a plurality of first command bits and a plurality of first address bits in the data address, and sequentially transmitting a plurality of second command bits in the control command through the second pin (eg, pin 160) Multiple second address bits in the meta and data addresses.

Additionally, the plurality of pulses includes a plurality of command pulses and a plurality of address pulses. On the detailed flow of capturing the control command and the data address (step S230), as shown in steps S530 and S540, the controller 130 will use the rising edge and the falling edge of each command pulse to retrieve the plurality of first And two second command bits in the command bit and two second command bits in the plurality of second command bits, and using the rising edge and the falling edge of each address pulse to extract the plurality of Two first address bits of the first address bit and two second address bits of the plurality of second address bits.

For example, in the embodiment of FIG. 6, the pulses P1 to P2 in the clock signal SCLK can be regarded as a plurality of command pulses, and the pulses P3 to P8 can be regarded as a plurality of address pulses. Further, in FIG. 6, the control command CM4 having 8 command bits is divided into two bit groups CM41 and CM42, and the bit groups CM41 and CM42 each include 4 command bits. Furthermore, in FIG. 6, the data address AD4 having 24 address bits is divided into two bit groups AD41 and AD42, and the bit groups AD41 and AD42 each include 12 address bits.

In operation, the controller 130 uses the pulse P1 (ie, the command pulse P1) to retrieve the first to second command bits in the bit group CM41 and the first to second commands in the bit group CM42. Bit. In addition, the controller 130 further uses the pulse P2 (ie, the command pulse P2) to retrieve the third to fourth command bits in the bit group CM41 and the third to fourth command bits in the bit group CM42. . In other words, in the dual input/output mode, the controller 130 only has to use the two pulses P1 and P2 to retrieve the control command CM4 having eight command bits.

On the other hand, the controller 130 uses the pulse P3 (ie, the address pulse P3) to extract the first to second address bits in the bit group AD41 and the first to second bits in the bit group AD42. Address bit. In addition, the controller 130 uses the pulse P4 (ie, the address pulse P4) to extract the 3rd to 4th address bits in the bit group AD41 and the 3rd to 4th bits in the bit group AD42. Address bit. By analogy, the controller 130 only needs to use the 6 pulses P3~P8 to retrieve the data address AD4 with 24 address bits.

In other words, when the memory device 100 switches to the dual input/output mode, the controller 130 will use four pulses or four address bits for each pulse to help improve the transmission of the memory device 100. speed. In addition, in the embodiment of FIG. 6, the controller 130 reads the memory data DT4 from the memory 110 according to the control command CM4, wherein the memory data DT4 is divided into two bit groups DT41 and DT42. Furthermore, the controller 130 transmits the bit groups DT41 and DT42 according to a plurality of pulses (for example, pulses P17 to P23), and the bit groups DT41 and DT42 pass through the two pins 150 and 160 of the memory device 100. Transfer to an external device.

In summary, the present invention utilizes both edges of the pulse of the clock signal to retrieve control commands and data addresses. Thereby, the memory device will be able to transmit control commands and data addresses using dual transmission rates, thereby helping to improve its transmission speed and read performance. In addition, the memory device can also switch its input and output modes, which can further improve its transmission speed and read performance.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

S210~S240‧‧‧ to illustrate the steps of the embodiment of Fig. 2

Claims (8)

A memory device includes: a memory; a clock generator that generates a clock signal including a plurality of pulses; and a controller, wherein the memory device transmits a control command and a data address to the controller, And the controller extracts two or more command bits in the control command or two or more address bits in the data address according to the rising edge and the falling edge of the pulses, and according to the control command The data address accesses the memory. The memory device of claim 1, wherein the memory device has a pin, and the pin is configured to sequentially transmit the command bit in the control command and the data address in the data address These address bits. The memory device of claim 1, wherein the memory device has a first pin and a second pin, and the first pin is configured to sequentially transmit the plurality of control commands. a first command bit and a plurality of first address bits in the data address, the second pin is configured to sequentially transmit a plurality of second command bits in the control command and the data address Multiple second address bits. The memory device of claim 3, wherein the pulses comprise a plurality of command pulses and a plurality of address pulses, and the controller uses the rising and falling edges of each of the command pulses to extract the Two first command bits in the first command bit and two second command bits in the second command bits, and the controller utilizes a rising edge and a falling edge of each of the address pulses, Taking two first address bits of the first address bits and two second address bits of the second address bits. A method for operating a memory device, comprising: generating a clock signal, wherein the clock signal comprises a plurality of pulses; transmitting a control command and a data address; and rising and falling according to the pulses in the clock signal Edge, capturing more than two command bits in the control command or two or more address bits in the data address; and accessing one of the memory devices according to the control command and the data address Memory. The method for operating a memory device according to claim 5, wherein the transmitting the control command and the data address comprises: sequentially transmitting the control command through a pin of the memory device Some command bits and the address bits in the data address. The method for operating a memory device according to claim 5, wherein the transmitting the control command and the data address comprises: sequentially transmitting the control command through a first pin of the memory device Transmitting a plurality of first command bits and a plurality of first address bits in the data address; and sequentially transmitting a plurality of second commands in the control command through a second pin of the memory device A bit and a plurality of second address bits in the data address. The method of operating a memory device according to claim 7, wherein the pulses comprise a plurality of command pulses and a plurality of address pulses, and according to rising and falling edges of the pulses in the clock signal The steps of capturing the command bits in the control command or the address bits in the data address include: Using the rising edge and the falling edge of each of the command pulses, extracting two first command bits of the first command bits and two second command bits of the second command bits; Extracting a rising edge and a falling edge of each of the address pulses, and extracting two first address bits of the first address bits and two second address bits of the second address bits yuan.