CN203733474U

CN203733474U - Synchronous memory

Info

Publication number: CN203733474U
Application number: CN201420093988.6U
Authority: CN
Inventors: 亚历山大; 谈杰
Original assignee: Xian Sinochip Semiconductors Co Ltd
Current assignee: Xian Sinochip Semiconductors Co Ltd
Priority date: 2014-03-03
Filing date: 2014-03-03
Publication date: 2014-07-23
Anticipated expiration: 2024-03-03

Abstract

The utility model provides a novel synchronous memory having the advantages that the area of the memory can be saved and the performance of the memory can be improved. The synchronous memory comprises a first-in first-out (FIFO) stack, a memory array and a clock delay unit, wherein a received reading command and a received reading address are input into the FIFO stack together, and meanwhile, a system clock provides a synchronous clock signal for the FIFO stack; the synchronous clock signal is converted into a delay clock signal through the clock delay unit, and the delay clock signal is used as an indication signal for the end of the reading command and the reading address of the FIFO stack to be provided for the FIFO stack and the memory array respectively; the FIFO outputs the delayed reading command and the reading address to the memory array, and the memory array outputs parallel data to be sent to a data output interface after direct parallel-to-serial operation.

Description

A kind of synchronous memories

Technical field:

The utility model relates to a kind of semiconductor memory.

Background technology

Computing machine and various electronic equipment are widely used in the various aspects of the modern life, increasing to internal memory product (DRAM storer) demand.

As shown in Figure 1, traditional reservoir designs framework, its feature is: outside read command and read address and access storage array with prestissimo; The data of extracting from storage array are first temporarily stored in data FIFO stack; By the time read command finishes (cas time delay (Fig. 4)) and from data FIFO stack, discharges data to data output interface.

There is following problem in this scheme:

1, legacy memory framework needs data FIFO stack, and all very large common 32 of general data bit wides, 64,128, the memory area taking is larger.

2, DRAM storer JEDEC standard definition activation command to time (Trcd) of read command as shown in Figure 3, the performance of less storer of Trcd time is better.Because legacy memory read command is accessed storage array with prestissimo, thus the Trcd that arranges no better than external system of inner Trcd time, will be to a great extent occupying system resources.

Utility model content

The purpose of this utility model is to provide a kind of novel synchronous memories, can save memory area, improve memory performance.

The technical solution of the utility model is as follows:

This synchronous memories, comprise FIFO stack, storage array and clock delay unit, its special character is: the read command that this synchronous memories receives and read the described FIFO stack of the common input in address, and simultaneity factor clock provides synchronizing clock signals to FIFO stack; Described synchronizing clock signals, through described clock delay unit output delay clock signal, as the indicator signal of FIFO stack reading order, end of address (EOA), offers respectively described FIFO stack and storage array; The read command of described FIFO stack output delay and read address to storage array, storage array output parallel data directly carries out and turns string module delivering to data output interface.

Above-mentioned clock delay unit can adopt digital delay phase-locked loop to realize.

The utlity model has following advantage:

1. save memory area

The utility model replaces data stack with command address storehouse; Required order bit wide is 1, and address bit wide depends on memory access capacity, and the DRAM storer of a 4Gbit is read address bit wide and is only required to be 10.Therefore required first-in first-out storehouse bit wide obviously reduces, thereby significantly optimizes chip area.

2, improve memory performance

The utility model is storehouse to be put into in read command and address first wait for that the T time visits again storage array, takes full advantage of the memory inside Trcd time, and the inner Trcd time equals outside Trcd+T.Under the constant prerequisite of memory inside Trcd, external system can arrange less Trcd like this.

Brief description of the drawings

Fig. 1 is the reservoir designs framework of prior art.

Fig. 2 is synchronous memories design architecture of the present utility model.

Fig. 3 is DRAM storer Trcd definition.

Fig. 4 is that DRAM storer cas defines time delay.

Embodiment

As shown in Figure 2, the receiver of read command and the output terminal of receiver of reading address are connected to the data input pin (input) of FIFO stack, the output terminal of the receiver of system clock is connected to the synchronous clock input end (input clock) of FIFO stack, synchronizing clock signals is through digital delay phase-locked loop output delay clock signal, as the indicator signal of FIFO stack reading order, end of address (EOA), this indicator signal is connected to the end signal input end (output clock) of FIFO stack; The read command of FIFO stack output delay and read address to storage array, storage array output parallel data.

Can find out, in the utility model, read command and to read address be not with prestissimo access storage array, but first put it into command address FIFO stack, (T equals cas and deducts the required access time of memory inside array time delay) visits again storage array to wait for the T time.Storage array output data directly carry out and turn string operation after deliver to data output interface.

Claims

1. a synchronous memories, comprise FIFO stack, storage array and clock delay unit, it is characterized in that: the read command that this synchronous memories receives and read the described FIFO stack of the common input in address, simultaneity factor clock provides synchronizing clock signals to FIFO stack; Described synchronizing clock signals, through described clock delay unit output delay clock signal, as the indicator signal of FIFO stack reading order, end of address (EOA), offers respectively described FIFO stack and storage array; The read command of described FIFO stack output delay and read address to storage array, storage array output parallel data directly carries out and turns string module delivering to data output interface.

2. synchronous memories according to claim 1, is characterized in that: described clock delay unit adopts digital delay phase-locked loop.