CN203224620U

CN203224620U - Radar data acquisition device based on ultrahigh speed USB

Info

Publication number: CN203224620U
Application number: CN 201320191389
Authority: CN
Inventors: 谢承华
Original assignee: CHENGDU YUANWANG TECHNOLOGY Co Ltd
Current assignee: CHENGDU YUANWANG TECHNOLOGY Co Ltd
Priority date: 2013-04-16
Filing date: 2013-04-16
Publication date: 2013-10-02
Anticipated expiration: 2023-04-16

Abstract

The utility model discloses a radar data acquisition device based on an ultrahigh speed USB (Universal Serial Bus), comprising an FPGA (Field Programmable Gate Array) and a memory. The radar data acquisition device is characterized by also comprising a photoelectric converter, a serial decoder and a USB 3.0 interface; wherein an input end of the photoelectric converter is connected with a radar data signal, an output end of the photoelectric converter is connected with an input end of the serial decoder; the FPGA is provided with a data analysis module, a format conversion module and a data synchronous module which are connected in series in order therein, an output end of the serial decoder is connected with an input end of the data analysis module, a memory end of the data synchronous module is connected with the memory, a communication end of the data synchronous module is connected with an inner end of the USB 3.0 interface, an outer end of the USB 3.0 interface is used for being connected with a PC (Personal Computer) machine. By applying a USB 3.0 ultrahigh speed bus technology in radar data acquisition, the radar data acquisition device of the utility model effectively overcomes the data transmission bottleneck for a high-resolution high-data-throughput radar system, and is suitable for a portable radar processing terminal and various signal processing systems.

Description

Radar data acquisition device based on hypervelocity USB

Technical field

The utility model relates to a kind of radar data acquisition device, relates in particular to the wide radar data acquisition device based on hypervelocity USB of a kind of transport tape.

Background technology

USB is a kind of fast and flexible, bus form easy for installation, is widely used in modern industry production and the scientific research.The traditional radar data harvester adopts the USB2.0 bussing technique more, its circuit structure block diagram as shown in Figure 1, its principle of work is: the radar data that signal processor generates writes in the external FIFO after the FPGA format conversion, and the bridge chip in the notice USB2.0 interface starts and reads the FIFO flow process, with the data buffer memory to bridge chip inside; Bridge chip in the USB2.0 interface and the data interaction between PC are adopted inquiry mode by the PC master control.

Super-speed development along with modern radar technology, sampling rate and processing bandwidth constantly increase, make data throughout sharply rise, X-band single polarization Doppler radar data transfer rate is about 256Mbps, as upgrade to dual polarization radar, its data transfer rate can reach 512Mbps, and particularly for some high-resolution radars, its data transfer rate often all surpasses 500Mbps.The peak transfer rate 480Mbps of the USB2.0 bus that above-mentioned traditional radar data harvester adopts, consider system overhead, the not enough 400Mbps of its actual transfer rate, and transport tape width, the data spatial cache is little, in case buffer memory occurring when big easily, the PC load overflows, so the traditional radar data harvester is subject to bus bandwidth and PC response time, when particularly being in big load operation for PC, the continuity of data can not be guaranteed fully, the continuous error-free received data transmission requirement of radar system can not be satisfied.

The utility model content

The purpose of this utility model provides a kind of transport tape the wide radar data acquisition device based on hypervelocity USB with regard to being in order to address the above problem.

The utility model is achieved through the following technical solutions above-mentioned purpose:

Radar data acquisition device based on hypervelocity USB described in the utility model comprises FPGA, storer, photoelectric commutator, serial decode device and USB3.0 interface, the input end of described photoelectric commutator connects the radar data signal, the output terminal of described photoelectric commutator is connected with the input end of described serial decode device, be provided with the data resolution module that is connected in series successively in the described FPGA, format converting module and data simultaneous module, the output terminal of described serial decode device is connected with the input end of described data resolution module, the storage end of described data simultaneous module is connected with described storer, the communication terminal of described data simultaneous module is connected with the inner of described USB3.0 interface, and the outer end of described USB3.0 interface is used for being connected with PC.

Further, described storer is DDR2.

The beneficial effects of the utility model are:

The utility model is applied to USB3.0 hypervelocity bussing technique and DDR2 memory technology in the radar data acquisition, efficiently solve the transmission bottleneck for high resolving power, high data throughput radar system, characteristics such as that the USB3.0 interface has is simple in structure, plug and play, be highly suitable for portable radar processing terminal and various signal processing system, have advantage applied widely.

Description of drawings

Fig. 1 is the circuit structure block diagram of traditional radar data harvester;

Fig. 2 is the circuit structure block diagram of the radar data acquisition device based on hypervelocity USB described in the utility model.

Embodiment

The utility model is described in further detail below in conjunction with accompanying drawing:

As shown in Figure 2, radar data acquisition device based on hypervelocity USB described in the utility model comprises FPGA, DDR2, photoelectric commutator, serial decode device and USB3.0 interface, the input end of photoelectric commutator connects the radar data signal, the output terminal of photoelectric commutator is connected with the input end of serial decode device, be provided with the data resolution module that is connected in series successively in the FPGA, format converting module and data simultaneous module, the output terminal of serial decode device is connected with the input end of data resolution module, the storage end of data simultaneous module is connected with DDR2, the communication terminal of data simultaneous module is connected with the inner of USB3.0 interface, and the outer end of USB3.0 interface is used for being connected with PC.In the said structure, the common composition data format converting module of data resolution module, format converting module and data simultaneous module in the common composition data receiving end of photoelectric commutator and serial decode device, FPGA.

As shown in Figure 2, the principle of work of this device is: the hypervelocity radar data of radar mean frequency processor (not shown) output installs to this through Optical Fiber Transmission, finishes opto-electronic conversion and serial decode by data receiver, obtains 16 bit parallel data; FPGA resolves these data by specific format, isolates data head and mode bit, and finishes floating-point format conversion and processing synchronously; The data buffer memory realizes that by two DDR2 that plate carries maximum can be stored the 2Gb data volume; The USB3.0 interface is realized the Data Bridge of PC and FPGA, and Transmission System of Radar Data adopts GPIFII communication protocol, and speed is faster, and efficient is higher, and PC also can send control command to FPGA by the USB3.0 interface, realizes the spatial cache dynamic assignment.

As shown in Figure 2, the concrete structure of each parts is as follows:

Photoelectric commutator: adopt FTAF-1312, operation wavelength 1310nm, the multimode mode, unidirectional peak transfer rate 1.25Gbps, two-way LC interface, operating voltage 3.3V, input electrical signal are the CML level, the output electric signal is the LVPECL level.

Serial decode device: adopt the TI DS92LV16 of company, 16 bit data bit wides, unidirectional peak transfer rate is 1.25Gbps, it is inner integrated 16:1 and 1:16 stringization, deserializer, support asynchronous transfer mode and losing lock self check, operating voltage 3.3V, parallel interface is the LVTTL level, serial line interface is the LVDS level, by the interconnection of level transferring chip SN65LVDT100 realization with the opto-electronic conversion chip.

FPGA: comprise data resolution module, format converting module and data simultaneous module three parts, all be located in the FPGA.FPGA adopts the ALTERA CycloneIII of company series EP3C16, and low in energy consumption, logical resource and IO are abundant, and integrated PLL is for generation of the reference clock of serial decode device.Specifying of each module is as follows:

Data resolution module mainly is responsible for parsing data start flag from parallel data stream, and this sign has identified the initial of radar system one frame data, has also comprised each extension set status information of radar system and antenna angle sign indicating number information in the data head.

Format converting module is responsible for the floating-point format (16 floating-points) that radar return data (32 fixed points) system that is converted to is required, and conversion loss is 0.02dB.

Floating data after data simultaneous module will be changed writes in the data buffer, because buffer is made of outside DDR2 chip, FPGA is by calling the integrated DDR2IP nuclear of ALTERA company, and it is encapsulated as fifo structure, notice USB controller reads data when FIFO is in half-full state, when being in the near-space state as FIFO, thereby notice USB controller time-out reads data to guarantee that FIFO is not read sky and causes error in data.Because it is fast that FIFO read data rhythm ratio is write rhythm data, thereby guarantee that FIFO can not occur writing full state, avoid loss of data.

DDR2: be two, adopt the MT47H64M16 chip, 16 bit data bus, the monolithic storage depth is 64M * 16Bits.This chip adopts SSTL_18CLASSI level standard, 667MHz bus frequency.Two storeies adopt the bus shared models, and the cascade storage depth can reach 2Gb, guarantee FIFO when PC is in busy condition can with during the whole buffer memorys of data, data can not occur and overflow and cause the phenomenon of losing, can effectively improve the radar system data accuracy.

The USB3.0 interface: inner chip adopts the CYUSB3014 of CYPRESS company, it is embedded 32-bit microprocessor, adopt the GPIFII agreement of optimizing with the FPGA data communication, with FPGA as data source, the FIFO mode of operation, FPGA provides and writes completely and read sky zone bit and enable operation, and the USB controller is initiatively initiated the read data operation, peak transfer rate is 5Gbps, and mode of operation is: Super/High/full.This chip also provides 13 programmable I/Os, and in order to the various states of characterization data transmission, convenient location and accent are surveyed.Control command between PC and the FPGA communicates by the serial ports that the USB controller provides, and standard UART agreement can satisfy the control operation of low speed.This chip is also supported backward compatible USB2.0 agreement, supports full speed/hypervelocity mode of operation, is applicable to the less demanding radar system of data throughout.

Claims

1. radar data acquisition device based on hypervelocity USB, comprise FPGA and storer, it is characterized in that: also comprise photoelectric commutator, serial decode device and USB3.0 interface, the input end of described photoelectric commutator connects the radar data signal, the output terminal of described photoelectric commutator is connected with the input end of described serial decode device, be provided with the data resolution module that is connected in series successively in the described FPGA, format converting module and data simultaneous module, the output terminal of described serial decode device is connected with the input end of described data resolution module, the storage end of described data simultaneous module is connected with described storer, the communication terminal of described data simultaneous module is connected with the inner of described USB3.0 interface, and the outer end of described USB3.0 interface is used for being connected with PC.

2. the radar data acquisition device based on hypervelocity USB according to claim 1, it is characterized in that: described storer is DDR2.