CN202422113U - Switching system for realizing industry standard architecture (ISA) bus on performance optimization with enhanced RISC-performance computing (PowerPC) embedded computer - Google Patents
Switching system for realizing industry standard architecture (ISA) bus on performance optimization with enhanced RISC-performance computing (PowerPC) embedded computer Download PDFInfo
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- CN202422113U CN202422113U CN2012200107306U CN201220010730U CN202422113U CN 202422113 U CN202422113 U CN 202422113U CN 2012200107306 U CN2012200107306 U CN 2012200107306U CN 201220010730 U CN201220010730 U CN 201220010730U CN 202422113 U CN202422113 U CN 202422113U
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Abstract
The utility model discloses a switching system for realizing an industry standard architecture (ISA) bus on a performance optimization with enhanced RISC-performance computing (PowerPC) embedded computer. The switching system comprises a peripheral component interconnect (PCI) Target bridge, an ISA bus converter bridge, a direct memory access (DMA) controller and a PCI Master bridge, wherein one end of the PCI Target bridge is connected with a PCI bus and the other end of the PCI Target bridge is connected with the ISA bus converter bridge; the other end of the ISA bus converter bridge is connected with the ISA bus; one end of the PCI Master bridge is connected with the PCI bus and the other end of the PCI Master bridge is connected with the DMA controller; and the other end of the DMA controller is connected with the ISA bus. By the switching system, the problem that the PCI bus of a PowerPC computer operates external equipment in a standard ISA bus mode is solved, and the external equipment communicates with the PowerPC computer in a DMA transmission mode of the standard ISA bus.
Description
Technical field
The utility model relates to the converting system that a kind of PowerPC embedded computer is realized isa bus.
Background technology
High speed development along with electronic technology; X86 such as i386, i486 embedded computer all is old manufacturing process; Big even the device stopping production of power consumption, therefore, former facing significantly with x86 embedded computer device designed changed; For fear of carry out the system equipment change because of embedded computer, can use the PowerPC embedded computer of present widespread use to replace the x86 computing machine.Yet, the isa bus of a standard of x86 computing machine expansion, and the PowerPC processor has only a Local BUS and a pci bus, does not have the isa bus expansion of standard.To substitute the x86 computing machine fully and just must realize the isa bus function of PowerPC embedded computer, must on the PowerPC computing machine, carry out the basic functions such as the operation of read-write peripheral hardware, interruption expansion and DMA transmission of isa bus.
The utility model content
The purpose of the utility model is to solve the deficiency of existing PowerPC embedded computer; Provide a kind of novel PowerPC embedded computer to realize the converting system of isa bus; Overcome conventional P owerPC embedded computer and have only a Local BUS and a pci bus, do not support the shortcoming of isa bus.
The purpose of the utility model realizes through following technical scheme: the PowerPC embedded computer is realized the converting system of isa bus; Be located between the pci bus and isa bus of PowerPC embedded computer; It comprises that one is discerned decoding to the operational order on the pci bus; Produce the read/write operation signal; And the PCI Target bridge of address signal, data-signal and address space decoded signal; A conversion of signals that PCI Target bridge is produced becomes the isa bus Bridge of isa bus signal, dma controller and one with the dma controller data stream through the pci bus data transmission in storer, or memory data is transferred to the PCI Master bridge of dma controller through pci bus; One end of PCI Target bridge is connected with pci bus; The other end of PCI Target bridge is connected with the isa bus Bridge; The other end of isa bus Bridge is connected with isa bus; One end of PCI Master bridge is connected with pci bus, and the other end of PCI Master bridge is connected with dma controller, and the other end of dma controller is connected with isa bus.
The beneficial effect of the utility model is: after the PowerPC embedded computer replaces the x86 computing machine; Need not to change electronic equipment and the system's miscellaneous equipment that designed with the x86 embedded computer originally; Solved the problem of the pci bus of PowerPC computing machine with standard I SA bus mode operation external unit; Simultaneously also solved the problem that external unit carries out communication with the DMA transmission mode and the PowerPC computing machine of standard I SA bus; And be not limited to 8 or 16 bit data width of isa bus, can carry out the DMA transmission of 32 bit data width.
Description of drawings
Fig. 1 is the utility model structural representation block diagram.
Embodiment
The technical scheme of the utility model is described in further detail: as shown in Figure 1 below in conjunction with accompanying drawing; The PowerPC embedded computer is realized the converting system of isa bus; Be located between the pci bus and isa bus of PowerPC embedded computer; It comprises that one is discerned decoding to the operational order on the pci bus; Produce the read/write operation signal; And the PCI Target bridge of address signal, data-signal and address space decoded signal, a conversion of signals that PCI Target bridge is produced becomes the isa bus Bridge of isa bus signal, dma controller and one with the dma controller data stream through the pci bus data transmission in storer, or memory data is transferred to the PCI Master bridge of dma controller through pci bus; One end of PCI Target bridge is connected with pci bus; The other end of PCI Target bridge is connected with the isa bus Bridge; The other end of isa bus Bridge is connected with isa bus; One end of PCI Master bridge is connected with pci bus, and the other end of PCI Master bridge is connected with dma controller, and the other end of dma controller is connected with isa bus.
Adopt the CPLD chip to realize the Target bridge function of pci bus; The CPLD conversion chip adopts the EPM1270F256 chip of altera corp; The pci bus signal of PowerPC processor is connected on the CPLD chip; Isa bus after will changing is again drawn externally connector, and the isa bus of standard comprises that 16Bit data bus, 24Bit address bus, read/write control bus, address allow signal AEN etc.Thereby realize the PowerPC processor through the operation pci bus, through accomplishing operation behind the CPLD to isa bus.Wherein, IP core module adopts the IP core of Latice company; Operational order on the pci bus is discerned decoding, produces the read/write operation signal, and address signal, data-signal and address space decoded signal; The isa bus Bridge is transferred to isa bus with the signal that IP core produces, and accomplishes the data transmission to isa bus equipment.Its principle of work is following: the processor of PowerPC embedded computer carries out read/write operation to pci bus; Produce read/write command; IP core module is discerned this order and the address space of its operation is deciphered, and forms the bus operation signal of 32Bit data width; The isa bus Bridge is discerned the external unit that will operate according to address space, these signals is converted again to the bus operation of 8 or 16 bit data width.
When the external unit on the isa bus needs the memory resource of direct and PowerPC computing machine to carry out data transmission; Through dma controller operation PCI Master bridge; PCI Master bridge through pci bus with data transmission in storer; Perhaps memory data is transferred to dma controller, thereby the memory resource that reaches isa bus and PowerPC computing machine carries out the purpose of data transmission.Wherein, dma controller must be compatible with the dma controller on the isa bus, and the dma controller of standard I SA bus adopts two intel D8237 to carry out cascade, totally 7 passages; The IP core compatible with D8237 that also uses two altera corps to provide revises a little and carries out cascade.Any DMA passage of isa bus transmits to the dma controller request for data through corresponding dma request signal DREQx; Dma controller can be arbitrated DRQx; File an application to pci bus by the PCI REQ signal of PCI Master bridge then, arbitrate by the pci bus arbiter device.After the DMA request of above-mentioned isa bus is succeedd by pci bus arbiter; Pci bus is answered a response signal GNT; The response signal DACKx to isa bus of this signal controlling dma controller, so DACKx effectively representes the DMA request achieving success on the isa bus.Dma controller produces reading (IORD/) or writing (IOWE/), DAM address permission signal AEN on the isa bus then; And the address signal A15～A0 of isa bus; Data on the isa bus are transferred to PCI Master bridge successively, and PCI Master bridge carries out data transmission through pci bus and computer-internal storer again; Perhaps dma controller writes the data of computer-internal storer on the equipment of isa bus successively.The DMA one-time request can be accomplished the transmission of single byte, the perhaps transmission of a certain blocks of data (maximum 64K byte) after succeeing.
Claims (1)
1.PowerPC embedded computer is realized the converting system of isa bus; Be located between the pci bus and isa bus of PowerPC embedded computer; It is characterized in that: it comprises that one is discerned decoding to the operational order on the pci bus; Produce the read/write operation signal; And the PCI Target bridge of address signal, data-signal and address space decoded signal; A conversion of signals that PCI Target bridge is produced becomes the isa bus Bridge of isa bus signal, dma controller and one with the dma controller data stream through the pci bus data transmission in storer, or memory data is transferred to the PCI Master bridge of dma controller through pci bus; One end of PCI Target bridge is connected with pci bus; The other end of PCI Target bridge is connected with the isa bus Bridge; The other end of isa bus Bridge is connected with isa bus; One end of PCI Master bridge is connected with pci bus, and the other end of PCI Master bridge is connected with dma controller, and the other end of dma controller is connected with isa bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200107306U CN202422113U (en) | 2012-01-11 | 2012-01-11 | Switching system for realizing industry standard architecture (ISA) bus on performance optimization with enhanced RISC-performance computing (PowerPC) embedded computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200107306U CN202422113U (en) | 2012-01-11 | 2012-01-11 | Switching system for realizing industry standard architecture (ISA) bus on performance optimization with enhanced RISC-performance computing (PowerPC) embedded computer |
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| Publication Number | Publication Date |
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| CN202422113U true CN202422113U (en) | 2012-09-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2012200107306U Expired - Fee Related CN202422113U (en) | 2012-01-11 | 2012-01-11 | Switching system for realizing industry standard architecture (ISA) bus on performance optimization with enhanced RISC-performance computing (PowerPC) embedded computer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103793263A (en) * | 2014-01-24 | 2014-05-14 | 天津大学 | DMA transaction-level modeling method based on Power PC processor |
| CN104714907A (en) * | 2013-12-11 | 2015-06-17 | 中国航空工业第六一八研究所 | Design method for converting PCI bus into ISA bus or APB bus |
-
2012
- 2012-01-11 CN CN2012200107306U patent/CN202422113U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104714907A (en) * | 2013-12-11 | 2015-06-17 | 中国航空工业第六一八研究所 | Design method for converting PCI bus into ISA bus or APB bus |
| CN104714907B (en) * | 2013-12-11 | 2018-01-16 | 中国航空工业第六一八研究所 | A kind of pci bus is converted to ISA and APB bus design methods |
| CN103793263A (en) * | 2014-01-24 | 2014-05-14 | 天津大学 | DMA transaction-level modeling method based on Power PC processor |
| CN103793263B (en) * | 2014-01-24 | 2017-04-26 | 天津大学 | DMA transaction-level modeling method based on Power PC processor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120905 Termination date: 20160111 |