CN115509987B - High-precision trigger board card based on MiniVPX architecture and trigger method - Google Patents

High-precision trigger board card based on MiniVPX architecture and trigger method Download PDF

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CN115509987B
CN115509987B CN202211130709.4A CN202211130709A CN115509987B CN 115509987 B CN115509987 B CN 115509987B CN 202211130709 A CN202211130709 A CN 202211130709A CN 115509987 B CN115509987 B CN 115509987B
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trigger
board card
bus
functional
board
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CN115509987A (en
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魏德宝
刘旺
蓝林锴
张京超
乔立岩
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Harbin Institute of Technology
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Harbin Institute of Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

Interface module and trigger unit, high accuracy trigger integrated circuit board and trigger method based on MiniVPX framework, relate to aircraft airborne test system field. Aiming at the problems in the prior art that the real-time performance and the synchronism of airborne test data are difficult to ensure by the existing test system, the invention provides the technical scheme that: a trigger bus unit of an interface module, the unit comprising: the system comprises a trigger bus, a CPU board card, a trigger board card and at least two functional board cards; at least two functional boards are connected in series, the functional boards sequentially send trigger signals to the next functional board, the last functional board sends the trigger signals to the CPU board, and the first functional board is used for responding the trigger signals sent by the trigger boards; the CPU board card is used for sending a control signal to the trigger board card; the trigger board card is used for sending trigger signals to the first functional board card and also respectively sending the trigger signals to all the functional board cards in a star connection mode. The system is suitable for being applied to the airborne test system in the field of airborne test systems of aircrafts.

Description

High-precision trigger board card based on MiniVPX architecture and trigger method
Technical Field
The field of aircraft airborne test systems relates to, in particular to a high-precision trigger board card.
Background
The MiniVPX architecture-based test system has become an emerging test platform with the advantages of high reliability, extremely small volume, high-performance data transmission bandwidth, modularization and the like. The main control board card is used as a calculation control core, and the functions of data acquisition, analysis processing, storage, package export and the like are completed through each functional board card.
In the actual test process, many test systems require strict synchronous input and output relation between signals, and the synchronization and control of one test are preconditions for many test items, namely, after collecting and outputting a certain signal, the next test action is synchronously performed. Depending on factors such as stimulus, response, etc., synchronization mechanisms mainly occur in two ways: one is to use a clock; the other is to use a trigger. The test system based on MiniVPX architecture does not define bus protocol related to synchronization and triggering, but each functional board card and test instrument in the system should have accurate synchronization or triggering control to achieve the purpose of simultaneous operation or meeting certain condition operation, and the triggering board card needs to be designed from both hardware and logic aspects.
In an onboard test system, the function of triggering the board card directly influences the accuracy and instantaneity of data acquisition of the data acquisition equipment. In order to ensure the real-time performance and the synchronism of the onboard test data, it is necessary to provide a high-precision trigger board card in the onboard test system.
The real-time performance and the synchronism of the airborne test data are difficult to ensure by the existing test system, the occupied space of the airborne chassis is large because of the large volume of the test system, the requirement of small-size and light-weight is difficult to realize, and the related research of the high-precision trigger board card based on MiniVPX does not exist in the prior art.
Disclosure of Invention
Aiming at the problems that the real-time performance and the synchronism of airborne test data are difficult to ensure by the existing test system in the prior art, and the occupied space of an airborne chassis is also large and the requirements of small size and light weight are difficult to realize because the volume of the test system is large based on the existing test system, the invention provides the technical scheme that:
a trigger bus unit of an interface module, the unit comprising: the system comprises a trigger bus, a CPU board card, a trigger board card and at least two functional board cards;
the at least two functional boards are connected in series, the functional boards sequentially send trigger signals to the next functional board, the last functional board sends the trigger signals to the CPU board, and the first functional board is used for responding the trigger signals sent by the trigger boards;
the CPU board card, the trigger board card and the functional board card respectively interact with the trigger bus;
the CPU board card is used for sending a control signal to the trigger board card;
the trigger board card is used for sending trigger signals to the first functional board card and also respectively sending the trigger signals to all the functional board cards in a star connection mode.
Further, a preferred implementation manner is provided, the last functional board card sends a trigger signal to the CPU board card in a point-to-point connection manner, the CPU board card sends the trigger signal to the trigger board card in a point-to-point connection manner, and the trigger board card sends the trigger signal to the CPU board card in a star connection manner.
Further, a preferred embodiment is provided, wherein the star connection is via a star trigger line.
Further, there is provided a preferred embodiment wherein the trigger bus includes an SMBus bus for transmitting device configuration information collected by the unit.
Further, a preferred embodiment is provided, wherein the trigger bus performs information interaction with the CPU board card, the trigger board card and the function board card through TRIG [2:0 ].
Based on the same inventive concept, the present invention also provides an interface module, comprising: the interface module triggers the bus unit.
Based on the same inventive concept, the invention also provides a high-precision trigger board card based on a MiniVPX architecture, wherein the board card comprises: the device comprises a power module, a clock distribution module, a control module, a storage module, an interface module and a connector;
the interface module is the interface module, and the power module is used for supplying power to the clock distribution module, the control module and the storage module;
the clock distribution module performs information interaction with the connector and is used for multiplexing the received clock signals to each functional board card;
the control module is used for carrying out information interaction with the connector through the interface module and controlling the switching of the clock source of the clock distribution module;
the storage module is used for storing the working information of the trigger board card.
Based on the same inventive concept, the invention also provides a triggering method of the high-precision triggering board card, wherein the method is realized based on the high-precision triggering board card based on the MiniVPX framework, and the method comprises the following steps:
step 1: initializing the board;
step 2: collecting the received control signals;
step 3: analyzing the control signal;
step 4: judging whether the control signal is to start acquisition according to the analyzed signal, and if so, starting acquisition of data by the board card;
step 5: collecting a received new control signal II;
step 6: analyzing the second control signal;
step 7: and judging whether the control signal is the end of acquisition according to the analyzed signal, and if so, ending the acquisition of data by the board card.
Further, a preferred embodiment is provided, wherein in the step 2 and the step 5, the acquisition signal is received through an Aurora bus.
Further, there is provided a preferred embodiment, wherein the step 4 specifically includes: further comprises:
step 4.1: and if the judgment result is negative, waiting for a next acquired control signal.
The invention has the advantages that:
the high-precision trigger board card based on the MiniVPX framework can ensure the real-time performance and the synchronism of airborne test data, is based on the MiniVPX structural design, can be used in a miniaturized case based on MiniVPX, and can provide high-precision clocks and trigger bus types with rich types for equipment.
The high-precision trigger board card based on the MiniVPX framework is designed based on the MiniVPX framework, has the characteristic of small size, realizes a clock distribution function on a circuit under the condition that the size of the board card is limited, and realizes a trigger function by an FPGA.
The high-precision trigger board card based on the MiniVPX framework designs various types of trigger buses, including a point-to-point trigger bus, a star trigger bus and a self-defined TRIG [2:0] bus, and can be triggered by using different trigger modes according to different scenes and different trigger precision requirements.
The high-precision trigger board card based on the MiniVPX framework provided by the invention uses a combined trigger mode to trigger a single channel for a specific scene for acquiring single-channel data.
The high-precision trigger board card based on the MiniVPX framework forwards the accurate clock signals, transmits the accurate clock signals to the back board and front board connectors, and synchronously provides accurate synchronous clock signals for all functional boards and multiple boxes in the chassis.
The method is suitable for being applied to an airborne test system in the field of airborne test systems of aircrafts, and simultaneously provides a basis for researching a high-precision trigger board card based on a MiniVPX architecture.
Drawings
Fig. 1 is a schematic diagram of a trigger card according to an eleventh embodiment;
FIG. 2 is a schematic diagram of a trigger bus structure according to an eleventh embodiment;
FIG. 3 is a schematic diagram of a trigger bus topology according to an eleventh embodiment;
fig. 4 is a schematic diagram of a trigger card control module according to an eleventh embodiment;
fig. 5 is a schematic diagram of a combined triggering principle according to the eleventh embodiment;
fig. 6 is a schematic diagram of a trigger card workflow according to the eleventh embodiment.
Detailed Description
In order to make the advantages and benefits of the technical solution provided by the present invention more apparent, the technical solution provided by the present invention will now be described in further detail with reference to the accompanying drawings, in which:
in a first embodiment, the present embodiment provides a trigger bus unit of an interface module, the unit including: the system comprises a trigger bus, a CPU board card, a trigger board card and at least two functional board cards;
the at least two functional boards are connected in series, the functional boards sequentially send trigger signals to the next functional board, the last functional board sends the trigger signals to the CPU board, and the first functional board is used for responding the trigger signals sent by the trigger boards;
the CPU board card, the trigger board card and the functional board card respectively interact with the trigger bus;
the CPU board card is used for sending a control signal to the trigger board card;
the trigger board card is used for sending trigger signals to the first functional board card and also respectively sending the trigger signals to all the functional board cards in a star connection mode.
In the second embodiment, the triggering bus unit of the interface module provided in the first embodiment is further defined, the last functional board card sends a triggering signal to the CPU board card through a point-to-point connection mode, the CPU board card sends the triggering signal to the triggering board card through a point-to-point connection mode, and the triggering board card sends the triggering signal to the CPU board card through a star connection mode.
In the third embodiment, the trigger bus unit of the interface module provided in the second embodiment is further defined, and the star connection is implemented by a star trigger line.
The fourth embodiment and the present embodiment are further defined on the trigger bus unit of the interface module provided in the third embodiment, where the trigger bus includes an SMBus bus, and the SMBus bus is used to transmit device configuration information collected by the unit.
In a fifth embodiment, the triggering bus unit of the interface module provided in the first embodiment is further defined, where the triggering bus performs information interaction with the CPU board card, the triggering board card and the functional board card through TRIG [2:0 ].
An sixth embodiment provides an interface module, including: the trigger bus unit of the interface module according to any one of the first to second embodiments.
The seventh embodiment provides a high-precision trigger board card based on a MiniVPX architecture, where the board card includes: the device comprises a power module, a clock distribution module, a control module, a storage module, an interface module and a connector;
the interface module is an interface module provided in the sixth embodiment, and the power module is configured to supply power to the clock distribution module, the control module, and the storage module;
the clock distribution module performs information interaction with the connector and is used for multiplexing the received clock signals to each functional board card;
the control module is used for carrying out information interaction with the connector through the interface module and controlling the switching of the clock source of the clock distribution module;
the storage module is used for storing the working information of the trigger board card.
An eighth embodiment provides a method for triggering a high-precision trigger board card, which is characterized in that the method is implemented based on the high-precision trigger board card based on the MiniVPX architecture provided in the seventh embodiment, and the method includes:
step 1: initializing the board;
step 2: collecting the received control signals;
step 3: analyzing the control signal;
step 4: judging whether the control signal is to start acquisition according to the analyzed signal, and if so, starting acquisition of data by the board card;
step 5: collecting a received new control signal II;
step 6: analyzing the second control signal;
step 7: and judging whether the control signal is the end of acquisition according to the analyzed signal, and if so, ending the acquisition of data by the board card.
In the ninth embodiment, the triggering method of the high-precision triggering board card provided in the eighth embodiment is further limited, and in the step 2 and the step 5, the acquisition signal is received through an Aurora bus.
In tenth embodiment, the triggering method of the high-precision triggering board card provided in the eighth embodiment is further limited, and the step 4 specifically includes: further comprises:
step 4.1: and if the judgment result is negative, waiting for a next acquired control signal.
An eleventh embodiment is a specific embodiment provided for the high-precision trigger board card based on MiniVPX architecture provided in the seventh embodiment, and is also used for explaining embodiments one to ten, specifically:
trigger board card structure and functional design based on MiniVPX architecture
The trigger board card structure is shown in fig. 1, and the board card comprises a clock distribution module, a control module, a storage module, a power module and an interface module. The power supply module is composed of a power supply chip and an auxiliary circuit and supplies power to the FPGA and other chips. The memory module is composed of a Flash chip and E 2 The PROM chip stores the program bit stream of the FPGA and the configuration information of the board card. The interface module is composed of a trigger bus and a corresponding communication bus which are defined by the connector.
The clock distribution module consists of a plurality of clock driving chips, clock crystal oscillators and auxiliary circuits thereof, and the clock driving chips carry out multipath distribution on signals generated by the clock crystal oscillators or accurate time signals transmitted by the connectors and enhance the signal driving capability. The clock distribution module also comprises a clock source selection function, and clock signals generated by the crystal oscillator with high stability on the trigger board card and reference clock signals transmitted by the master control board card are selected through FPGA control signals. The output signals of the clock distribution module are transmitted into each functional board card in the chassis through the connector and the chassis backboard, and the output signals comprise reference clock signals with various frequencies and accurate time information signals. The control module of the trigger board card takes the FPGA chip as a core to finish the functions of controlling the clock distribution module, generating various trigger signals and the like. When a test system based on a MiniVPX architecture is started, upper computer software is connected with a main control board card through an Ethernet port, a network discovers each functional board card in a chassis and sends configuration information to the main control board card, and the main control board card sends the configuration information to the power board cards comprising a trigger plate through a communication bus. And then, the upper computer sends control information, the main control board card sends the control information to the trigger board card after receiving the control information, the trigger board card sends a trigger signal, and all the functional board cards in the chassis start to work. When the case is started and the upper computer software does not send control information, the tested equipment sends an external trigger signal to the test system, the waveform on the TRIG trigger bus of the corresponding function board card of the test system is changed, and after the main control board card detects the state change, the data receiving function of the corresponding function board card is started and the state information is stored.
(1) Power supply module
The power module is responsible for supplying power to a circuit on the trigger board card, and the power module carries out secondary conversion on 12V transmitted by a power connector of the MiniVPX framework backboard connector. The first-stage power supply converts the first-stage power supply into 5V, and the second-stage power supply converts the 5V into 3.3V, 1.0V and other voltages to supply power for chips such as a crystal oscillator, a clock driving chip, an FPGA and the like.
(2) Storage module
The memory module consists of a Flash chip and an E chip 2 PROM constitutes, and two chips all are configured through FPGA. The Flash chip is used as a configuration chip of the FPGA and stores firmware logic of the FPGA in a bit file form. E (E) 2 The PROM chip stores the information of the board card transmitted by the FPGA, when the chassis is started, the trigger board card can read Flash in the storage module, meanwhile, the working state information is written into the E2PROM, meanwhile, the upper computer can receive the information of each functional board card, and the corresponding information of the trigger board card is recorded by E 2 The PROM is transmitted into the backboard connector through the FPGA, is transmitted into the main control board card, and is packaged and transmitted to the upper computer after being processed.
(3) Clock distribution module
The clock forwarding module consists of a plurality of crystal oscillators and clock driving chips. The functions are as follows:
1) Multiplexing high-stability clock signals generated by the on-board crystal oscillator, and transmitting the clock signals to a connector connected with the back plate, wherein the clock signals are used as reference clocks of other functional board cards in the chassis;
2) And multiplexing accurate clock signals transmitted by the main control board card, and transmitting the accurate clock signals to each functional board card through the backboard connector. One path of accurate clock signal is transmitted to the MMCX connector of the front panel of the trigger card, and the signal can provide an accurate clock signal for synchronization among multiple cases in a simultaneous application scene of the multiple cases;
3) And providing reference clock signals for the transmission protocols of each functional board card and the main control board card in the chassis. The clock distribution module is also provided with crystal oscillators with the same frequency, the corresponding clock driving chips receive the two clock sources, and the FPGA control signals select one path required as the reference clock of the transmission protocol of the functional board card of the test system.
(4) Interface module
The interface module comprises an interface for communication between the FPGA and the storage module, a trigger bus and a hardware circuit of the communication bus. The interface module and the storage module are communicated through an SPI bus, and the communication bus is a serial LVDS differential line and an SMBus of an Aurora protocol. The trigger bus structure is shown in fig. 2, and the trigger bus is: custom TRIG [2:0], star trigger line, point-to-point trigger line. The three trigger lines are controlled by FPGA, wherein TRIG 2:0 is used as trigger bus, star trigger line is used as high-speed trigger line and connected with each functional board card (including main control board card) in the case via backboard connector. The point-to-point trigger line is a local trigger line and is only connected with the board card of the adjacent slot position in the test system.
FIG. 2 is a schematic diagram of a trigger bus architecture;
the TRIG [2:0] is used as a public trigger line to provide trigger signals among boards for the system, wherein the TRIG [2:0] is used as a trigger bus and connected with each functional board, after an upper computer sends a trigger command, the trigger board transmits the trigger signals to the TRIG [2:0] trigger bus, and after the trigger signals are acquired by the corresponding functional board, corresponding functions are started; when the function board card is triggered by external signals, the trigger signal is transmitted to the TRIG [2:0] trigger bus, and after the trigger board card receives the trigger signal, the trigger board card sends related information to the main control board card through the Aurora serial bus. The star trigger line is used as an independent set of trigger bus, which provides high-precision and low-delay trigger signals for the main control board card and other functional board cards, and meets the high-precision trigger requirement which cannot be met by TRIG 2:0. The wiring of the star trigger line uses a long line matching technology, so that the trigger time delay of the star trigger line of the trigger board reaching each functional board card is ensured to be low, and the trigger precision is high. The star trigger line is designed by adopting LVDS level standard, so that the influence of noise on a trigger signal is reduced. When a high-precision low-delay trigger signal is needed in the system, the trigger plate adopts a star trigger line to send the trigger signal to each functional board card. The point-to-point trigger lines are daisy chain buses, which connect the main control board card and the functional board card 1 of the test system, and provide an additional signal line to the backplane connector. The standby trigger line can be used for transmitting trigger signals and can also be used for communicating with a corresponding functional board card. Meanwhile, the signal wire is output by the FPGA and then led to the MMCX connector to serve as a trigger source/triggered board card, so that the signal wire has expandability, can be connected with a functional board card with the MMCX connector of the board card in other cases or is connected with a non-adjacent functional board card, and the topology of the point-to-point trigger bus is changed. Three trigger bus topology diagrams are shown in fig. 3, and it can be seen that the point-to-point trigger buses form a daisy chain in the whole trigger bus topology, the trigger board card can only trigger the function board card 1, the function board card 1 can only trigger the function board card 2, and so on.
In the usage scenario of multi-channel data acquisition, the designated channels of the designated modules can be triggered in a combined triggering manner. The method is based on a star trigger line and a TRIG trigger line, wherein the star trigger line triggers a specified function board card, and the TRIG trigger line waveform is used as a code to represent the number of a specified channel.
FIG. 3 is a schematic diagram of a trigger bus topology;
in the communication bus, the trigger board card communicates with the master control board card through the Aurora bus. The Aurora bus belongs to a high-speed serial bus, can rapidly transmit data, and transmits control information, configuration information and the like sent to a trigger board card by a main control board card. The SMBus is a low-speed bus, transmits board card configuration information and the like, and can also be used as a standby low-speed communication bus for transmitting data.
(5) Trigger control module
The control module of the trigger board card is connected with the back board connector of the interface module to complete communication with the main control board card in the case; receiving control information transmitted by a main control board card, and generating a corresponding trigger waveform after analysis; and controlling the clock source switching of the clock distribution module. The control module of the trigger board card realizes a logic function based on the FPGA, and comprises a communication function and a trigger signal generation function, and the schematic diagram is shown in fig. 4. The control module receives information transmitted by the Aurora interface and the SMBus interface. The information transmitted by the Aurora interface is control information, and the information transmitted by the SMBus interface is equipment configuration information. The control information transmitted by the main control board card of the case is received, wherein the control information comprises instructions, the types of the instructions comprise triggering instructions, detecting instructions, clock source switching instructions and the like, and the types and the contents of the instructions can be expanded according to the different functional board cards. And analyzing the control information, and realizing the functions of generating waveforms corresponding to the trigger buses to trigger a certain functional board card, detecting the state of the TRIG [2:0] bus or other functions according to the instruction content.
FIG. 4 is a schematic diagram of a trigger card control module;
when the functional board card is a data acquisition board card, the test system of the MiniVPX framework is a data acquisition device, and a combined triggering mode is designed for realizing the single-channel acquisition function of the multi-channel data acquisition device. At this time, the trigger board analyzes the control information, and according to the analyzed trigger instruction, a combined trigger function is used, specifically, a star trigger line is used to trigger the appointed acquisition board, and meanwhile, TRIG [2:0] bus codes are used to represent the corresponding acquisition channels of the appointed acquisition board. When the designated functional board card receives the star trigger signal, the TRIG [2:0] bus is decoded, only the designated channel is triggered and data acquisition is performed, so that the function of independently acquiring data of the specific channel is realized. Because the star trigger line of the trigger board can trigger a plurality of appointed acquisition boards simultaneously, the star trigger line can be used for triggering a plurality of appointed boards in a combined trigger mode, and the corresponding acquisition channels of the corresponding boards are appointed by TRIG [2:0 ]. The trigger of the acquisition board m and the channel n can be realized through a combined trigger mode, and the trigger of the acquisition board m, the k and the channel n can also be realized. Fig. 5 is a schematic diagram of a combined trigger.
FIG. 5 is a schematic diagram of a combined trigger principle;
combined working principle of trigger board card based on MiniVPX architecture
The whole trigger board card function is completed based on the FPGA. The Aurora protocol high-speed serial interface of the FPGA receives configuration information and control information from a master control board card of the MiniVPX chassis, and receives accurate time signals at specified pins. After receiving the trigger instruction of the main control board card, the trigger board card selects a proper trigger bus to transmit a trigger signal according to the requirements of trigger time delay, trigger precision, channel number and the like. When the requirement on the triggering precision is high and the requirement on the triggering time delay is low, the star trigger line is used for triggering the functional board card; when the trigger delay requirement is low, TRIG [2:0] is used for triggering. Because the trigger plate can only trigger the function board card 1 through point-to-point trigger, when only the function board card 1 is triggered and the trigger precision requirement is low, a point-to-point trigger line is used. When the application scene of the function board card is data collection and a certain specific channel of the function board card needs to be triggered, the combined triggering is adopted, namely a star trigger line and a TRIG 2:0 bus are used for triggering simultaneously, wherein the star trigger line triggers a corresponding module, and the waveform of the TRIG 2:0 bus represents the corresponding channel.
After a certain time, the control triggers the bus to restore the initial state. After the function board card in the trigger case is input externally, the information is obtained through the trigger bus TRIG [2:0] trigger board, and the information is transmitted to the main control board card through the Aurora high-speed serial interface. And when the master control board card sends and collects the information of the trigger board card, the trigger board card is used as a master device to transmit the information to the master control board card.
Taking a data acquisition function board as an example, the test platform of the MiniVPX architecture is a data acquisition system. After the system is initialized, the upper computer sends control information to the master control board card of the MiniVPX test system, and after the master control board card is connected to the trigger instruction, the master control board card inputs the trigger instruction and the corresponding function board card serial number through an Aurora transmission pin on the connector. The main control board card of the MiniVPX test system can also send out instructions by itself through a high-speed serial communication bus based on an Aurora protocol, after the trigger board card confirms that the Aurora bus data is received, the information about the trigger mode selection and the corresponding board card in the data is analyzed, whether the instructions start or end is checked, the proper trigger mode and the corresponding triggered board card are selected, and a trigger signal is generated on the corresponding trigger bus.
The trigger card trigger function workflow diagram is shown in fig. 6.
The steps in fig. 6 are described as follows:
(1) After the main control board card is started, triggering the board card to initialize the board card according to configuration information transmitted by the main control board card;
(2) The trigger board card receives information transmitted from the main control board card through an Aurora bus;
(3) After the trigger board card confirms that the receiving is completed, analyzing the received data;
(4) The trigger board card judges whether the trigger instruction is to start acquisition according to the analyzed information, if yes, the trigger board card selects a corresponding trigger bus to generate a trigger signal, the functional board card starts to acquire data, and the trigger bus is restored after a period of time; if not, waiting for the next Aurora bus to transmit information, and not generating a trigger signal;
(5) The trigger board receives information through an Aurora bus;
(6) After the trigger board card confirms that the receiving is completed, analyzing the received data;
(7) The trigger board card judges whether the trigger instruction is the end of acquisition according to the analyzed information, if yes, the corresponding trigger bus is selected, a trigger signal is generated, the functional board card finishes acquisition, and the trigger bus is restored after a period of time; if not, the next Aurora bus transmission is continued to be waited.
The technical solution provided by the present invention is described in further detail through several specific embodiments, so as to highlight the advantages and benefits of the technical solution provided by the present invention, but the specific embodiments described above are not intended to be limiting, and any modification and improvement, combination and equivalent substitution of the embodiments, etc. based on the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims (8)

1. High-precision trigger board card based on MiniVPX framework, its characterized in that, the board card includes: the device comprises a power module, a clock distribution module, a control module, a storage module, an interface module and a connector;
the interface module comprises a trigger bus unit of the interface module, the unit comprising: the system comprises a trigger bus, a CPU board card, a bus trigger board card and at least two functional board cards;
the at least two functional boards are connected in series, the functional boards sequentially send trigger signals to the next functional board, the last functional board sends the trigger signals to the CPU board, and the first functional board is used for responding to the trigger signals sent by the bus trigger boards;
the CPU board card, the bus trigger board card and the functional board card respectively interact with the trigger bus;
the CPU board card is used for sending a control signal to the bus trigger board card;
the bus trigger board card is used for sending trigger signals to the first functional board card and also respectively sending the trigger signals to all the functional board cards in a star connection mode;
the power supply module is used for supplying power to the clock distribution module, the control module and the storage module;
the clock distribution module performs information interaction with the connector and is used for multiplexing the received clock signals to each functional board card;
the control module is used for carrying out information interaction with the connector through the interface module and controlling the switching of the clock source of the clock distribution module;
the storage module is used for storing the working information of the bus trigger board card.
2. The high-precision trigger board card based on the MiniVPX framework according to claim 1, wherein the last functional board card sends a trigger signal to the CPU board card in a point-to-point connection mode, the CPU board card sends the trigger signal to the bus trigger board card in a point-to-point connection mode, and the bus trigger board card sends the trigger signal to the CPU board card in a star connection mode.
3. The MiniVPX architecture-based high-precision trigger card of claim 2, wherein the star connection is implemented by a star trigger line.
4. The MiniVPX architecture-based high-precision trigger card of claim 3, wherein the trigger bus comprises an SMBus bus for transmitting device configuration information collected by the unit.
5. The high-precision trigger board card based on MiniVPX architecture according to claim 1, wherein the trigger bus performs information interaction with the CPU board card, the bus trigger board card and the functional board card through TRIG [2:0 ].
6. The method for triggering the board card with high precision is realized based on the MiniVPX architecture-based high-precision triggering board card as claimed in claim 1, and comprises the following steps:
step 1: initializing the board;
step 2: collecting the received control signals;
step 3: analyzing the control signal;
step 4: judging whether the control signal is to start acquisition according to the analyzed signal, and if so, starting acquisition of data by the board card;
step 5: collecting a received new control signal II;
step 6: analyzing the second control signal;
step 7: and judging whether the second control signal is the acquisition completion or not according to the analyzed signal, and if so, ending the acquisition of data by the board card.
7. The method according to claim 6, wherein in the step 2 and the step 5, the acquisition signal is received through an Aurora bus.
8. The method for triggering the high-precision trigger card according to claim 6, wherein the step 4 is specifically: further comprises:
step 4.1: and if the judgment result is negative, waiting for a next acquired control signal.
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