CN112285530A - Universal testing device for VPX high-speed signal board - Google Patents
Universal testing device for VPX high-speed signal board Download PDFInfo
- Publication number
- CN112285530A CN112285530A CN202011043067.5A CN202011043067A CN112285530A CN 112285530 A CN112285530 A CN 112285530A CN 202011043067 A CN202011043067 A CN 202011043067A CN 112285530 A CN112285530 A CN 112285530A
- Authority
- CN
- China
- Prior art keywords
- vpx
- board
- interface
- data
- core processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
Abstract
The invention discloses a general testing device for a VPX high-speed signal board, and relates to the field of high-speed signal acquisition such as measurement and control communication. The invention is realized by the following technical scheme: the universal computing module is used as a central node of the star switch, the PCIe of the X4 of the connector is connected with the core processing module to complete a control function, the control and state detection of the core processing module and the control and monitoring of an external test instrument are performed, the core processing module interacts with the universal computing module, received information is sent to the signal processing board for processing, a command of a reuse control system is responded through single board software, and different function options are loaded; the core processing module takes three parallel FPGAs as a core, completes analysis distribution of control commands and transmission of signal data streams through the FPGAs, is connected with SRIO signals of the VPX back plate to form an SRIO data transmission network with data interaction, and the FPGAs send data to each other point to point at variable time.
Description
Technical Field
The invention relates to the field of high-speed signal acquisition such as measurement and control communication, and is mainly applied to development and integration of test equipment and ground equipment of data chain terminal products. The VPX framework high-performance signal processing test device can be particularly applied to high-speed signal processing of aerospace and various airborne, shipboard and aircraft-borne equipment.
Background
With the continuous development of test technology, the data transmission bandwidth is also larger and larger. The embedded signal processing platform has an increasing trend of requirements on system processing capacity, data throughput capacity and data transmission bandwidth, and the traditional parallel shared buses such as the VME and the CPCI are increasingly difficult to adapt to the future development requirements of the embedded signal processing platform. Many application fields require that synthetic aperture radars SAR have processing capabilities to enable real-time imaging. Data processors are required to have high I/O throughput, large bus bandwidth, and sufficiently strong computing power. For high-resolution SAR, the improvement of resolution results in exponential increase of data computation and throughput, and in addition, the motion compensation and autofocus processing for obtaining high resolution make the real-time processing scheme design and implementation of SAR very difficult. The prior real-time processing system is generally based on a shared bus (CPC I or VME), which causes a bottleneck of data transmission and has to sacrifice resolution to meet the requirement of real-time processing. In order to solve the problem, later designers add an independent data transmission bus, adopt a point-to-point bus RACE + + as a data bus and a VME as a control bus, and the double-bus design improves the design complexity on one hand and also increases the error probability and the maintenance difficulty of the system on the other hand. Currently, a new VPX standard based on an embedded system is proposed, which has a very large data bandwidth and solves the bottleneck problem of data transmission. At present, parallel shared buses such as VME and CPCI are gradually replaced by high-speed serial buses represented by VPX, which is the first choice for reinforcing embedded platforms due to its advanced bus structure, excellent cold-conducting and shock-resistant performance and high-speed transmission bandwidth. Every system processor in the current VME bus-based radar system array must wait until the processor obtains the total priority to send data. This not only causes the processor to terminate processing of the current data block, but also terminates processing of the incoming data by the processor.
The VPX high-speed signal acquisition processing card is a core board card of a VPX embedded signal processing platform for providing access and processing of analog signals. The high-performance signal processing platform based on the 3UVPX architecture comprises an onboard 2-chip multi-core DSP processor, a large-capacity DDR3 cache and a large-capacity NandFlash memory, and is provided with 4 paths of gigabit Ethernet ports, supports a TCP/IP protocol, and 1 path of x4 SRIO is connected to a backboard. The 3U module adopts two pieces of TI KeyStone series multi-core floating point/fixed point operation DSPTMS320C6678 as a main processing unit, high-speed interconnection is carried out between the two pieces of DSP through Hyper, SRIO of the two pieces of DSP are respectively connected to a backboard, and high-speed SRIO interconnection between boards is realized. VPX may support various high speed bus protocols such as serial RapidIO, PCI-E, 10G Ethernet, infiniband, etc. Through the protocols, a high-speed channel can be formed with other IO boards or CPU boards in the chassis.
The VPX interface supports standard boards of two forms of 3U and 6U. The general 6UVPX board cards include 1 public connector P0 and 6 self-defining connectors P1-P6, P0 accomplishes the control function, and the pin includes power pin, control pin and test pin, and in the debugging test process of system module level, VPX general signal processing module needs to possess the test debugging condition before the complete machine equips, accomplishes the state confirmation of module level, reaches the complete machine equips the condition. VPX signal integrity on the backplane must be addressed to avoid interoperability issues, which become increasingly severe as higher serial baud rates are moved. VPX systems are typically deployed in the worst case environment with hundreds of pins in the connector pin field, and improperly inserted pins can cause system failure requiring the backplane to be detected and repaired before it leaves the production environment. Over time, the compliant pins may damage the connector and PCB from shock and vibration. Causing wear on the protective surface of the PCB and possibly shorting to another copper component. The pin may become disengaged from the connector and become a floating object, which may cause a short circuit between two other compatible pins. To ensure that the back-plate operates as designed and the final stage of operation is the production and testing stage. For days, weeks, and months of engineering, signal integrity simulations, PCB design, and post-simulation are all spent adjusting the PCB design to achieve optimal performance. If the connector pins are not properly inserted into the PCB holes, several months of engineering work may quickly be reversed. Processing high speed VPX backplanes requires a great deal of expertise. The universal VPX high-speed signal board testing device is used for generating various excitation signals and digital bus interfaces, automatically testing the VPX universal signal processing module, evaluating the performance of the interfaces and the processing capacity, detecting, recording and analyzing parameters of signals output by the module, completing index conformance analysis, and supporting the whole machine debugging and testing of the beam forming measurement and control system.
Disclosure of Invention
Aiming at the test problems of long engineering test time, various interfaces of the board to be tested, high complexity of VPX signal integrity test and the like, the invention provides a universal test device for a VPX high-speed signal board and a universal test device for the VPX high-speed signal board, which have the advantages of simple realization, good magnetic compatibility, high universality, quick interface test, functional coverage, defect diagnosis and performance test capability.
The above object of the present invention can be achieved by a test apparatus for a VPX high-speed signal board, comprising: the general computer module and the core processing module are inserted in a VPX back plate VPX slot in a case, and the general computer module and the core processing module are characterized in that: the universal computing module is used as a central node of the star switch, the PCIe of the X4 of the P1 connector of the common connector P0 and the P1-P6 self-defined connectors is connected with the core processing module to complete a control function, the core processing module is controlled and monitored by state detection and an external test instrument, the core processing module interacts with the universal computer module, received information is sent to the signal processing board for processing, and different function options are loaded by responding to a command of a reuse control system through single board software; the core processing module takes three Field Programmable Gate Arrays (FPGA) connected in parallel as a core, completes analysis distribution of control commands and transmission of signal data streams through the FPGA, is connected with SRIO signals of a VPX backplane to form a data interactive SRIO data transmission network, mutually transmits data in a point-to-point mode at variable time, uses upper computer single board software to test a signal processing board card, automatically tests serial RapidIO interfaces applied to a serial backplane, a DSP and a related serial data plane connection and based on functional performance indexes of packet-switched high-speed interconnection SRIO, and simultaneously detects parameters of signals output by the module, And recording and analyzing, and completing index conformance analysis and performance evaluation of the interface and the processing capacity.
Compared with the prior art, the invention has the beneficial effects that:
the method is simple to implement, good in magnetic compatibility and high in universality. The general computer module and the core processing module are inserted into VPX slots of a back plate in a case conforming to the OpenVPX standard to support 7 plate positions and special plate positions for a power supply, the general computer module is used for providing an operation-friendly and easy-to-use user interface, and the functional performance indexes of PCIE, GTX, stray wires, optical modules, clock management functions, Ethernet switching functions, network port performance, LVDS, SRIO and the like of a VPX board to be tested are tested through a human-computer interaction interface, so that authorized checking of user option and loading control of option and the like can be completed, the general computer module has the functions of covering, defect diagnosis and performance testing capability, the working efficiency is improved, and meanwhile, the product maturity can be greatly and rapidly improved. The mainboard position and 5 function board positions.
The flexibility is high. The invention mainly uses a high-new energy processing computer and a plurality of universal expansion interfaces to form a universal computing module as a central node of star exchange, controls and detects the state of the core processing module through PCIe of X4 of a P1 connector and the core processing module, and controls and monitors the external test instrument through VPX2-7 human-computer interaction interface, has high flexibility in finishing authorization check of user option and loading control of option, brings ultra-strong stability of the system through excellent heat dissipation performance and bus reinforcement performance of VPX, and can transmit signals from one slot to another slot through an interconnection cable of the system, and the signals are transmitted or accessed through a J1 structure connector through a multi-Gigg-SMA cable adapter. The VPX signal processing module has the functional characteristics of flexibility, expansibility, easy implementation, small volume, light weight, low power consumption and the like, and supports the synchronous automation performance and function evaluation of a plurality of VPX general signal processing modules.
High universality and quick interface test. The invention adopts a general computation module as a central node of star exchange, controls and detects the state of a core processing module and controls and monitors an external test instrument by connecting PCIe of X4 of P1 connectors of P0 and P1-P6 self-defining connectors with the core processing module, the core processing module interacts with a general computer module, sends received information to a signal processing board for processing, loads different function selection pieces by responding to a command of a reuse control system through single board software, adopts Rapid IO, PCIE and other high-speed data transmission, not only has quick interface test, but also can test a certain connector interface of a signal processing board to be tested in a time sharing way, tests any signal to define the target of the self-defining connectors, ensures that the data among board cards can be transmitted in a large quantity, and reliably completes the real-time processing of high-speed signals, the method can be applied to single board testing, module testing verification, algorithm function verification and chip prototype verification.
The method has the capabilities of function coverage, defect diagnosis and performance test. The invention takes three parallel FPGAs as a core, completes the analysis distribution of control commands and the transmission of signal data streams through the FPGAs, and is connected with SRIO signals of a VPX backboard to form an SRIO data transmission network with data interaction, the FPGAs send data to each other point-to-point at variable time, upper computer single board software is used for testing a signal processing board card, functional performance indexes of PCIE, GTX, stray wires, optical modules, clock management functions, Ethernet exchange functions, network port performance, LVDS, SRIO and the like of the VPX universal signal processing module to be tested and the VPX board card are automatically tested, and parameters of signals output by the modules are detected, recorded and analyzed, thereby completing index conformity analysis and performance evaluation of interfaces and processing capacity, and having the functions of covering, defect diagnosis and performance test capacity.
The connector of the general VPX high-speed signal board testing device P0 is arranged on the movable guide rail and can be kept at any distance from other connectors. Other functional class connectors are divided by function.
The invention is suitable for scenes such as software radio, radar or sonar signal processing, intelligent signal analysis, high-speed graphic image processing and the like. Because each processing node in the system can directly communicate point to point, the software design is provided with greater flexibility. The scheme can meet the real-time processing requirement of the high-resolution radar, and can be widely applied to signal processing systems with high requirements of various system radars, electronic countermeasures, images and the like.
Drawings
The patent is further described below with reference to the drawings and examples.
FIG. 1 is a schematic block diagram of a general test device for VPX high-speed signal boards according to the present invention;
FIG. 2 is a hardware exploded schematic of FIG. 1;
the technical scheme of the invention is further described in detail in the following with reference to the attached drawings.
Detailed Description
See fig. 1. In a preferred embodiment described below, a test apparatus for testing a VPX high speed signal board in general, includes: the general computer module and the core processing module are plugged in a VPX back plate VPX slot in the case, wherein: the universal computing module is used as a central node of the star switch, is connected with the core processing module through PCIe of X4 of a P1 connector, completes control and state detection of the core processing module and control and monitoring of an external test instrument, interacts with the universal computing module, sends received information to the signal processing board for processing, responds to a command of a reuse control system through single board software, and loads different function options; the core processing module takes three Field Programmable Gate Arrays (FPGA) connected in parallel as a core, completes analysis distribution of control commands and transmission of signal data streams through the FPGA, is connected with SRIO signals of a VPX backboard to form a data interactive SRIO data transmission network, mutually transmits data in a point-to-point mode at variable time, tests a signal processing board card by using upper computer single board software, automatically tests functional performance indexes of PCIE, GTX, stray wires, an optical module, a clock management function, an Ethernet switching function, network port performance, LVDS, SRIO and the like of the VPX general signal processing module to be tested and the VPX board card, and simultaneously detects, records and analyzes parameters of signals output by the module to complete index conformance analysis and performance evaluation of interfaces and processing capacity.
The core processing unit provides high-speed and resource-rich programmable chipset structure test excitation and comparison result data. The single board software loading algorithm verification and chip prototype verification program on the core processing unit can respond to the command of the reuse control system, and load different functional options to interact with the general computer module through high-speed connection interfaces such as GTX/GTH/LVDS and the like provided between the core processing subsystem and the interface conversion subsystem. The core processing unit is also provided with abundant clock processing resources, and a PLL (phase locked loop) provides clocks with different frequencies and requirements for any interface unit. The clock control unit is a variable component and is used for being matched with the clock processing part to generate various abundant clock frequency points. The power supply control unit is used for meeting different power supply function requirements of different single boards.
The core processing module comprises: the phase-locked loop PLL provides clock control units with different frequencies and clocks for any interface unit, the FPGA core processing module is used for being matched with the clock processing unit to generate various abundant clock frequency points, and the power supply control unit meets different power supply function requirements of different single boards, wherein the clock control unit is a variable component, and abundant clock processing resources are arranged on the variable component. The VPX case adopts a high-strength aluminum-magnesium alloy profile 5U reinforced case, a power supply adopts a dual-redundancy power supply design, a customized VPX back plate is installed in the VPX case and supports 5 standard 6U VPX board cards, the VPX board cards are installed through a positioning pin and a guide rail, the board cards are connected through a 6U 5-groove VPX back plate, an interface board completes external and internal information transmission and instruction interaction, and the interface board and a signal processing board perform image broadcast transmission and instruction information point-to-point interaction through an SRIO network. The front part of the case is provided with a 6U standard horizontal plug-in card supporting high-speed Serial protocols such as Serial Rapid IO, PCI Express and the like, a high-performance air-cooling heat dissipation design meeting high-performance application requirements is adopted, and a cold-guiding card frame in the case is used for installing a heat dissipation cold-guiding card. The VPX case power supply adopts a customized module power supply, supports 18-36V wide power supply input, works stably and reliably, adopts a stud wiring mode in a power supply mode, and meets the requirements of severe environments such as impact, vibration and the like.
The FPGA core processing module loads a single board software algorithm verification and chip prototype verification program through high-speed connection interfaces such as GTX/GTH/LVDS/PCIE/RIO/discrete lines and the like, and realizes data interaction and internal data communication through an internal SRIO network, a PCIE network, a socket IO interface, a CAN interface, an RS-422 interface, an LVDS interface and a GPIO interface through each board card backplane connector and a VPX backplane. And the data interaction between the FPGAs on the interface board is realized by designing the full network structure of the SRIO by utilizing the SRIO exchange chip and the VPX back plate. The FPGA core processing module is configured with different data flow modes, so that the interface board sends the same data to 3 FPGAs in a broadcasting mode, broadcast transmission of images and point-to-point interaction of instruction information are reliably carried out through an SRIO network, instruction distribution and image transmission between the display control system and the photoelectric front end are completed, the image information is processed in real time, data transmission among the multiple signal processing boards is realized through a PCIE network, the data are input into the interface board, then the interface board transmits the processed data to the multiple signal processing boards, and the signal processing boards transmit the processed data to the interface board for output. SRIO is a serial RapidIO interface that interfaces to serial backplanes, DSPs, and related serial data planes. The serial RapidIO comprises a 3-layer structure protocol, namely a physical layer, a transmission layer and a logic layer. Physical layer definition electrical characteristics, link control, low level error management, underlying flow control data; the transport layer defines packet switching, routing and addressing mechanisms; the logical layer defines the overall protocol and packet format. The minimum pin number can be realized, DMA transmission is adopted, and complex extensible topology and multipoint transmission are supported; the optional four speeds of 1.25Gbps, 2.5Gbps, 3.125Gbps and 5Gbps can meet different application requirements.
See fig. 2. The chassis back plate is composed of a P0 connector powered by a direct current power supply and other functional P1-P6 connectors, and the 3U-sized VPX board card comprises 1 public connector P0 and 2 custom connectors P1, P2 and P0 connectors and movable guide rails, and can keep any distance from other P1-P6 connectors. The P0 connector provides three main power signals of Vsl (12V), Vs2(3.3V) and Vs3(5V) and three auxiliary power signals of +12V _ AUX, -12V _ AUX and 3.3V _ AUX, the other functional type P1-P6 connectors are divided into connectors such as SRIO, LVDS, electro-optical ports, GTX and gigabit network interfaces by functions, the P1-P6 comprises custom pins required by a user, and each connector can test a certain connector interface of a signal processing board to be tested in a time-sharing mode and test the target of the VPX high-speed signal board.
The general computing module mainly comprises a high-new-energy processing computer and a plurality of general expansion interfaces. The general computer module and the core processing module are inserted into a VPX slot of a backboard conforming to the OpenVPX standard in a case, and the VPX slot supports 7 board positions, 1 power supply special board position, 1 mainboard board position and 6 function board positions. The general computation module is used as a central node of the star switch and is connected with the core processing module through PCIe of X4 of a P1 connector, the VPX2-7 human-computer interaction interface is provided, the core processing module is controlled and state is detected, an external test instrument is controlled and monitored, test excitation and comparison result data are constructed by a programmable chipset of the core processing module, authorization check of user option and loading control of option are completed.
All features disclosed in this specification may be combined in any combination, except features and/or steps that are mutually exclusive. The above preferred embodiments are only intended to illustrate the technical solution of the present invention and not to limit, and although the present invention has been described in detail by the above preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention defined by the claims.
Claims (10)
1. A general test device for VPX high-speed signal boards comprises: the general computer module and the core processing module are inserted in a VPX back plate VPX slot in a case, and the general computer module and the core processing module are characterized in that: the universal computing module is used as a central node of the star switch, the PCIe of the X4 of the P1 connector of the common connector P0 and the P1-P6 self-defined connectors is connected with the core processing module to complete a control function, the core processing module is controlled and monitored by state detection and an external test instrument, the core processing module interacts with the universal computer module, received information is sent to the signal processing board for processing, and different function options are loaded by responding to a command of a reuse control system through single board software; the core processing module takes three Field Programmable Gate Arrays (FPGA) connected in parallel as a core, completes analysis distribution of control commands and transmission of signal data streams through the FPGA, is connected with SRIO signals of a VPX backplane to form a data interactive SRIO data transmission network, mutually transmits data in a point-to-point mode at variable time, uses upper computer single board software to test a signal processing board card, automatically tests serial RapidIO interfaces applied to a serial backplane, a DSP and a related serial data plane connection and based on functional performance indexes of packet-switched high-speed interconnection SRIO, and simultaneously detects parameters of signals output by the module, And recording and analyzing, and completing index conformance analysis and performance evaluation of the interface and the processing capacity.
2. The VPX high speed signal board universal test apparatus of claim 1, wherein: the core processing unit provides high-speed and resource-rich programmable chipset structure test excitation and comparison result data.
3. The VPX high speed signal board universal test apparatus of claim 1, wherein: the single board software loading algorithm verification and chip prototype verification program on the core processing unit responds to the command of the reuse control system, and different functional options are loaded to interact with the general computer module through a GTX/GTH/LVDS high-speed connection interface provided between the core processing subsystem and the interface conversion subsystem.
4. The VPX high speed signal board universal test apparatus of claim 1, wherein: the core processing unit is also provided with abundant clock processing resources, and a phase-locked loop PLL (phase-locked loop) provides clocks with different frequencies and requirements for any interface unit.
5. The VPX high speed signal board universal test device of claim 4, wherein: the clock control unit is a variable component and is used for being matched with the clock processing part to generate various abundant clock frequency points.
6. The VPX high speed signal board universal test apparatus of claim 1, wherein: the core processing module comprises: the phase-locked loop PLL provides clock control units with different frequencies and clocks for any interface unit, the FPGA core processing module which is matched with the clock processing unit to generate various abundant clock frequency points and the power supply control unit which meets different power supply function requirements of different single boards are matched, wherein the clock control unit is a variable component, and abundant clock processing resources are arranged on the variable component.
7. The VPX high speed signal board universal test apparatus of claim 1, wherein: the VPX case adopts a high-strength aluminum-magnesium alloy profile 5U reinforced case, a power supply adopts a dual-redundancy power supply design, a customized VPX back plate is installed in the VPX case and supports 5 standard 6U VPX board cards, the VPX board cards are installed through a positioning pin and a guide rail, the board cards are connected through a 6U 5-groove VPX back plate, an interface board completes external and internal information transmission and instruction interaction, and the interface board and a signal processing board perform image broadcast transmission and instruction information point-to-point interaction through an SRIO network.
8. The VPX high speed signal board universal test apparatus of claim 1, wherein: the front part of the case is provided with a 6U standard horizontal plug-in card supporting Serial Rapid IO and PCI Express high-speed Serial protocols, a high-performance air-cooling heat dissipation design meeting high-performance application requirements is adopted, and a cold-guiding card frame in the case is used for installing a heat dissipation cold-guiding card.
9. The VPX high speed signal board universal test apparatus of claim 1, wherein: the FPGA core processing module loads a single board software algorithm verification and chip prototype verification program through a GTX/GTH/LVDS/PCIE/RIO/discrete line high-speed connection interface, realizes data interaction and internal data communication of an internal SRIO network, a PCIE network, a socket IO interface, a CAN interface, an RS-422 interface, an LVDS interface and a GPIO interface through each board card backplane connector and a VPX backplane, and realizes data interaction between FPGAs on an interface board by designing a whole network structure of SRIO through an SRIO exchange chip and the VPX backplane.
10. The VPX high speed signal board universal test apparatus of claim 1, wherein: the FPGA core processing module is configured with different data flow modes, so that the interface board sends the same data to 3 FPGAs in a broadcasting mode, broadcast transmission of images and point-to-point interaction of instruction information are reliably carried out through an SRIO network, instruction distribution and image transmission between the display control system and the photoelectric front end are completed, the image information is processed in real time, data transmission among the multiple signal processing boards is realized through a PCIE network, the data are input into the interface board, then the interface board transmits the processed data to the multiple signal processing boards, and the signal processing boards transmit the processed data to the interface board for output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011043067.5A CN112285530A (en) | 2020-09-28 | 2020-09-28 | Universal testing device for VPX high-speed signal board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011043067.5A CN112285530A (en) | 2020-09-28 | 2020-09-28 | Universal testing device for VPX high-speed signal board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112285530A true CN112285530A (en) | 2021-01-29 |
Family
ID=74421643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011043067.5A Pending CN112285530A (en) | 2020-09-28 | 2020-09-28 | Universal testing device for VPX high-speed signal board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112285530A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110009552A (en) * | 2019-04-11 | 2019-07-12 | 湖南必然信息技术有限公司 | A kind of high bandwidth performance processing method of image big data |
| CN111061198A (en) * | 2019-12-31 | 2020-04-24 | 南京长峰航天电子科技有限公司 | Feed control system for updating data in real time and data updating method |
| CN113259205A (en) * | 2021-07-01 | 2021-08-13 | 湖南博匠信息科技有限公司 | Method and system for testing internal interconnection interface of multi-board system |
| CN113820586A (en) * | 2021-08-30 | 2021-12-21 | 南京国电南自电网自动化有限公司 | Single board automatic test system and method suitable for relay protection device |
| CN114567899A (en) * | 2022-03-14 | 2022-05-31 | 中科南京移动通信与计算创新研究院 | Terminal detection device based on VPX framework and signal processing method |
| CN114817111A (en) * | 2022-04-28 | 2022-07-29 | 中国科学院计算技术研究所 | Embedded intelligent computing device supporting multi-card parallel |
| CN115237849A (en) * | 2022-09-23 | 2022-10-25 | 北京东远润兴科技有限公司 | Dynamically reconfigurable and heterogeneous computing module and computing device |
| CN115509987A (en) * | 2022-09-16 | 2022-12-23 | 哈尔滨工业大学 | Interface module, trigger unit, high-precision trigger board card based on MiniVPX architecture and trigger method |
| CN116930722A (en) * | 2023-09-12 | 2023-10-24 | 悦芯科技股份有限公司 | Method and system for testing memory chip wafer |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004199834A (en) * | 2002-12-20 | 2004-07-15 | Fujitsu Ltd | Semiconductor device, semiconductor storage device, and test method therefor |
| US20120281706A1 (en) * | 2011-05-06 | 2012-11-08 | Puneet Agarwal | Systems and methods for cloud bridging between intranet resources and cloud resources |
| CN103678212A (en) * | 2013-11-18 | 2014-03-26 | 航天恒星科技有限公司 | Universal interface detection device based on VPX framework |
| CN105335327A (en) * | 2015-10-13 | 2016-02-17 | 电子科技大学 | Reconfigurable/dual redundancy VPX3U signal processing carrier board based on Soc |
| CN206584345U (en) * | 2016-12-09 | 2017-10-24 | 中国电子科技集团公司第三十研究所 | A kind of general-utility test platform for embedded computer board reliability test |
| CN208092195U (en) * | 2018-01-30 | 2018-11-13 | 重庆秦嵩科技有限公司 | VPX tests cabinet |
| CN109116314A (en) * | 2018-07-06 | 2019-01-01 | 中国电子科技集团公司第十四研究所 | VPX module universal testing method |
| CN208971541U (en) * | 2018-12-07 | 2019-06-11 | 苏州中科安源信息技术有限公司 | Portable heating based on VPX framework decrypts test equipment |
| CN209356635U (en) * | 2018-12-12 | 2019-09-06 | 浪潮集团有限公司 | A kind of radar based on VPX framework calculates the test device of board |
| CN111123073A (en) * | 2019-12-27 | 2020-05-08 | 天津芯海创科技有限公司 | Quick self-checking device of hardware board card |
| CN111339008A (en) * | 2020-02-28 | 2020-06-26 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | VPX platform architecture integrated radio frequency system |
-
2020
- 2020-09-28 CN CN202011043067.5A patent/CN112285530A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004199834A (en) * | 2002-12-20 | 2004-07-15 | Fujitsu Ltd | Semiconductor device, semiconductor storage device, and test method therefor |
| US20120281706A1 (en) * | 2011-05-06 | 2012-11-08 | Puneet Agarwal | Systems and methods for cloud bridging between intranet resources and cloud resources |
| CN103678212A (en) * | 2013-11-18 | 2014-03-26 | 航天恒星科技有限公司 | Universal interface detection device based on VPX framework |
| CN105335327A (en) * | 2015-10-13 | 2016-02-17 | 电子科技大学 | Reconfigurable/dual redundancy VPX3U signal processing carrier board based on Soc |
| CN206584345U (en) * | 2016-12-09 | 2017-10-24 | 中国电子科技集团公司第三十研究所 | A kind of general-utility test platform for embedded computer board reliability test |
| CN208092195U (en) * | 2018-01-30 | 2018-11-13 | 重庆秦嵩科技有限公司 | VPX tests cabinet |
| CN109116314A (en) * | 2018-07-06 | 2019-01-01 | 中国电子科技集团公司第十四研究所 | VPX module universal testing method |
| CN208971541U (en) * | 2018-12-07 | 2019-06-11 | 苏州中科安源信息技术有限公司 | Portable heating based on VPX framework decrypts test equipment |
| CN209356635U (en) * | 2018-12-12 | 2019-09-06 | 浪潮集团有限公司 | A kind of radar based on VPX framework calculates the test device of board |
| CN111123073A (en) * | 2019-12-27 | 2020-05-08 | 天津芯海创科技有限公司 | Quick self-checking device of hardware board card |
| CN111339008A (en) * | 2020-02-28 | 2020-06-26 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | VPX platform architecture integrated radio frequency system |
Non-Patent Citations (3)
| Title |
|---|
| 王燕 等: "基于VPX总线的高速数字电路测试系统研究及应用", 《计算机测量与控制》, vol. 24, no. 1, pages 4 - 6 * |
| 苟欢敏 等: "基于VPX的6U信号处理系统设计", 《电子与封装》, vol. 14, no. 11, pages 21 - 25 * |
| 郭静: "FPGA+SRIO+VPX架构的多路高速互连信息处理系统实现", 《重庆工商大学学报(自然科学版)》, vol. 27, no. 4, pages 46 - 51 * |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110009552A (en) * | 2019-04-11 | 2019-07-12 | 湖南必然信息技术有限公司 | A kind of high bandwidth performance processing method of image big data |
| CN110009552B (en) * | 2019-04-11 | 2023-08-22 | 深圳市玄武科技信息有限公司 | High-bandwidth performance processing method for large image data |
| CN111061198B (en) * | 2019-12-31 | 2023-03-03 | 南京长峰航天电子科技有限公司 | Feed control system for updating data in real time and data updating method |
| CN111061198A (en) * | 2019-12-31 | 2020-04-24 | 南京长峰航天电子科技有限公司 | Feed control system for updating data in real time and data updating method |
| CN113259205A (en) * | 2021-07-01 | 2021-08-13 | 湖南博匠信息科技有限公司 | Method and system for testing internal interconnection interface of multi-board system |
| CN113259205B (en) * | 2021-07-01 | 2021-12-03 | 湖南博匠信息科技有限公司 | Method and system for testing internal interconnection interface of multi-board system |
| CN113820586A (en) * | 2021-08-30 | 2021-12-21 | 南京国电南自电网自动化有限公司 | Single board automatic test system and method suitable for relay protection device |
| CN114567899A (en) * | 2022-03-14 | 2022-05-31 | 中科南京移动通信与计算创新研究院 | Terminal detection device based on VPX framework and signal processing method |
| CN114567899B (en) * | 2022-03-14 | 2023-12-19 | 中科南京移动通信与计算创新研究院 | Terminal detection device and signal processing method based on VPX architecture |
| CN114817111B (en) * | 2022-04-28 | 2023-08-29 | 中国科学院计算技术研究所 | Embedded intelligent computing device supporting multi-card parallelism |
| CN114817111A (en) * | 2022-04-28 | 2022-07-29 | 中国科学院计算技术研究所 | Embedded intelligent computing device supporting multi-card parallel |
| CN115509987B (en) * | 2022-09-16 | 2023-06-02 | 哈尔滨工业大学 | High-precision trigger board card based on MiniVPX architecture and trigger method |
| CN115509987A (en) * | 2022-09-16 | 2022-12-23 | 哈尔滨工业大学 | Interface module, trigger unit, high-precision trigger board card based on MiniVPX architecture and trigger method |
| CN115237849A (en) * | 2022-09-23 | 2022-10-25 | 北京东远润兴科技有限公司 | Dynamically reconfigurable and heterogeneous computing module and computing device |
| CN116930722A (en) * | 2023-09-12 | 2023-10-24 | 悦芯科技股份有限公司 | Method and system for testing memory chip wafer |
| CN116930722B (en) * | 2023-09-12 | 2024-01-05 | 悦芯科技股份有限公司 | Method and system for testing memory chip wafer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112285530A (en) | Universal testing device for VPX high-speed signal board | |
| CN102129274B (en) | Server, server subassembly and fan speed control method | |
| US7734858B2 (en) | Fabric interposer for blade compute module systems | |
| CN101291261B (en) | Method and system for in-board device testing | |
| CN109885526B (en) | Information processing platform based on OpenVPX bus | |
| CN110717853B (en) | Optical image processing system based on embedded GPU | |
| CN110865958A (en) | LRM-based integrated switching management module design method | |
| CN116680220B (en) | Signal transceiver and signal receiving and transmitting system | |
| CN102402474B (en) | Prototype verification device for programmable logic devices | |
| CN117111693A (en) | Server case system, method and device for designing server case system | |
| CN100541387C (en) | A kind of server system based on the Opteron processor | |
| US11009547B2 (en) | Device and method for testing a computer system | |
| CN109783286B (en) | Built-in test method, test device, terminal equipment and storage medium | |
| CN108196527B (en) | Test verification system of FPGA and DSP tightly coupled architecture capable of being reconfigured | |
| CN109240972A (en) | A kind of GPU board and the VPX signal processing cabinet using the board | |
| CN113568847B (en) | Network card and processor interconnection device and server | |
| CN216352292U (en) | Server mainboard and server | |
| CN107391321B (en) | Electronic computer single board and server debugging system | |
| CN209860930U (en) | Modular ubiquitous power Internet of things platform based on data exchange of hybrid communication network | |
| CN113534919A (en) | Low-delay acquisition and operation system based on VPX framework | |
| CN104572390B (en) | A kind of method of testing based on domestic CPU multi-unit server computing unit of soaring | |
| CN115877180A (en) | Testing device | |
| CN216209855U (en) | Reconnaissance surveillance radar module level detector | |
| CN208834296U (en) | A kind of GPU board and the VPX signal processing cabinet using the board | |
| CN112399175B (en) | Test platform of ARINC818 daughter card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |