CN115877180A - Testing device - Google Patents

Testing device Download PDF

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Publication number
CN115877180A
CN115877180A CN202211553996.XA CN202211553996A CN115877180A CN 115877180 A CN115877180 A CN 115877180A CN 202211553996 A CN202211553996 A CN 202211553996A CN 115877180 A CN115877180 A CN 115877180A
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interface
test
pcie
test circuit
low
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CN202211553996.XA
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卢一锐
付波
张飞
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Huaqin Technology Co Ltd
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Huaqin Technology Co Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

A test device is applied to electronic technology and used for carrying out single-board function test on a backboard to be tested in a low-cost mode. The test device comprises a test chip, a test circuit and a backboard to be tested. The test chip is connected with the slot position of the test circuit, the test circuit comprises a first interface, the to-be-tested backboard comprises a second interface, the first interface is connected with the second interface through a bus, and the first interface and the second interface both comprise PCIe interfaces. In the scheme, the connected test chip and the test circuit are equivalent to a GPU module, and the first interface and the second interface are connected through the bus, namely the test circuit is connected with the backboard to be tested, so that the function test of the backboard to be tested can be realized. When the single board function test is carried out on the backboard to be tested, when the plugging times of the first interface of the test circuit reach the service life of the test circuit, the single board function test can be continued only by replacing the test circuit without replacing a test chip.

Description

Testing device
Technical Field
The invention relates to the technical field of electronics, in particular to a testing device.
Background
A Graphics Processing Unit (GPU) server, also called a GPU server, has the advantages of high computation speed, high stability, support for elastic change, and the like, and is widely applied to the technical field of computer science. The GPU server includes a motherboard, a backplane, an input/output (IO) board, and a GPU module. Currently, GPU servers use peripheral component interconnect express (PCIe) technology for signaling using PCIe generation 5. PCIe technology is a high-speed serial computer expansion bus standard technology, which distributes independent channel bandwidth to connected devices through high-speed serial point-to-point dual-channel high-bandwidth transmission, and supports functions of active power management, error reporting, end-to-end reliable transmission, hot plug, quality of service and the like. Compared to the 4 th generation PCIe technology, the 5 th generation PCIe technology (i.e., PCIe5.0) increases the transmission rate of signals from 16GT/s to 32GT/s.
Since the GPU server transmits signals faster using PCIe5 th generation technology, higher requirements are placed on the performance of the backplane in the GPU server. Therefore, the backplane is a board card capable of transmitting high-speed signals of pci 5.0. In the production process of the backplane, a Board Function Test (BFT) needs to be performed on the produced backplane. During testing, the backboard to be tested needs to be tested by matching with the GPU module, and the backboard to be tested needs to be connected with the GPU module once when each backboard to be tested is tested. However, the service life of the interface for the GPU module connected to the backplane to be tested is about 200 times, so that one GPU module needs to be replaced every 200 test backplanes. At present, the purchase cost of one GPU module is about 150 ten thousand yuan, and thus, a large amount of capital cost is consumed for testing the backplane to be tested by using the GPU module.
In summary, a testing apparatus for testing the function of the backplane under test in a low cost manner is needed.
Disclosure of Invention
The invention provides a testing device which is used for carrying out single-board function testing on a backboard to be tested in a low-cost mode.
In a first aspect, the present invention provides a test apparatus. The test device comprises a test chip, a test circuit and a backboard to be tested. The test chip is connected with the slot position of the test circuit, the test circuit comprises a first interface, the backboard to be tested comprises a second interface, the first interface is connected with the second interface through a bus, and the first interface and the second interface both comprise PCIe interfaces.
In the embodiment of the invention, the connected test chip and the test circuit are equivalent to a GPU module, and the first interface and the second interface are connected through the bus, namely the test circuit is connected with the backboard to be tested, so that the function test of the backboard to be tested can be realized. In the testing process, when the plugging times of the first interface of the testing circuit connected with the backboard to be tested reach the service life of the backboard to be tested, the testing circuit is only required to be replaced, the testing chip is reconnected with the slot position of the replaced testing circuit, namely, the slot position is equivalent to a new GPU module, and the backboard to be tested can be subjected to single board function testing by connecting the first interface of the replaced testing circuit with the second interface of the backboard to be tested. In other words, when the single board function test is performed on the backplane to be tested, when the plugging times of the first interface of the test circuit reach the service life of the test circuit, the single board function test can be continued only by replacing the test circuit without replacing the test chip.
Optionally, the PCIe interface is a PCIe5.0 interface. By using the PCIe5.0 interface, the PCIe interface can be made to provide a faster signaling rate.
Optionally, the test chip is a CX7 chip. By using the CX7 chip supporting the PCIe5.0 technology, whether the backboard to be tested can transmit the high-speed signal of the PCIe5.0 or not, and the signal integrity and the signal connectivity during transmission can be tested.
Optionally, the test chip and the test circuit are used to implement GPU functionality. In the embodiment of the invention, the test chip and the test circuit for realizing the GPU function can replace a GPU module to carry out single-board function test on the backboard to be tested, so that the single-board function test can be carried out on the backboard to be tested in a low-cost mode.
Optionally, the first interface and/or the second interface includes at least two PCIe interfaces.
Optionally, the slot of the test circuit includes a PCIe slot corresponding to the PCIe interfaces on the test circuit one to one, one end of the PCIe slot is connected to the PCIe interface on the test circuit, and the other end of the PCIe slot is used to connect the test chip. In the embodiment of the invention, the test chip communicates with the test circuit through the PCIe slot position.
Optionally, the first interface and the second interface further include low-speed signal interfaces, and the low-speed signal interfaces include PCIe pins and low-speed signal pins.
In the embodiment of the invention, the low-speed signal pin can be used for transmitting a low-speed signal. The low-speed signal pin is arranged in the test circuit, so that the test circuit can transmit low-speed signals, the test device can realize the transmission of the low-speed signals, and can test the signal integrity and the signal connectivity of the backboard to be tested when the backboard to be tested transmits the low-speed signals.
Optionally, the low-speed signal pin includes at least one of the following pins: i is 2 A pin C; and, FPGA pins; and, an NVLINK pin; and, an HMC USB pin.
Optionally, the test circuit further includes a low-speed signal slot corresponding to the low-speed signal interface. The test chip is connected with the low-speed signal slot position, and can receive and process the low-speed signal transmitted by the test circuit and return a processing result to the test circuit according to a signal form.
Optionally, the test circuit further includes a first power interface and a second power interface.
Optionally, any power interface includes at least two charging interfaces.
Optionally, the test circuit further comprises a first voltage converter and a second voltage converter; one end of the first voltage converter is connected with the first power interface, and the other end of the first voltage converter is connected with at least one PCIe slot position and the low-speed signal slot position of the test circuit; the first end of the second voltage converter is connected with the second power interface, and the second end of the second voltage converter is connected with the rest PCIe slots of the test circuit.
Optionally, the test circuit further includes a complex programmable logic device and a third voltage converter; the complex programmable logic device is connected with one end of the third voltage converter and is used for electrifying the PCIe slot position and/or the low-speed signal slot position of the test circuit and judging whether the PCIe slot position and/or the low-speed signal slot position of the test circuit are/is successfully electrified or not; the second end of the third voltage converter is connected with a PCIe slot position and/or a low-speed signal slot position of the test circuit; and the third end of the third voltage converter is connected with the third end of the second voltage converter.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
Fig. 1 is a schematic view of an application scenario of a possible testing apparatus provided in the prior art;
FIG. 2 is a schematic view of an application scenario of a testing apparatus according to the present invention;
FIG. 3 is a schematic structural diagram of a testing apparatus according to the present invention;
FIG. 4 is a schematic structural diagram of a test circuit and a test chip according to the present invention;
fig. 5 is a schematic structural diagram of an actual test circuit and a backplane to be tested according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic view of an application scenario of a possible testing apparatus provided in the prior art. The application scene comprises a main board, an IO board, a backboard to be tested and a GPU module. The IO board is arranged on the mainboard and provides and manages all input and output control and management functions required by the whole system for the mainboard. The backboard to be tested is usually vertically placed and is respectively connected with the IO board and the GPU module on the mainboard, so that the communication between the mainboard and the GPU module is realized, and in addition, the backboard to be tested also provides a power interface for power supply of the GPU server. When the single-board function test is carried out on the backboard to be tested, the main board sends signals to the backboard to be tested through the IO board, the backboard to be tested transmits the signals to the GPU module, the GPU module receives and processes the signals, and the processed results are transmitted to the main board in a signal form.
In detail, the single board function test includes a signal integrity test, a signal connectivity test, and a power integrity test. Wherein, the signal integrity test can test the transmission quality in the signal transmission process. Signal Integrity (SI) refers to the quality of a signal on a transmission path. The transmission path may be a common metal wire, an optical device, or other medium. A signal with good signal integrity means that the signal can be transmitted from the source to the sink without distortion within a required time. In the field of high-speed signal transmission, signal integrity testing is crucial to research, development and debugging of products. The signal connectivity test can be obtained by calculating the ratio of the signal at the receiving end to the signal at the transmitting end. The power integrity test is to test whether the backboard to be tested can normally transmit the electric signal and the transmission quality of the electric signal.
As described in the background, the prior art requires the use of GPU modules to test the backplane under test, thereby consuming a large capital cost.
In view of this, an embodiment of the present invention provides a testing apparatus for performing a single board function test on a backplane to be tested in a low-cost manner.
Fig. 2 is a schematic view of an application scenario of a testing apparatus according to an embodiment of the present invention. The application scene comprises a main board, an IO board, a backboard to be tested, a test chip, a test circuit and a backboard to be tested. The IO board is disposed on the main board, and details of the IO board can be referred to the above description, which is not described herein again. The backboard to be tested is respectively connected with the IO board and the test circuit on the mainboard, and the test circuit is also connected with the test chip. For details of the test circuit, the test chip, and the backplane to be tested, reference is made to the following descriptions, which are not repeated herein.
Fig. 3 is a schematic structural diagram of a testing apparatus according to an embodiment of the present invention. The test device comprises a test chip, a test circuit and a backboard to be tested. The test chip is connected with the slot position of the test circuit, the test circuit comprises a first interface, the to-be-tested backboard comprises a second interface, the first interface is connected with the second interface through a bus, and the first interface and the second interface both comprise PCIe interfaces.
In the embodiment of the invention, the connected test chip and the test circuit are equivalent to a GPU module, and the first interface and the second interface are connected through the bus, namely the test circuit is connected with the backboard to be tested, so that the function test of the backboard to be tested can be realized. In the testing process, when the plugging times of the first interface of the testing circuit connected with the backboard to be tested reach the service life of the backboard to be tested, the testing circuit is only required to be replaced, the testing chip is reconnected with the slot position of the replaced testing circuit, namely, the slot position is equivalent to a new GPU module, and the backboard to be tested can be subjected to single board function testing by connecting the first interface of the replaced testing circuit with the second interface of the backboard to be tested. In other words, when the single board function test is performed on the backplane to be tested, when the plugging times of the first interface of the test circuit reach the service life of the test circuit, the single board function test can be continued only by replacing the test circuit without replacing the test chip. In practical application, the replacement cost of the GPU module is about 150 ten thousand yuan, and the replacement cost of the test circuit is very low, so that the scheme can perform single board function test on the backboard to be tested in a low-cost mode.
In one possible implementation, the PCIe interface is a PCIe5.0 interface. The pci 5.0 interface uses pci 5.0 technology. The PCIe5.0 technology brings higher transmission speed, for example, x16 bandwidth, the signal transmission rate of the PCIe5.0 technology is increased from 64GB/s to 128GB/s of PCIe 4.0, and the upper limit of the device transmission rate is effectively increased, so that the increasing bandwidth requirements in scenes such as data centers, high-performance computation, edge computation, machine learning, artificial intelligence, 5G networks and the like can be met, and a device manufacturer can realize the same bandwidth with fewer channels. Thus, by using the PCIe5.0 interface, the PCIe interface can be made to provide a faster signaling rate.
In one possible embodiment, the test chip is a CX7 chip. The CX7 chip is a chip from Invidia Corporation (NVIDIA), can be used for high-performance calculation, and supports the PCIe5.0 technology. In the embodiment of the invention, by using the CX7 chip supporting the PCIe5.0 technology, whether the backboard to be tested can transmit the high-speed signal of the PCIe5.0 or not and the signal integrity and the signal connectivity during transmission can be tested.
In one possible embodiment, the test chip and the test circuit are used to implement GPU functionality. In the embodiment of the invention, the test chip and the test circuit for realizing the GPU function can replace a GPU module to carry out single-board function test on the backboard to be tested, so that the single-board function test can be carried out on the backboard to be tested in a low-cost mode.
Fig. 4 is a schematic structural diagram of a test circuit and a test chip according to an embodiment of the present invention. Wherein the first interface and/or the second interface comprises at least two PCIe interfaces.
In a possible implementation manner, the slot of the test circuit includes a PCIe slot corresponding to the PCIe interfaces on the test circuit one to one, one end of the PCIe slot is connected to the PCIe interfaces on the test circuit, and the other end of the PCIe slot is used for connecting the test chip.
In the embodiment of the invention, the test chip communicates with the test circuit through the PCIe slot position.
As shown in fig. 4, the first interface and the second interface each further include a low-speed signal interface, and the low-speed signal interface includes a PCIe pin and a low-speed signal pin.
In one possible embodiment, the low-speed signal pin includes at least one of: integrated Circuit bus (I) 2 C) A pin; and, a Field Programmable Gate Array (FPGA) pin; and, NVLINK pin; and, a HOST MANAGEMENT CONSOLE (HMC) USB pin.
In detail, I 2 C pin is based on I 2 And C, a pin of the protocol. I.C. A 2 Protocol C is a simple two-way two-wire bus protocol standard. I is 2 The C protocol only needs 2 pins and few connecting lines and areas to realize the communication between the chips. Use of I 2 The working current of the communication of the C protocol is very low, so that the power consumption of the system is reduced. In addition, I 2 The protocol C also has a perfect response mechanism, which can enhance the reliability of communication.
The FPGA pin refers to a pin based on an FPGA protocol.
The NVLINK pin refers to a pin based on the NVLINK protocol. NVLINK is a bus and its communication protocol developed and introduced by NVIDIA (NVIDIA). NVLINK adopts point-to-point structure and serial transmission, is used for connection between CPU and GPU, and also can be used for interconnection between a plurality of graphics processors.
The HMC USB pin refers to a pin based on the HMC USB protocol. The HMC is a hardware management port through which a network cable may be connected to control the management minicomputers, including installing operating systems and the like. In addition, the HMC is also used to perform hardware management functions, e.g., its HMC will issue control function requests through the service processors of the managed system.
In the embodiment of the invention, the low-speed signal pin can be used for transmitting a low-speed signal. The low-speed signal pin is arranged in the test circuit, so that the test circuit can transmit low-speed signals, the test device can realize the transmission of the low-speed signals, and can test the signal integrity and the signal connectivity of the backboard to be tested when the backboard to be tested transmits the low-speed signals.
As shown in fig. 4, the test circuit further includes a low-speed signal slot corresponding to the low-speed signal interface. The test chip is connected with the low-speed signal slot position, and can receive and process the low-speed signal transmitted by the test circuit and return a processing result to the test circuit according to a signal form.
As shown in fig. 4, the test circuit further comprises a first power interface and a second power interface. In the embodiment of the invention, the first power interface and the second power interface can receive the electric signals from the backboard to be tested. For example, the electrical signal may be 54V, and 54V is the voltage for the backplane to be tested to power the GPU module.
In one possible embodiment, at least two charging interfaces are included in any power interface.
As shown in fig. 4, the test circuit further includes a first voltage converter and a second voltage converter; one end of the first voltage converter is connected with the first power interface, and the other end of the first voltage converter is connected with at least one PCIe slot position and the low-speed signal slot position of the test circuit; the first end of the second voltage converter is connected with the second power interface, and the second end of the second voltage converter is connected with the rest PCIe slot positions of the test circuit.
For example, taking the first power interface and the second power interface to receive the 54V electrical signal as an example, since the voltage required by the PCIe slot and the low-speed signal slot is 12V, a first voltage converter is required to convert the 54V electrical signal received from the first power interface into a 12V electrical signal, and a second voltage converter is required to convert the 54V electrical signal received from the second power interface into a 12V electrical signal.
As shown in fig. 4, the test circuit further includes a complex programmable logic device and a third voltage converter; the complex programmable logic device is connected with one end of the third voltage converter and is used for electrifying the PCIe slot position and/or the low-speed signal slot position of the test circuit and judging whether the PCIe slot position and/or the low-speed signal slot position of the test circuit are/is successfully electrified or not; the second end of the third voltage converter is connected with a PCIe slot position and/or a low-speed signal slot position of the test circuit; and the third end of the third voltage converter is connected with the third end of the second voltage converter.
A Complex Programmable Logic Device (CPLD) is a digital logic device developed on the basis of a Programmable Logic Device (PLD). The user can program the compiled CPLD program into the CPLD chip through the special CPLD program writer, thereby realizing the digital logic function of the program design. Therefore, the CPLD can implement various digital logic functions by writing a hardware program of specific logic instead of a discrete digital logic chip.
As shown in fig. 5, an embodiment of the present invention provides a methodThe structure of the actual test circuit and the backboard to be tested. The test device comprises a test chip, a test circuit and a backboard to be tested. Wherein, the first interface of the test circuit comprises a low-speed signal interface, namely a J3 interface. The J3 interface includes PCIe pins and low-speed signal pins. Wherein, the low-speed number pin comprises I 2 C11 Pin, I 2 A C16 pin, a FPGA0 (GEN 1) pin, a NVLINK0-1 (GEN 3) pin, and an HMC USB pin; PCIe pins include SW0-GPU4 PE 2-15 pins and SW0-GPU2PE 3-15 pins.
The first interface of the test circuit further comprises 7 PCIe interfaces which are J4 interface, J5 interface, J6 interface, J7 interface, J8 interface, J9 interface and J10 interface respectively. The J4 interface comprises SW0-GPU2PE 3-7 pins and SW0-GPU4 PE2 0-7 pins; the J5 interface comprises SW1-GPU1 PE 4-15 pins and SW1-GPU3 PE 5-15 pins; the J6 interface comprises SW1-GPU1 PE 4-7 pins and SW1-GPU3 PE5 0-7 pins; the J7 interface comprises SW2-GPU8 PE 2-15 pins and SW2-GPU6 PE3 8-15 pins; the J8 interface comprises SW2-GPU6 PE3 0-7 pins and SW2-GPU8 PE2 0-7 pins; the J9 interface comprises SW3-GPU5PE 4-15 pins and SW3-GPU7 PE5 8-15 pins; the J10 interface includes SW3-GPU5PE 4-7 pins and SW3-GPU7 PE5 0-7 pins.
The first power interface of test circuit includes 3 interfaces that charge, is respectively: j54 interface, J30 interface, and J32 interface. Wherein, the J54 interface comprises a P54V _ PSU pin; the J30 interface includes a P54V _ PSU pin; the J32 interface includes a P54V _ PSU pin.
The second power interface of the test circuit comprises 3 charging interfaces, which are respectively: j33 interface, J31 interface, and J55 interface. Wherein, the J33 interface comprises a P54V _ PSU pin; the J31 interface includes a P54V _ PSU pin; the J55 interface includes a P54V _ PSU pin.
The slot of the test circuit comprises two low-speed signal slots, namely a PCIe X1 Gen2 slot and a PCIe X2 Gen3 slot. And the two low-speed signal slot positions are connected with a low-speed pin in the J3 interface.
The Slot positions of the test circuit also comprise 8 high-speed signal Slot positions which are a PCIe X16 Slot 0 Slot position, a PCIe X16 Slot 1 Slot position, a PCIe X16 Slot 2 Slot position, a PCIe X16 Slot 3 Slot position, a PCIe X16 Slot4 Slot position, a PCIe X16 Slot 5 Slot position, a PCIe X16 Slot 6 Slot position and a PCIe X16 Slot 7 Slot position respectively. The PCIe X16 Slot 0 Slot is connected with two PCIe pins in the J3 interface, namely SW0-GPU4 PE28-15 pin and SW0-GPU2PE3 8-15 pin; the PCIe X16 Slot 1 Slot is connected with two PCIe pins in the J4 interface; the PCIe X16 Slot 2 Slot is connected with two PCIe pins in the J5 interface; the PCIe X16 Slot 3 Slot is connected with two PCIe pins in the J6 interface; the PCIe X16 Slot4 Slot is connected with two PCIe pins in the J7 interface; the PCIe X16 Slot 5 Slot is connected with two PCIe pins in the J8 interface; the PCIe X16 Slot 6 Slot is connected with two PCIe pins in the J9 interface; the PCIe X16 Slot 7 Slot connects with two PCIe pins in the J10 interface.
The slot of the test circuit further comprises a first voltage converter DC/DC and a second voltage converter DC/DC. The slot of the test circuit also comprises a third voltage converter DC/DC and a complex programmable logic device CPLD.
The second interface of the backplane to be tested, corresponding to the first interface of the test circuit, comprises a low-speed signal interface, i.e. a J3 interface. The J3 interface includes PCIe pins and low-speed signal pins. Wherein, the low-speed pin comprises I 2 C11 Pin, I 2 A C16 pin, a FPGA0 (GEN 1) pin, a NVLINK0-1 (GEN 3) pin, and an HMC USB pin; PCIe pins include SW0-GPU4 PE 2-15 pins and SW0-GPU2PE 3-15 pins. The second interface of the backboard to be tested further comprises 7 PCIe interfaces which are J4 interface, J5 interface, J6 interface, J7 interface, J8 interface, J9 interface and J10 interface respectively. Wherein, the J4 interface comprises SW0-GPU2PE3 0-7 pins and SW0-GPU4 PE2 0-7 pins; the J5 interface comprises SW1-GPU1 PE 4-15 pins and SW1-GPU3 PE 5-15 pins; the J6 interface comprises pins SW1-GPU1 PE 4-7 and pins SW1-GPU3 PE5 0-7; the J7 interface comprises SW2-GPU8 PE 2-15 pins and SW2-GPU6 PE3 8-15 pins; the J8 interface comprises SW2-GPU6 PE3 0-7 pins and SW2-GPU8 PE2 0-7 pins; the J9 interface comprises SW3-GPU5PE 4-15 pins and SW3-GPU7 PE5 8-15 pins; the J10 interface includes SW3-GPU5PE 4-7 pins and SW3-GPU7 PE5 0-7 pins.
The first power interface of the backplate that awaits measuring includes 3 interfaces that charge, is respectively: j54 interface, J30 interface, and J32 interface. The J54 interface comprises a P54V _ PSU pin; the J30 interface includes a P54V _ PSU pin; the J32 interface includes a P54V _ PSU pin. The second power interface of backplate that awaits measuring includes 3 interfaces that charge, is respectively: j33 interface, J31 interface, and J55 interface. Wherein, the J33 interface comprises a P54V _ PSU pin; the J31 interface includes a P54V _ PSU pin; the J55 interface includes a P54V _ PSU pin.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A testing device is characterized by comprising a testing chip, a testing circuit and a backboard to be tested;
the test chip is connected with the slot position of the test circuit, the test circuit comprises a first interface, the backboard to be tested comprises a second interface, the first interface is connected with the second interface through a bus, and the first interface and the second interface both comprise peripheral component interconnect express (peripheral component interconnect express) PCIe interfaces.
2. The test apparatus of claim 1, wherein the first interface and/or the second interface comprises at least two PCIe interfaces.
3. The testing device of claim 1, wherein the slot of the testing circuit comprises a PCIe slot corresponding to PCIe interfaces on the testing circuit one to one, one end of the PCIe slot is connected to the PCIe interfaces on the testing circuit, and the other end of the PCIe slot is used for connecting the testing chip.
4. The test device of claim 1, wherein the first interface and the second interface each further comprise a low-speed signal interface comprising a PCIe pin and a low-speed signal pin.
5. The test device of claim 4, wherein the low-speed signal pin comprises at least one of:
integrated circuit bus I 2 A pin C; and the combination of (a) and (b),
FPGA pins of a field programmable gate array; and the combination of (a) and (b),
an NVLINK pin; and the combination of (a) and (b),
host management console HMC USB pin.
6. The test device of claim 4, wherein the test circuit further comprises a low-speed signal slot corresponding to the low-speed signal interface.
7. The test device of claim 1, wherein the test circuit further comprises a first power interface and a second power interface.
8. The test device of claim 7, wherein at least two charging interfaces are included in any power interface.
9. The test device of claim 1, wherein the test circuit further comprises a first voltage converter and a second voltage converter;
one end of the first voltage converter is connected with the first power interface, and the other end of the first voltage converter is connected with at least one PCIe slot position and a low-speed signal slot position of the test circuit;
the first end of the second voltage converter is connected with the second power interface, and the second end of the second voltage converter is connected with the rest PCIe slot positions of the test circuit.
10. The test apparatus of claim 1, wherein the test circuit further comprises a complex programmable logic device and a third voltage converter;
the complex programmable logic device is connected with one end of the third voltage converter and is used for powering up a PCIe slot position and/or the low-speed signal slot position of the test circuit and judging whether the PCIe slot position and/or the low-speed signal slot position of the test circuit are/is powered up successfully;
the second end of the third voltage converter is connected with a PCIe slot position of the test circuit and/or the low-speed signal slot position;
and the third end of the third voltage converter is connected with the third end of the second voltage converter.
CN202211553996.XA 2022-12-06 2022-12-06 Testing device Pending CN115877180A (en)

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