CN114567899B - Terminal detection device and signal processing method based on VPX architecture - Google Patents
Terminal detection device and signal processing method based on VPX architecture Download PDFInfo
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- H—ELECTRICITY
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- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/06—Testing, supervising or monitoring using simulated traffic
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention provides a terminal detection device and a signal processing method based on a VPX architecture, and belongs to the technical field of communication detection. The detection device specifically comprises a chassis which is based on a VPX framework and is used for bearing terminal test hardware, and the chassis bears a backboard, a front plugboard and a rear plugboard. The invention adopts a post-outgoing line mode, the equipment on-shelf wiring is tidier and more convenient, and the problem that the traditional multi-carrier ATCA communication architecture is not suitable for being used under the condition of severe external natural environment is solved. In addition, the data number processing board of the high-speed exchange board adopts SRIO and Ethernet double exchange to realize high-speed data intercommunication among boards, each board can be independently dismantled and upgraded, and the system capacity expansion is realized without independent hardware stacking. Meanwhile, the detection device based on the VPX architecture simulates the base station, has the characteristics of miniaturization and convenient movement, can be suitable for terminal tests of different users, and effectively solves the problems that the base station required by the terminal test is not movable and has limited quantity.
Description
Technical Field
The invention relates to the technical field of communication terminal detection, in particular to a terminal detection device based on a VPX architecture and an application method thereof.
Background
Terminals often need to be subjected to a large number of tests before delivery to ensure the reliability of the terminals, and the terminal tests comprise function verification in the process of terminal development, delivery tests, subsystem environment tests, function tests in the process of electromagnetic compatibility tests, integration tests, preparation tests before the tests, and tests during daily maintenance.
In order to realize factory testing of terminal equipment, terminal testing in the prior art generally adopts a mode of communicating with a base station, but the number of the base stations is limited and the base stations are not movable, so that the problems of difficulty in testing and low expandability exist.
Disclosure of Invention
The invention aims to: the terminal detection device based on the VPX framework and the application method thereof are provided to solve the problems in the prior art, and the terminal device delivery test is realized by the detection device which has the advantages of stability, reliability, high integration level and suitability for different types of terminal tests.
The technical scheme is as follows: in a first aspect, a terminal detection device based on VPX architecture is provided, the device comprising: and the chassis is used for bearing terminal test hardware. The terminal test hardware comprises: back plate, front picture peg and back picture peg. The front plugboard and the rear plugboard are connected with the backboard through connectors.
In some implementations of the first aspect, at least three communication paths are integrated on the backplane, for implementing service data transmission, parameter configuration, and interaction of status management signals between at least two boards. The communication path includes: data path, control path and management path.
In some implementations of the first aspect, the front card specifically includes: the system comprises a power panel, an exchange panel, a main control panel, a data processing panel, a network control interface panel, a channel simulation panel, a terminal frequency conversion panel, a station side frequency conversion panel and a terminal baseband panel.
In some implementations of the first aspect, the rear board specifically includes: master control interface tail board, net accuse tail board, analog to digital conversion board, channel simulation tail board, terminal tail board, radio frequency interface tail board.
In some implementations of the first aspect, the front card and the rear card each include an external interface for enabling data interaction. Specifically, the front plugboard is an RJ45 network port as an external interface; the rear plugboard external interface comprises: the system comprises an Ethernet interface, a debugging serial port, an intermediate frequency SMA interface and an output intermediate frequency SMA interface. The Ethernet interface and the debugging serial port in the rear plugboard are used for expanding the corresponding function interfaces in the front plugboard.
In some implementations of the first aspect, the front cards are interconnected through the management path, and are used to implement SRIO and ethernet switching. The SRIO and the Ethernet adopt a double star-shaped switching structure, and in addition, the SRIO is a transmission protocol of high-speed data between boards; ethernet is the transport protocol for inter-board parameter configuration.
In some implementations of the first aspect, the switch board internal assembly includes: the system comprises an SoC chip, an Ethernet exchange chip and an SRIO exchange chip; based on the internal components, the exchange board is used for realizing clock synchronous distribution and backup, SRIO and Ethernet data exchange, board card state management and parameter configuration functions among all front plugboards in the chassis.
In some implementations of the first aspect, the back plate includes: high-speed exchange board slot position, net accuse interface board slot position, data processing board slot position, main control board slot position, channel simulation board slot position, terminal frequency conversion board slot position, station side frequency conversion board slot position, terminal baseband board slot position and power strip slot position.
The backboard divides three groups of connecting lines, a first connecting line interface connects the power supply board with other slot board cards for providing needed power supply, and simultaneously provides clocks for the terminal detection device by penetrating through the front plugboard; the second connecting line is inserted into the terminal detection device, so that the SRIO presents a star-shaped switching structure; the third connecting line is inserted in the terminal detection device, so that the Ethernet presents a star-shaped switching structure, and simultaneously, the expansion of an Ethernet port and the intercommunication between the front plugboard and the rear plugboard are realized through an external interface.
In a second aspect, a signal processing method is provided that divides a signal processing procedure into a forward link for transmission of a transmission signal between terminal devices and a reverse link for transmission of a response signal between terminal devices. When the terminal equipment is the test monitoring equipment and the terminal to be tested, the cooperative network management server specifically comprises the following steps in the forward link:
step 1, a main control board issues parameter configuration instructions to a network control interface board through a network port;
step 2, after receiving the instruction, the network control interface board carries out parameter configuration on the forward data processing board;
step 3, after parameter configuration is completed, the main control board starts to issue a data instruction;
step 4, after receiving the data instruction, the network control interface board exchanges data to the forward data processing board through the SRIO protocol;
step 5, after the forward data processing board encodes, modulates and up-converts the data, the forward data processing board is matched with the corresponding analog-to-digital conversion tail board to finish the transmission of the TDM channel and the service channel;
step 6, connecting data to a channel simulation tail board through a radio frequency line;
step 7, after the channel simulation tail board receives the data from the TDM channel and the service channel, preprocessing the signals;
and 8, transmitting the processed signal to a terminal band plate to be tested.
In some implementations of the second aspect, in the return link, specifically including the steps of:
step (1), a main control board issues parameter configuration instructions to a network control interface board through a network port;
step (2), after receiving the instruction, the network control interface board carries out parameter configuration on the return data processing board;
after the parameter configuration is completed, the terminal sends data to the radio frequency interface box;
step (4), the radio frequency interface box receives data to the terminal frequency conversion board to complete the conversion from the S frequency band signal to the intermediate frequency signal; specifically, the data processing board in the backward link is matched with the corresponding digital-analog conversion tail board to complete the receiving of 1 ALOHA channel and 1 service channel signals, and the functions of down-conversion, timing synchronization, demodulation and decoding of the multi-carrier signals are completed;
step (5), exchanging data to a network control interface board through an SRIO protocol;
step (6), the network control interface board finishes the conversion of the business data frame format protocol and exchanges data to the network management server through the Ethernet protocol;
and (7) the network management server receives the data, packages the data, and reports the statistics error code result to the test monitoring equipment.
The beneficial effects are that: the invention provides a terminal detection device and a signal processing method based on a VPX framework, which are based on the VPX framework, wherein a front plugboard and a rear plugboard are both borne by a backboard, the stability and the reliability are high, and a rear wire-outgoing mode is adopted, so that the equipment on-shelf wiring is tidier and more convenient, and the problem that the traditional multi-carrier ATCA communication framework is not suitable for being used under the condition of severe external natural environment is solved.
In addition, the terminal detection device provided by the application has the characteristics of high integration level and strong expandability. The data number processing board of the high-speed exchange board adopts SRIO and Ethernet double exchange to realize high-speed data intercommunication among boards, each board can be independently dismantled and upgraded, and the system capacity expansion is realized without independent hardware stacking. Meanwhile, the detection device based on the VPX architecture simulates the base station, has the characteristics of miniaturization and convenient movement, can be adapted to terminal tests of different users, and effectively solves the problems that the base station required by the terminal test is not movable and has limited quantity.
Drawings
Fig. 1 is a schematic diagram of an overall architecture of a terminal detection device according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a high-speed switch board architecture according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a network control interface board and a network control tail board according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a data processing board and an analog-to-digital conversion board according to an embodiment of the present invention.
Fig. 5 is a topology diagram of a backplane in an embodiment of the invention.
Fig. 6 is a schematic diagram of a signal processing forward link in an embodiment of the invention.
Fig. 7 is a flow chart of signal processing forward link in an embodiment of the invention.
Fig. 8 is a schematic diagram of a signal processing return link in an embodiment of the present invention.
Fig. 9 is a flow chart of a signal processing return link in an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.
The English definitions referred to in the drawings are as follows: the SHMC represents a server management interface chip, the SRIO Switch represents an SRIO Switch chip, the Ethernet Switch represents an Ethernet Switch chip, the SYSTEM CLOCK represents a SYSTEM CLOCK, the SYSTEM POWER represents a SYSTEM POWER supply, the RJ45 represents an external interface, the IPMC represents an intelligent platform management controller, the IPMB represents an intelligent platform management bus, the CIU represents a central interface device, the BPU represents a baseband processing unit, the RTM represents a rear conversion module, i.e., a tail board, the HDLC represents an advanced data link control, and the LISU represents an intermediate frequency signal processing unit.
Example 1
In this embodiment, a terminal detection device based on a VPX architecture is provided, and the device specifically includes a VPX chassis for carrying terminal test hardware, where the terminal test hardware includes: back plate, front picture peg and back picture peg. The front plugboard and the rear plugboard are connected with the high-speed backboard through connectors. In a preferred embodiment, the front and rear boards are 3U in size and are all connected to the backplane via VPX standard connectors P0, P1, and P2, which are high speed connectors with transmission rates up to 6.25 Gbps.
At least three communication paths are integrated on the backboard and are used for realizing business data transmission, parameter configuration and interaction of state control signals between at least two boards. In a preferred embodiment, the communication path on the back plate specifically includes: data path, control path and management path.
In a preferred embodiment, as shown in fig. 1, the front board specifically includes: the system comprises a power panel, 2 exchange boards, a main control panel, 2 data processing panels, a network control interface panel, a channel simulation panel, a terminal frequency conversion panel, a station side frequency conversion panel and a terminal baseband panel. The front plugboards are interconnected through a management passage of the backboard. In the preferred embodiment, the chassis is a 4U cold-conducting reinforced chassis, and is provided with a back plate, 10 front plugboards and 7 back plugboards, wherein the front plugboards are interconnected through an IPMB bus of the back plate, so that SRIO and Ethernet exchange is realized. The SRIO is used as a transmission protocol of high-speed data between boards, the Ethernet is used as a transmission protocol of parameter configuration between boards, the SRIO and the Ethernet of the high-speed switching boards adopt double star-shaped switching structures, and the two high-speed switching boards respectively control the SRIO and the Ethernet links of the boards.
The rear plugboard specifically comprises: the system comprises a main control interface tail board, a network control tail board, 2 analog-to-digital conversion boards, a channel analog tail board, a terminal tail board and a radio frequency interface tail board.
The embodiment adopts a high-performance and high-reliability VPX architecture computer system standard, so that the system operates more stably and reliably in a complex severe environment, and the integration level and the expandability of the system are greatly improved.
Example two
In a further embodiment based on the first embodiment, the external interfaces of the high-speed switch boards in the front plugboards are RJ45 network interfaces, and the rest front plugboards have no external interfaces. The external interfaces of the network control tail board in the rear plugboard comprise an Ethernet interface and a debugging serial port, and the external interfaces of the analog-to-digital conversion board in the rear plugboard comprise an input intermediate frequency SMA interface and an output intermediate frequency SMA interface.
In the preferred embodiment, the net control tail board in the rear plugboard is used for expanding the function interfaces of the net control interface board in the front plugboard for 3 Ethernet interfaces and 1 debugging serial port; the analog-digital conversion plate inputs and outputs intermediate frequency SMA interfaces respectively.
Example III
In a further embodiment based on the first embodiment, as shown in fig. 2, the high-speed switch board in the front plugboard mainly comprises a SoC chip ZYNQ-7100, an ethernet switch chip BCM5389 and an SRIO switch chip CPS1432, and is used for implementing clock synchronous distribution and backup, SRIO and ethernet data exchange, board card status management and parameter configuration functions between the front plugboards in the chassis. Wherein ZYNQ-7100 configures Ethernet and SRIO switching chips through the I2C interface.
Specifically, the SRIO switching port of the high-speed switching board is connected to the backboard through the VPX high-speed differential connector P1, so that data exchange with other front plugboards is realized; the Ethernet port of the high-speed exchange board is connected to the backboard through the VPX high-speed differential connector P2, so that the interaction of data and control information with other front plugboards is realized; the P0 connector is used to power the board and provide a system reference clock. UART and JTAG are mounted on the high-speed exchange board for debugging and using the board card, and the front plugboard is provided with an RJ45 gigabit network port for remote upgrading and management of the Ethernet port.
Example III
In a further embodiment based on the first embodiment, as shown in fig. 3, the network control interface board in the front plugboard is a high-performance data processing card based on the Open VPX architecture, and mainly realizes functions of the information source simulator, including various functions of sending information source data, physical layer network management service, converting business data frame format protocol, data/signaling interaction with various devices of a large system, channel selection of a data processing board in a chassis, parameter configuration and the like.
In a further embodiment, as shown in fig. 3, the network control interface board in the front plugboard is matched with the network control tail board in the rear plugboard, so as to realize flexible expansion of the function interface of the network control interface board, so as to support connection with a plurality of devices. The method specifically comprises the following steps: CPU module, ethernet exchange module, SRIO exchange module and IPMC module.
In the preferred embodiment, an SRIO port of the SRIO switching module is connected with 2 FP high-speed channels, and is accessed into the backboard through a VPX high-speed differential connector P1, and a single channel can support a transmission rate of 20Gbps at maximum, so that redundant backup of the SRIO high-speed interface is realized; the Ethernet port of the main control interface board is connected with 2 UTP extremely narrow channels, and is accessed to the backboard through the VPX high-speed differential connector P2, the maximum transmission rate of a single channel is 1Gbps, and the interaction of data and control information among other front plugboards is realized; the P0 connector provides board power and provides a system reference clock. A UART is mounted on the network control interface board for debugging and using the board card, and the front plugboard is provided with an RJ45 gigabit network port for remote upgrading and management of the Ethernet port.
In a further embodiment, the network control tail board in the rear plugboard is in butt joint with the front plugboard through the back board, so that an interface expansion function is realized, and connection with a plurality of devices is supported. The interface tail board is used for realizing the expansion of the function interface of the network control interface board, and the module integrates 3 Ethernet ports and 1 debugging serial port. On one hand, 2 paths of SGMII signals led out by SERDES1 integrated in the onboard PowerPC are respectively connected to 2 PHY chips through a back plate, so that gigabit Ethernet port expansion of the network control interface board PowerPC is realized; on the other hand, the 1-path gigabit Ethernet port is directly expanded by the GePHY inside the Ethernet switching chip on the network control interface board.
Example IV
In a further embodiment based on the first embodiment, the data processing board in the front plugboard is used for realizing the single-beam and multi-beam digital signal receiving and transmitting processing functions, including the digital up-down conversion signal preprocessing function, the timing synchronization, the modulation demodulation, the encoding decoding and other baseband functions.
Specifically, as shown in fig. 4, the data processing board includes a forward baseband board and a backward baseband board, and the data processing board is respectively used for completing forward service sending and backward service receiving functions through a modulator module. In the preferred embodiment, the forward baseband board performs 7 TDM time division multiplexed channels and 7 traffic channel transmissions. 7 traffic channels share a modulator module, the modulator module is divided into a normal mode and an anti-interference mode, and 7 channels can be randomly allocated with the normal mode or the anti-interference mode; the return baseband board completes 1 ALOHA channel and 1 traffic channel reception.
The data processing board adopts a large-scale FPGA as a processing chip of a waveform core algorithm, the model is preferably Xilinx V7690T, the FPGA realizes board card power supply through a P0 interface, and the P0 interface provides a system synchronous clock; the two paths of high-speed Serders pins of the FPGA are connected with the P1 interface to respectively realize the SGMII protocol and the SRIO interface protocol, and data interaction can be carried out with other front plugboards through a backboard connecting line.
In a further embodiment, the analog-to-digital conversion board in the rear plugboard is matched with the data processing board in the front plugboard, and the two SMA interfaces are used for realizing the function of interconverting the intermediate frequency digital signal and the analog signal. The board design meets the ANSI/VITA46.0/VITA65 standard of VPX. In a preferred embodiment, the analog-to-digital conversion board comprises 1 ADC (analog-to-digital converter) chip and 1 DAC (digital-to-analog converter) chip, and is used for realizing data receiving and sending of intermediate frequency analog signals; and the amplifier is connected with the ADC chip and the DAC chip and is used for realizing the function of gain control. The P0 connector provides power and a clock for the sampling board; the P1 and P2 connectors are directly connected with the backboard, the data line and the control line of the DAC chip are connected with the FPGA of the data processing board through the P1 interface, and the data line and the control line of the ADC chip are connected with the FPGA of the data processing board through the P2 interface.
In a further embodiment, the hardware board card of the channel simulation board is the same as the data processing board, mainly realizes the function of simulating signal channel parameters, can realize the injection of channel model parameters through upper computer software, and loads parameters such as delay, doppler and the like on acquired waveforms according to preset channel parameters through the acquired channel model. In a preferred embodiment, the maximum Doppler frequency shift of the channel simulation board simulation model is 1Mhz, the maximum delay is + -30 ms, the delay model comprises fixed, linear, sinusoidal, custom, and the like, and a single terminal maximally supports simulation of 109 spot beams.
The channel analog tail board hardware board card is the same as the analog-to-digital conversion board, and mainly realizes the function of interconverting an intermediate frequency digital signal and an analog signal. The channel simulation tail board needs to be matched with the channel simulation board for use, and is provided with two SMA interfaces.
Example five
In a further embodiment based on the first embodiment, the main control board is a high-performance management and control board based on the intel i7 processor, mainly realizing functions of a network management server and test monitoring equipment, wherein the network management server mainly manages channel resources, configures channel frequency point resources for the terminal, analyzes and encapsulates air interface signaling, and realizes network management functions of network access, resource downloading, link establishment, service communication and the like of the terminal. The network management server software is used for communicating with the information source simulator and the test monitoring equipment software on one hand, analyzing the service data from the information source simulator, splicing packets, counting error code results and reporting the error code results to the test monitoring equipment, receiving related control instructions of the test monitoring equipment on the other hand, distributing related test case resources and realizing related service logic, and completing the whole test process; in addition, the network management server software also receives the status report from the channel simulator, analyzes and realizes the functions of beam switching, resource allocation, pre-allocation and the like of the terminal according to the parameters of the status report.
In a further embodiment, the test monitoring device is a control center of the whole detection device, on one hand, realizes automatic test, supports multiple measurement modes and multiple test scenes, adapts to different users, is compatible with independent or random combination test of different test scenes such as single beam, multiple beam, unidirectional, bidirectional, service, network management server and the like, automatically distributes system resources and processes data according to different test scenes and test modes, and controls different modules in the detection device in real time to automatically complete test tasks and dynamically update test progress and test results; on the other hand, the state of each module of the detection equipment such as a network management server, a frequency conversion board, a channel simulation board, a front/back data processing board, a main control interface board and the like is monitored in real time, the risk monitoring of the detection equipment is automatically realized, and the stability of the detection equipment is improved.
In a further embodiment, the station-side frequency conversion board mainly realizes up-conversion of the intermediate frequency signal into an S-band signal, and the terminal frequency conversion board mainly realizes down-conversion of the S-band signal into the intermediate frequency signal. The station side frequency conversion board and the terminal frequency conversion board form a frequency conversion board for realizing frequency conversion from an intermediate frequency signal to an S-band signal. The frequency conversion board is further divided into an up-conversion module, a down-conversion module and a control module, wherein the up-conversion module up-converts the intermediate frequency signal into an S-band signal, synchronizes an external clock signal and provides a reference clock signal for the down-conversion module; the down-conversion module down-converts the S-band signal into an intermediate frequency signal; the control module controls and detects the up-down frequency conversion module, communicates with the outside through the rear panel network port, and controls the output of frequency points and gains.
Example six
In a further embodiment based on the first embodiment, as shown in fig. 5, the back board is a 3U-sized 12-slot structure, conforms to the VPX bus double-star topology structure, supports the front board and the rear board, and comprises 2 high-speed exchange board slots, 1 network control interface board slots, 2 data processing board slots, 1 main control board slots, 1 channel simulation board slots, 1 terminal variable frequency board slots, 1 station side variable frequency board slots, 1 terminal baseband board slots and 1 power board slots, and the chassis reserves 2 slots for later expansion board card use.
The backboard is divided into three groups of connection lines P0, P1 and P2, wherein a P0 interface connects a power panel to supply power to other slot level board cards to provide 12V,5V and 3.3V power, a P0 interface connects a clock line of a slot level of the high-speed switching board to a data processing board, a network control interface board, a channel simulation board and a terminal baseband board, and the high-speed switching board can provide a system reference clock for the data processing board, the network control interface board, the channel simulation board and the terminal baseband board through the backboard; the P1 interface connects the SRIO exchange chip of the high-speed exchange board slot position and the network control interface board slot position with the P1 interface of the data processing board to realize the star-shaped exchange structure of the SRIO; the P2 interface connects the Ethernet exchange chip of the high-speed exchange board slot position and the network control interface board slot position with the P1 interface of the data processing board, thus realizing the star-shaped exchange structure of the Ethernet. One port of the Ethernet exchange chip is led out from the P2 interface of the slot position of the network control interface board and is connected to the P2 interface of the network control tail board, so that the external expansion of 1-channel gigabit Ethernet port is realized, 2-channel SGMII signals are led out from the P1 interface of the slot position of the network control interface board and are respectively connected to 2 PHY chips through a back plate, and the expansion of 2-channel gigabit Ethernet port of the main control interface board is realized. The P2 interface of the backboard slot position realizes communication among the network control interface board, the data processing board and the corresponding rear plug tail board, and the P2 interface of the signal processing board slot position realizes intercommunication of the front plug board and the rear plug board of the AD/DA chip data line.
In a further embodiment, the power board provides power for each service card in the chassis; the program function loaded by the data processing board comprises a forward data processing board and a backward data processing board, the forward service sending and the backward service receiving functions are respectively completed, the forward data processing board is matched with a corresponding digital-analog-digital conversion tail board to complete 7 TDM channels and 7 service channels to send, wherein the 7 service channels share a modulator module, the modulator module is divided into a conventional mode and an anti-interference mode, and the 7 channels can be arbitrarily allocated with the conventional mode or the anti-interference mode; and the backward data processing board is matched with the corresponding digital-analog conversion tail board to complete the reception of 1 ALOHA channel and 1 service channel. The 2 analog-digital conversion boards respectively receive and transmit carrier signals, the analog-digital conversion boards are communicated with the corresponding data processing boards through the P2 interfaces, each data processing board has the functions of intermediate frequency conversion processing and baseband processing, the data processing boards are exchanged to the network control interface board through the P1 interface SRIO protocol, and the network control interface board transmits data to the upper-layer main control board through the Ethernet protocol of the P2 interface for communication.
Example seven
In a further embodiment based on the first embodiment, the process of implementing signal processing based on the terminal detection device is divided into a forward link and a reverse link, wherein the forward link is used for transmitting signals between terminal devices, and the reverse link is used for transmitting response signals between terminal devices; when the terminal equipment is the test monitoring equipment and the terminal to be tested, the cooperative network management server, as shown in fig. 6 and 7, specifically comprises the following steps:
step 1, a main control board issues parameter configuration instructions to a network control interface board through a network port;
step 2, after receiving the instruction, the network control interface board carries out parameter configuration on the forward data processing board;
step 3, after parameter configuration is completed, the main control board starts to issue a data instruction;
step 4, after receiving the data instruction, the network control interface board exchanges data to the forward data processing board through the SRIO protocol;
step 5, after the forward data processing board encodes, modulates and up-converts the data, 7 TDM channels and 7 service channels are sent by matching with the corresponding analog-to-digital conversion tail board;
step 6, connecting data to a channel simulation tail board through a radio frequency line;
step 7, after the channel simulation tail board receives the data from the TDM channel and the service channel, preprocessing the signals; specifically, the channel simulation board performs channel environment simulation, then connects the simulated data to the station side frequency conversion board through the radio frequency line interface of the channel simulation tail board to realize the frequency conversion from the intermediate frequency signal to the S frequency band signal, and then sends the S frequency band signal to the terminal band board through the radio frequency interface box.
In a further embodiment, as shown in fig. 8 and 9, the return link specifically comprises the steps of:
step (1), a main control board issues parameter configuration instructions to a network control interface board through a network port;
step (2), after receiving the instruction, the network control interface board carries out parameter configuration on the return data processing board;
after the parameter configuration is completed, the terminal sends data to the radio frequency interface box;
step (4), the radio frequency interface box receives data to the terminal frequency conversion board to complete the conversion from the S frequency band signal to the intermediate frequency signal; specifically, the backward data processing board is matched with the corresponding digital-analog conversion tail board to complete the receiving of 1 ALOHA channel and 1 service channel signals, and the functions of down-conversion, timing synchronization, demodulation and decoding of the multi-carrier signals are completed;
step (5), exchanging data to a network control interface board through an SRIO protocol;
step (6), the network control interface board finishes the conversion of the business data frame format protocol and exchanges data to the network management server through the Ethernet protocol;
and (7) the network management server receives the data, packages the data, and reports the statistics error code result to the test monitoring equipment.
As described above, although the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limiting the invention itself. Various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (3)
1. A VPX architecture-based terminal detection device, comprising:
the chassis is used for bearing terminal test hardware; the terminal test hardware includes: back plate, front plugboard and back plugboard;
the front plugboard and the rear plugboard are connected with the backboard through connectors;
at least three communication paths are integrated on the backboard and used for realizing the interaction of service data transmission, parameter configuration and state control signals between at least two boards;
the communication path includes: a data path, a control path, and a management path; the process of performing signal processing according to the data link is divided into a forward link for transmission of a transmission signal between terminal devices and a reverse link for transmission of a response signal between terminal devices;
the front plugboards are interconnected through the management channel and are used for realizing SRIO and Ethernet exchange; the SRIO and the Ethernet adopt a double star type switching structure; the SRIO is a transmission protocol of high-speed data between boards; the Ethernet is a transmission protocol of parameter configuration between boards;
the front plugboard specifically comprises: the system comprises a power panel, an exchange panel, a main control panel, a data processing panel, a network control interface panel, a channel simulation panel, a terminal frequency conversion panel, a station side frequency conversion panel and a terminal baseband panel; the station side frequency conversion plate and the terminal frequency conversion plate form a frequency conversion plate and are used for realizing frequency conversion from an intermediate frequency signal to an S-band signal; the frequency conversion board divides an up-conversion module, a down-conversion module and a control module, wherein the up-conversion module up-converts an intermediate frequency signal into an S-band signal, synchronizes an external clock signal and provides a reference clock signal for the down-conversion module; the down-conversion module down-converts the S-band signal into an intermediate frequency signal; the control module controls and detects the up-down frequency conversion module, communicates with the outside through the rear panel network port, and controls the output of frequency points and gains;
the data processing board comprises a forward baseband board and a backward baseband board, and is respectively used for executing forward service sending and backward service receiving functions through a modulator module; wherein the forward baseband board performs 7 TDM time division multiplexing channels and 7 traffic channel transmissions; 7 traffic channels share a modulator module, the modulator module is divided into a normal mode and an anti-interference mode, and 7 channels can be randomly allocated with the normal mode or the anti-interference mode; the backward baseband board completes 1 ALOHA channel and 1 traffic channel reception;
the components in the front plugboard are interconnected through a communication bus penetrating through the backboard, and data interaction is carried out based on SRIO and Ethernet communication protocols;
the rear plugboard specifically comprises: the system comprises a main control interface tail plate, a network control tail plate, an analog-to-digital conversion plate, a channel analog tail plate, a terminal tail plate and a radio frequency interface tail plate; the network control tail board is in butt joint with the front plugboard through the back board, performs an interface expansion function and is used for connecting with a plurality of devices;
the network control interface board in the front plugboard is matched with the network control tail board in the rear plugboard, and is used for realizing flexible expansion of the function interface of the network control interface board so as to support connection with a plurality of devices;
the front plugboard and the rear plugboard both comprise external interfaces for realizing data interaction;
the front plugboard external interface is an RJ45 network interface;
the rear plugboard external interface comprises: the system comprises an Ethernet interface, a debugging serial port, an intermediate frequency SMA interface and an output intermediate frequency SMA interface;
the Ethernet interface and the debugging serial port in the rear plugboard are used for expanding corresponding function interfaces in the front plugboard;
the exchange plate inner assembly includes: the system comprises an SoC chip, an Ethernet exchange chip and an SRIO exchange chip;
based on the internal components, the exchange board is used for realizing clock synchronous distribution and backup, SRIO and Ethernet data exchange, board card state management and parameter configuration functions among all front plugboards in the chassis; the SRIO port is connected with 2 FP high-speed channels, and is connected to the backboard through a VPX high-speed differential connector P1, and a single channel maximally supports 20Gbps transmission rate, so that redundancy backup of the SRIO high-speed interface is realized; the Ethernet port of the main control interface board is connected with 2 UTP extremely narrow channels, and is accessed to the backboard through the VPX high-speed differential connector P2, the maximum transmission rate of a single channel is 1Gbps, and the interaction of data and control information among other front plugboards is realized; the P0 connector supplies power for the board card and provides a system reference clock; a UART is mounted on the network control interface board for debugging and using the board card, and the front plugboard is provided with an RJ45 gigabit network port for remote upgrading and management of the Ethernet port;
the back plate includes: high-speed exchange board slot, network control interface board slot, data processing board slot, main control board slot, channel simulation board slot, terminal frequency conversion board slot, station side frequency conversion board slot, terminal baseband board slot and power board slot;
the backboard is divided into three groups of connecting lines, and a first connecting line interface is used for connecting a power panel to other slot level board cards for providing a required power supply and simultaneously providing a clock for the terminal detection device by penetrating through the front plugboard; the second connecting line is inserted into the terminal detection device, so that the SRIO presents a star-shaped switching structure; the third connecting line is inserted in the terminal detection device, so that the Ethernet presents a star-shaped switching structure, and simultaneously, the expansion of an Ethernet port and the intercommunication between the front plugboard and the rear plugboard are realized through an external interface.
2. A signal processing method, using the terminal detection device based on VPX architecture according to claim 1, characterized in that the signal processing procedure is divided into a forward link and a reverse link, the forward link is used for transmitting signals between terminal devices, and the reverse link is used for transmitting response signals between terminal devices; when the terminal equipment is the test monitoring equipment and the terminal to be tested, the cooperative network management server specifically comprises the following steps in the forward link:
step 1, a main control board issues parameter configuration instructions to a network control interface board through a network port;
step 2, after receiving the instruction, the network control interface board carries out parameter configuration on the forward data processing board;
step 3, after parameter configuration is completed, the main control board starts to issue a data instruction;
step 4, after receiving the data instruction, the network control interface board exchanges data to the forward data processing board through the SRIO protocol;
step 5, after the forward data processing board encodes, modulates and up-converts the data, the forward data processing board is matched with the corresponding analog-to-digital conversion tail board to finish the transmission of the TDM channel and the service channel;
step 6, connecting data to a channel simulation tail board through a radio frequency line;
step 7, after the channel simulation tail board receives the data from the TDM channel and the service channel, preprocessing the signals;
and 8, transmitting the processed signal to a terminal band plate to be tested.
3. The signal processing method according to claim 2, characterized in that in the return link, it comprises in particular the steps of:
step (1), a main control board issues parameter configuration instructions to a network control interface board through a network port;
step (2), after receiving the instruction, the network control interface board carries out parameter configuration on the return data processing board;
after the parameter configuration is completed, the terminal sends data to the radio frequency interface box;
step (4), the radio frequency interface box receives data to the terminal frequency conversion board to complete the conversion from the S frequency band signal to the intermediate frequency signal; specifically, the data processing board in the backward link is matched with the corresponding digital-analog conversion tail board to complete the receiving of 1 ALOHA channel and 1 service channel signals, and the functions of down-conversion, timing synchronization, demodulation and decoding of the multi-carrier signals are completed;
step (5), exchanging data to a network control interface board through an SRIO protocol;
step (6), the network control interface board finishes the conversion of the business data frame format protocol and exchanges data to the network management server through the Ethernet protocol;
and (7) the network management server receives the data, packages the data, and reports the statistics error code result to the test monitoring equipment.
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