CN106294275A - A kind of high speed processing plate system - Google Patents
A kind of high speed processing plate system Download PDFInfo
- Publication number
- CN106294275A CN106294275A CN201610606456.1A CN201610606456A CN106294275A CN 106294275 A CN106294275 A CN 106294275A CN 201610606456 A CN201610606456 A CN 201610606456A CN 106294275 A CN106294275 A CN 106294275A
- Authority
- CN
- China
- Prior art keywords
- chip
- module
- dsp
- clock
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17375—One dimensional, e.g. linear array, ring
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
The invention discloses a kind of high speed processing plate system, including shell, it is provided with power module in described shell, DSP module, clock module, FPGA module, clock module and interface module, power module is other each module for power supply, clock module provides clock signal for DSP module, DSP module includes 5 pieces of dsp chips, it is respectively DSP0, DSP1, DSP2, DSP3 and DSP4, the JTAG signal of dsp chip leads to the front panel of shell through socket, connection is circularized by Link mouth between each dsp chip, LINK port transmission is with 4bit pattern, between dsp chip, the Link port transmission rate of communication is equal to or more than 125 Mb/S.The Link port transmission rate being connected between FPGA module with dsp chip equals to or more than 20Mb/S, and the core clock of dsp chip is 600MHz.The present invention is mainly made up of 5 pieces of dsp chips and jumbo FPGA module, and FPGA module transmits data by Link mouth to dsp chip, has the ability processing large-scale data, and can be controlled dsp chip by external bus transmission instruction.
Description
Technical field
The present invention relates to technical field of electronic communication, be specifically related to a kind of high speed processing plate system.
Background technology
Current dsp processor mostly can only at a time receive or send, and so makes bus transfer bandwidth significantly
Discount (at least reduces one times).Some dsp processor adds some accessory channels, such as to solve this problem
McBSP, HPI etc..But these interface rates are the lowest, the highest also with regard to the speed grade of tens MB, it is clear that can not to meet
The demand of modern signal processing.
Summary of the invention
The problem existed for above-mentioned prior art, the present invention is further improved on prior art basis, this
The bright one that relates to is based on high speed processing plate system, and the present invention is formed DSP module by 5 pieces of dsp chips, by FPGA module to DSP mould
Block transmits data, and data processing rate is the highest.
The present invention is achieved through the following technical solutions foregoing invention purpose.
A kind of high speed processing plate system, including shell, is provided with power module, DSP module, clock mould in described shell
Block, FPGA module, clock module and interface module, described power module is other each module for power supply, and described clock module is DSP
Module provides clock signal, and described DSP module includes 5 pieces of dsp chips, respectively DSP0, DSP1, DSP2, DSP3 and DSP4, institute
The JTAG signal stating dsp chip leads to the front panel of shell through socket, is circularized even by Link mouth between each dsp chip
Connecing, LINK port transmission is with 4bit pattern, and between dsp chip, the Link port transmission rate of communication is equal to or more than 125 Mb/S.,
The Link port transmission rate being connected between FPGA module with dsp chip equals to or more than 20Mb/S, the core clock of dsp chip
It is 600MHz.
The present invention is mainly made up of 5 pieces of dsp chips and jumbo FPGA module, and FPGA module passes through Link mouth to DSP
Chip transmits data, has the ability processing large-scale data, and can be controlled dsp chip by external bus transmission instruction
System.JTAG signal leads to front panel through socket, carries out on-line debugging and program Solidification by special keyset.LINK port transmission
Requiring 4bit pattern, between dsp chip, direct-connected link speed is not less than 125 Mb/S, is preferably designed with 600 Mb/S,
Between FPGA and DSP, link speed is not less than 20Mb/S, is preferably designed with 80 Mb/S, and therefore cabling is in strict accordance with resistance
Anti-matching principle, in conjunction with conventional cabling experience, the division on ground the most electric, interior uses entirety to divide, it is to avoid individually drawing of zonule
Divide the impact that transfer rate is caused.
Further, described dsp chip is ADSP-TS201SABPZ060, and the jtag interface of 5 dsp chips passes through Flos Chrysanthemi
Chain mode is attached, the FLASH chip of the described plug-in 8Mb of DSP0 chip, the SDRAM of the plug-in 128Mb/32bit of described DSP1
Chip, the data address bus of described DSP4 chip is connected with the external world by twoport chip, and daisy chaining can utilize limited
Signal transmssion line connect multiple devices, there is not the problem such as bus contention and obstruction.
Further, described SDRAM chip is MT48LC32M16, and described FLASH chip selects S29GL256, described
The plug-in a piece of S29GL256 FLASH chip of DSP0 chip, described DSP1 plug-in two panels MT48LC32M16 2PSDRAM, Ji Keman
Foot user uses requirement, and DSP4 bus passes through twoport chip correspondence with foreign country.
Further, described FPGA module includes a fpga chip, and described fpga chip is altera corp
EP2C70F672 chip, the JTAG signal of described fpga chip leads to front panel through socket, facilitates on-line debugging and logic to burn
Writing, fpga chip uses configuration chip to start, and fpga chip transmits data, EP2C70F672 core by Link mouth to dsp chip
Sheet has 4 high-performance PLL, and up to 475 User Defined IO, it is possible to meet the design need of this high speed processing plate system
Ask.
Further, described power module is controlled by CPLD and the power management being connected with CPLD, by power management,
Reduce the risk that Link port communications is unstable under high/low temperature.
Further, described clock module include one piece of AD9522 chip, described dsp chip and SDRAM chip by time
Clock module is provided separately clock, and required clock is more, and AD9522 can provide 12 road differential clocks or 24 road single ended clock, can
The clock frequency different by configuring output, therefore selects AD9522 chip to provide clock for justifying.
Further, described clock module produces 50MHz clock, then carries out 12 frequencys multiplication by inside dsp chip.
Further, described shell is radiating box, a size of 180mm × 170mm × 1.8mm (± 0.2mm), the present invention
Volume is little, lightweight, it is simple to grafting in computer.And, case surface should not have the phenomenons such as indenture, scuffing, crack, deformation；
Plated surface coating should not be bubbled, chaps and come off, and metal parts should not have corrosion and mechanical damage, shell has clear, complete
Letter symbol and mark with neat functions.
Further, the front panel of described shell reserves FPGA test port, it is simple to this high speed processing plate system test.
The present invention compared with prior art, at least have following benefit effect:
(1) present invention is mainly made up of 5 pieces of dsp chips and jumbo FPGA module, and FPGA module passes through Link mouth to DSP core
Sheet transmits data, has the ability processing large-scale data, and can be controlled dsp chip by external bus transmission instruction
System.
(2) present invention is based on above-mentioned mentality of designing, it is possible to realize modularity, standardized designs, improves its versatility, and
Simple to operate, convenient and swift.
(3) in the present invention, 5 dsp chips are designed as distributed group battle array, and jtag interface is attached by daisy chaining,
Limited signal transmssion line can be utilized to connect multiple devices, there is not the problem such as bus contention and obstruction, more strengthen its number
According to disposal ability.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing being further appreciated by the embodiment of the present invention, constitutes of the application
Point, it is not intended that the restriction to the embodiment of the present invention.In the accompanying drawings:
Fig. 1 is the theory diagram of the present invention；
Fig. 2 is the internal annexation figure of the present invention；
Fig. 3 is Link mouth annexation figure in the present invention；
Fig. 4 is DSP module theory diagram in the present invention
Fig. 5 is FPGA module theory diagram in the present invention；
Fig. 6 is clock module theory diagram in the present invention；
Fig. 7 is the shape assumption diagram of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with embodiment and accompanying drawing, to this
Invention is described in further detail, and the exemplary embodiment of the present invention and explanation thereof are only used for explaining the present invention, do not make
For limitation of the invention.
Embodiment 1:
As shown in Figures 1 to 4, a kind of high speed processing plate system, including shell, in described shell, it is provided with power module, DSP mould
Block, clock module, FPGA module, clock module and interface module, power module is other each module for power supply, and clock module is
DSP module provides clock signal, and DSP module includes 5 pieces of dsp chips, respectively DSP0, DSP1, DSP2, DSP3 and DSP4,
The JTAG signal of dsp chip leads to the front panel of shell through socket, circularizes connection by Link mouth between each dsp chip,
LINK port transmission is with 4bit pattern, and between dsp chip, the Link port transmission rate of communication is equal to or more than 125 Mb/S., FPGA
The Link port transmission rate being connected between module with dsp chip equals to or more than 20Mb/S, and the core clock of dsp chip is
600MHz。
The present invention is mainly made up of 5 pieces of dsp chips and jumbo FPGA module, and FPGA module passes through Link mouth to DSP
Chip transmits data, has the ability processing large-scale data, and can be controlled dsp chip by external bus transmission instruction
System.JTAG signal leads to front panel through socket, carries out on-line debugging and program Solidification by special keyset.LINK port transmission
Requiring 4bit pattern, between dsp chip, direct-connected link speed is not less than 125 Mb/S, is preferably designed with 600 Mb/S,
Between FPGA and DSP, link speed is not less than 20Mb/S, is preferably designed with 80 Mb/S, and therefore cabling is in strict accordance with resistance
Anti-matching principle, in conjunction with conventional cabling experience, the division on ground the most electric, interior uses entirety to divide, it is to avoid individually drawing of zonule
Divide the impact that transfer rate is caused.
Embodiment 2:
The present embodiment is the further improvement done on the basis of above-described embodiment, as shown in Figures 1 to 4, in the present embodiment,
Dsp chip is ADSP-TS201SABPZ060, and the jtag interface of 5 dsp chips is attached by daisy chaining, DSP0
The FLASH chip of the plug-in 8Mb of chip, the SDRAM chip of the plug-in 128Mb/32bit of DSP1, the data address of DSP4 chip is total
Line is connected with the external world by twoport chip, and daisy chaining can utilize limited signal transmssion line to connect multiple devices, does not deposits
In the problem such as bus contention and obstruction.SDRAM chip is MT48LC32M16, and FLASH chip selects S29GL256, DSP0 chip
Plug-in a piece of S29GL256 FLASH chip, DSP1 plug-in two panels MT48LC32M16 2PSDRAM, user can be met and use
Requirement, DSP4 bus passes through twoport chip correspondence with foreign country.
Embodiment 3:
The present embodiment is the further improvement done on the basis of above-described embodiment, as shown in Figures 1 to 5, in the present embodiment, states
FPGA module includes a fpga chip, and described fpga chip is the EP2C70F672 chip of altera corp, described FPGA core
The JTAG signal of sheet leads to front panel through socket, facilitates on-line debugging and logic programming, and fpga chip uses configuration chip to open
Dynamic, fpga chip transmits data by Link mouth to dsp chip, and EP2C70F672 chip has 4 high-performance PLL, Yi Jiduo
Reach 475 User Defined IO, it is possible to meet the design requirement of this high speed processing plate system.
Embodiment 4:
The present embodiment is the further improvement done on the basis of above-described embodiment, as in figure 2 it is shown, in the present embodiment, described electricity
Source module is controlled by CPLD and the power management being connected with CPLD, and CPLD crystal oscillator is 25MHz, by power management, reduces
The risk that under high/low temperature, Link port communications is unstable.
Embodiment 4:
The present embodiment is the further improvement done on the basis of above-described embodiment, as shown in Figures 1 to 6, in the present embodiment, time
Clock module includes one piece of AD9522 chip, and clock module produces 50MHz clock, then carries out 12 frequencys multiplication by inside dsp chip.
Dsp chip and SDRAM chip are provided separately clock by clock module, and required clock is more, and AD9522 can provide 12 tunnels poor
Timesharing clock or 24 road single ended clock, can export different clock frequencies by configuring, and therefore selecting AD9522 chip is justifying
Clock is provided.
Embodiment 5:
The present embodiment is the further improvement done on the basis of above-described embodiment, as it is shown in fig. 7, in the present embodiment, shell is
Radiating box, a size of 180mm × 170mm × 1.8mm (± 0.2mm), volume of the present invention is little, lightweight, it is simple in computer
Grafting.And, case surface should not have the phenomenons such as indenture, scuffing, crack, deformation；Plated surface coating should not bubble, chaps and take off
Falling, metal parts should not have corrosion and mechanical damage, shell has clear, complete and neat functions letter symbol and
Mark.For ease of this high speed processing plate system test, the front panel of shell is reserved with FPGA test port.
As it has been described above, the present invention can preferably be implemented.
Claims (9)
1. a high speed processing plate system, it is characterised in that: include shell, in described shell, be provided with power module, DSP mould
Block, clock module, FPGA module, clock module and interface module, described power module is other each module for power supply, described clock
Module provides clock signal, described DSP module to include 5 pieces of dsp chips, respectively DSP0, DSP1, DSP2, DSP3 for DSP module
And DSP4, the JTAG signal of described dsp chip leads to the front panel of shell through socket, by Link mouth between each dsp chip
Circularizing connection, LINK port transmission is with 4bit pattern, and between dsp chip, the Link port transmission rate of communication is equal to or more than 125
Mb/S, the Link port transmission rate being connected between FPGA module with dsp chip equals to or more than 20Mb/S, dsp chip interior
Nuclear clock is 600MHz.
High speed processing plate system the most according to claim 1, it is characterised in that: described dsp chip is ADSP-
TS201SABPZ060, the jtag interface of 5 dsp chips is attached by daisy chaining, the described plug-in 8Mb of DSP0 chip
FLASH chip, the SDRAM chip of the plug-in 128Mb/32bit of described DSP1, the data address bus of described DSP4 chip passes through
Twoport chip is connected with the external world.
High speed processing plate system the most according to claim 2, it is characterised in that: described SDRAM chip is
MT48LC32M16, described FLASH chip selection S29GL256, the plug-in a piece of S29GL256 FLASH chip of described DSP0 chip,
Described DSP1 plug-in two panels MT48LC32M16 2PSDRAM.
High speed processing plate system the most according to claim 1, it is characterised in that: described FPGA module includes a FPGA core
Sheet, described fpga chip is the EP2C70F672 chip of altera corp, and the JTAG signal of described fpga chip is drawn through socket
To front panel, fpga chip uses configuration chip to start, and fpga chip transmits data by Link mouth to dsp chip.
High speed processing plate system the most according to claim 1, it is characterised in that: described power module by CPLD and with
The power management that CPLD connects controls.
High speed processing plate system the most according to claim 2, it is characterised in that: described clock module includes one piece of AD9522
Chip, described dsp chip and SDRAM chip are provided separately clock by clock module.
High speed processing plate system the most according to claim 6, it is characterised in that: described clock module produces 50MHz clock,
12 frequencys multiplication are carried out again by inside dsp chip.
High speed processing plate system the most according to claim 1, it is characterised in that: described shell is radiating box, a size of
180mm×170mm×1.8mm(±0.2mm)。
High speed processing plate system the most according to claim 8, it is characterised in that: the front panel of described shell is reserved FPGA and is surveyed
Examination mouth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610606456.1A CN106294275A (en) | 2016-07-29 | 2016-07-29 | A kind of high speed processing plate system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610606456.1A CN106294275A (en) | 2016-07-29 | 2016-07-29 | A kind of high speed processing plate system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106294275A true CN106294275A (en) | 2017-01-04 |
Family
ID=57663074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610606456.1A Withdrawn CN106294275A (en) | 2016-07-29 | 2016-07-29 | A kind of high speed processing plate system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106294275A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109491290A (en) * | 2018-11-16 | 2019-03-19 | 西安空间无线电技术研究所 | A kind of cold standby bus complexing circuit suitable for digital processing system |
-
2016
- 2016-07-29 CN CN201610606456.1A patent/CN106294275A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109491290A (en) * | 2018-11-16 | 2019-03-19 | 西安空间无线电技术研究所 | A kind of cold standby bus complexing circuit suitable for digital processing system |
| CN109491290B (en) * | 2018-11-16 | 2020-08-14 | 西安空间无线电技术研究所 | Cold backup bus multiplexing circuit suitable for digital processing system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203561931U (en) | External GPU card extending device | |
| CN109189714B (en) | Arria10 FPGA-based signal processing system with double processing nodes | |
| CN101847093B (en) | Digital signal processor with reconfigurable low power consumption data interleaving network | |
| CN106294275A (en) | A kind of high speed processing plate system | |
| CN108008362A (en) | A kind of if radar target echo and interference generation module | |
| CN205318373U (en) | Wireless real -time signal handles integrated circuit board based on VPX structure | |
| CN206039520U (en) | Handle board at a high speed | |
| CN209103281U (en) | Integrated multi-bus interface module based on pci interface | |
| CN106066844A (en) | A kind of many dsp processors system based on FPGA | |
| CN110516809B (en) | Implementation device of privacy amplification algorithm based on FPGA + RISC-V | |
| CN206039517U (en) | Many DSP treater based on FPGA | |
| CN207458046U (en) | A kind of programmable logic device and its internal logic function module time-sharing multiplex circuit | |
| CN102832947B (en) | For 20 galvanometer digital-to-analogue conversion plate of laser marking machine | |
| CN202373216U (en) | FPGA experimental development plate | |
| CN209168103U (en) | A kind of Communication processing central processing unit based on PowerPC architecture processor | |
| CN206322162U (en) | CM multiplication device with PCIE and GPRS interfaces | |
| CN104915313A (en) | FMC board card for realizing level transformation by using FPGA (field programmable gate array) | |
| CN206835066U (en) | Short-wave signal intermediate frequency acquisition process recovery card | |
| CN204719625U (en) | A kind of embedded-type modularized computing machine | |
| CN205193522U (en) | Can cascaded ripples accuse machine and quick -witted system of ripples accuse | |
| CN103995255A (en) | Multi-channel digital correlator in comprehensive aperture microwave remote sensing radiometer | |
| CN204044809U (en) | Single-chip network turns Multi-serial port device | |
| CN209241014U (en) | A kind of novel on-vehicle USB interface | |
| CN202218216U (en) | Low-power-consumption asynchronous comparison gate for low density parity check (LDPC) decoder | |
| CN104679216B (en) | A kind of data path means and its control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: The new West Road 610000 in Sichuan Province, Chengdu city high tech Development Zone No. 2 Applicant after: Sichuan Di Information Technology Co., Ltd. Address before: The new West Road 610000 in Sichuan Province, Chengdu city high tech Development Zone No. 2 Applicant before: Sichuan SDRising Information Technology Co., Ltd. |
|
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20170104 |