CN101699414A - Data processing system - Google Patents
Data processing system Download PDFInfo
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- CN101699414A CN101699414A CN200910235295A CN200910235295A CN101699414A CN 101699414 A CN101699414 A CN 101699414A CN 200910235295 A CN200910235295 A CN 200910235295A CN 200910235295 A CN200910235295 A CN 200910235295A CN 101699414 A CN101699414 A CN 101699414A
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- master control
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- data handling
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Abstract
The invention discloses a data processing system, which comprises a host computer, a master control device and a slave device, wherein the host computer is provided with a host interface used for data communication; the master control device is communicated with the host computer through the host interface; and the slave device is connected to the master control device and controlled by the master control device. By utilizing the data processing system, the data exchange velocity is greatly improved and the storage capacity is improved at the same time.
Description
Technical field
The present invention relates to data processing field, more specifically, the present invention relates to a kind of data handling system.
Background technology
FPGA is the abbreviation of English Field-Programmable Gate Array, i.e. field programmable gate array, and it is the product that further develops on the basis of programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome the limited shortcoming of original programming device gate circuit number again.
FPGA has the various configurations pattern: parallel holotype adds the mode of a slice EPROM for a slice FPGA; Master slave mode can be supported a slice PROM programming multiple FPGA; Serial mode can adopt serial PROM programming FPGA; The peripheral hardware pattern can be programmed by microprocessor the peripheral hardware of FPGA as microprocessor to it.
How to realize fast timing closure, reduce power consumption and cost, optimization Clock management and reduce FPGA and the problems such as complicacy of PCB concurrent designing, be the key issue that the system design engineer of employing FPGA need be considered always.Nowadays, along with FPGA to high density more, more high capacity, more the direction of low-power consumption and integrated more IP develops, some new problems also occur thereupon.Because monolithic FPGA resource-constrained, so exchanges data is slow, and capacity is also smaller.
Summary of the invention
Consider the problems referred to above and make the present invention, for this reason, fundamental purpose of the present invention is to provide a kind of data handling system, to improve exchanges data speed and the memory capacity in the FPGA technology.
To achieve these goals, according to embodiments of the invention, provide a kind of data handling system, it comprises: main frame has the host interface that is used for data communication; Master control set communicates by host interface and main frame; And slave unit, be connected to master control set, and control by master control set.
Also comprise in this data handling system: memory storage is connected to corresponding slave unit.Wherein, master control set and slave unit are programmable logic device (PLD), and slave unit is a plurality of programmable logic device (PLD), and a plurality of programming devices are connected with master control set respectively.This programmable logic device (PLD) is FPGA.
In addition, in this data handling system, master control set has the PCI-E bus controller, and the PCI-E bus controller is used for communicating and controlling with host interface slave unit.Slave unit has memory controller, is used for the memory storage that is connected with corresponding slave unit is controlled.Wherein, PCI-E bus controller and memory controller communicate, and memory storage is DDR2 SO-DIMM.
By the data handling system of the invention described above, make exchanges data speed improve a lot, also increased memory capacity simultaneously.
Description of drawings
Accompanying drawing is used to provide further understanding of the present invention, and constitutes the part of instructions, is used from explanation the present invention with embodiments of the invention one, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the structured flowchart according to the data handling system of the embodiment of the invention; And
Fig. 2 is the annexation figure according to the master control FPGA and the subordinate FPGA of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein only is used for description and interpretation the present invention, and be not used in qualification the present invention.
Fig. 1 is the structured flowchart according to the data handling system of the embodiment of the invention.
As shown in Figure 1, comprise in data handling system 100: main frame 300 has the host interface 302 that is used for data communication; Master control set 120 communicates by host interface and main frame; And slave unit 104-114, be connected to master control set 120, and control by master control set 120.In this data handling system 100, memory storage 204-214 is connected to corresponding slave unit 104-114.In an embodiment of the present invention, master control set 120 and slave unit 104-114 are programmable logic device (PLD), are preferably FPGA.A plurality of slave unit 104-114 are connected with master control set 120 respectively.It will be understood by those skilled in the art that the quantity that can at random dispose slave unit and memory storage according to different needs, it is not limited to 6 shown in Fig. 1.But, guarantee that slave unit is corresponding with the quantity of memory storage.
In Fig. 1, master control set 102 has PCI-E bus controller 102a, and PCI-E bus controller 102a is used for communicating and control slave unit 104-114 with host interface 302a.Slave unit 104-114 has memory controller 104a-114a, is used for the memory storage 204-214 that is connected with corresponding slave unit 104-114 is controlled.
Below, with reference to Fig. 2, be example with FPGA, the relation between master control set 102 and the slave unit 104-114 is described.
Fig. 2 is the annexation figure according to the master control FPGA and the subordinate FPGA of the embodiment of the invention.
As shown in the figure, master control FPGA receives a plurality of data DATA1-DATA3 that are applied to different subordinate FPGA from host interface, the PCI-E bus controller respectively with each subordinate FPGA in memory controller communicate, and data are sent in the memory controller of corresponding subordinate FPGA according to the sign in the different pieces of information.For example, send data DATA1 to a subordinate FPGA, send data DATA2 to another subordinate FPGA, and send data DATA3 to last subordinate FPGA.Here, it will be understood by those skilled in the art that the PCI-E bus controller can also with other interface communications among the subordinate FPGA, send the data to different subordinate FPGA.
In addition, in order further to improve exchanges data speed, the present invention adopts DDR2 SO-DIMM as memory storage.But it will be understood by those skilled in the art that memory storage is not limited to DDR2SO-DIMM, can use other existing memory and the following DDR3SO-DIMM that will use.In addition, in an embodiment of the present invention, host interface is a PCI-E 8x interface.But it will be understood by those skilled in the art that host interface is not limited to this PCI-E 8x interface, under the situation of the exchanges data speed that guarantees system, also can use the interface of other type, as PCI-E 16x interface, PCI-E 32x interface etc.
As mentioned above, in conjunction with Fig. 1 and Fig. 2 as can be known, present embodiment has adopted polylith FPGA integrated, by master-slave mode, coordinates the work of other subordinate FPGA as main control with the FPGA that has the PCI-E bus controller.Master control FPGA mainly realizes communicating by letter with the PCI-E data transmission of main frame and with subordinate FPGA.
Thereby, utilize the data handling system in the present embodiment, make exchanges data speed improve a lot, also increased memory capacity simultaneously.
In addition, also utilized DDR2SO-DIMM among the present invention, further improved exchanges data speed as memory storage.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a data handling system is characterized in that, comprising:
Main frame has the host interface that is used for data communication;
Master control set communicates by described host interface and described main frame; And
Slave unit is connected to described master control set, and is controlled by described master control set.
2. data handling system according to claim 1 is characterized in that, also comprises:
Memory storage is connected to corresponding described slave unit.
3. data handling system according to claim 2 is characterized in that, described master control set and described slave unit are programmable logic device (PLD).
4. data handling system according to claim 3 is characterized in that, described slave unit is a plurality of programmable logic device (PLD), and described a plurality of programming devices are connected with described master control set respectively.
5. data handling system according to claim 4 is characterized in that, described programmable logic device (PLD) is FPGA.
6. data handling system according to claim 5 is characterized in that described master control set has the PCI-E bus controller, and described PCI-E bus controller is used for communicating and control described slave unit with described host interface.
7. data handling system according to claim 6 is characterized in that described slave unit has memory controller, is used for the described memory storage that is connected with corresponding described slave unit is controlled.
8. data handling system according to claim 7 is characterized in that, described PCI-E bus controller and described memory controller communicate.
9. data handling system according to claim 7 is characterized in that, described memory storage is DDR2 SO-DIMM.
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| CN200910235295XA CN101699414B (en) | 2009-09-30 | 2009-09-30 | Data processing system |
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| CN200910235295XA CN101699414B (en) | 2009-09-30 | 2009-09-30 | Data processing system |
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| CN101699414A true CN101699414A (en) | 2010-04-28 |
| CN101699414B CN101699414B (en) | 2011-11-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105068955A (en) * | 2015-07-20 | 2015-11-18 | 北京广利核系统工程有限公司 | Local bus structure and data interaction method |
| CN109711552A (en) * | 2019-03-27 | 2019-05-03 | 深兰人工智能芯片研究院（江苏）有限公司 | A kind of data processing system and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5903733A (en) * | 1997-02-13 | 1999-05-11 | Toshiba America Information Systems, Inc. | Multifunction peripheral controller |
| CN1088218C (en) * | 1999-11-14 | 2002-07-24 | 邓国顺 | Electronic flash storage method and device for data processing system |
| CN1174196C (en) * | 2001-10-17 | 2004-11-03 | 珠海格力电器股份有限公司 | Air conditioner remote monitoring system with master/slave control function |
| CN2757220Y (en) * | 2004-10-15 | 2006-02-08 | 重庆大学 | Multi path grating data transducer based on programmable logic device and USB interface |
| CN1996321A (en) * | 2006-11-03 | 2007-07-11 | 威海渔翁科技开发有限公司 | Encryption card based on PCI Express bus technology |
| CN101281499B (en) * | 2008-05-29 | 2010-07-21 | 上海交通大学 | Mobile hard disc enciphering system of FPGA control MEMS strong chain |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105068955A (en) * | 2015-07-20 | 2015-11-18 | 北京广利核系统工程有限公司 | Local bus structure and data interaction method |
| CN105068955B (en) * | 2015-07-20 | 2018-04-03 | 北京广利核系统工程有限公司 | A kind of local bus architecture and data interactive method |
| CN109711552A (en) * | 2019-03-27 | 2019-05-03 | 深兰人工智能芯片研究院（江苏）有限公司 | A kind of data processing system and electronic equipment |
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Address after: 100193 Beijing, Haidian District, northeast Wang West Road, building 8, No. 36 Patentee after: Dawning Information Industry (Beijing) Co.,Ltd. Address before: 100084 No. 6 South Road, Zhongguancun Academy of Sciences, Beijing, Haidian District Patentee before: Dawning Information Industry (Beijing) Co.,Ltd. |
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Effective date of registration: 20220801 Address after: 100089 building 36, courtyard 8, Dongbeiwang West Road, Haidian District, Beijing Patentee after: Dawning Information Industry (Beijing) Co.,Ltd. Patentee after: DAWNING INFORMATION INDUSTRY Co.,Ltd. Address before: 100193 No. 36 Building, No. 8 Hospital, Wangxi Road, Haidian District, Beijing Patentee before: Dawning Information Industry (Beijing) Co.,Ltd. |