CN202453880U

CN202453880U - FPGA (field programmable gate array)-based low-cost 1553B bus interface circuit

Info

Publication number: CN202453880U
Application number: CN 201120417525
Authority: CN
Inventors: 鞠浩; 袁盾
Original assignee: No 8357 Research Institute of Third Academy of CASIC
Current assignee: No 8357 Research Institute of Third Academy of CASIC
Priority date: 2011-10-28
Filing date: 2011-10-28
Publication date: 2012-09-26
Anticipated expiration: 2021-10-28

Abstract

The utility model belongs to bus interface circuits, particularly relates to an FPGA (field programmable gate array)-based low-cost 1553B bus interface circuit and aims to reduce cost of the 1553B bus interface circuit and improve university thereof. The bus interface circuit comprises an FPGA chip, a 1553B integrated transceiver chip, a clock source, a power reset chip and an FPGA program load chip, the 1553B integrated transceiver chip, the clock source, the power reset chip and the FPGA program load chip are connected with the FPGA chip, the 1553B integrated transceiver chip exchanges bus data signals with the outside by the aid of two transformers, and the FPGA chip comprises a bus interface module, a shared memory, a control status register management module, a 1553B protocol processing module, a 1553B message processing module connected with the 1553B protocol processing module and a system clock module connected with the clock source. The FPGA-based low-cost 1553B bus interface circuit is simple in hardware, high in integration level and universality, small in size and flexible in operation and can be applied to bus connection of various control systems, the rejection rate is decreased, economic loss is lowered, and production cost is saved greatly.

Description

A kind of low-cost 1553B bus interface circuit based on FPGA

Technical field

The utility model belongs to bus interface circuit, is specifically related to a kind of low-cost 1553B bus interface circuit based on FPGA.

Background technology

There are DDC company, CONDOR company, SBS Co., Ltd. in main flow MIL-STD-1553B Bus Interface Chip supplier on the market.Wherein interface chips application such as the BU-61570 of DDC company, BU-6158, BU-61840 series are comparatively extensive, and the key distinction is the external interface form, and its its processing core changes of function is little; Because the monopolization of international vendor causes such interface chip expensive, is difficult to reduce the system development cost.

Summary of the invention

The purpose of the utility model is in order to reduce 1553B bus interface circuit cost, a kind of low-cost 1553B bus interface circuit based on FPGA to be provided.

The technical scheme that the utility model adopted is:

A kind of low-cost 1553B bus interface circuit based on FPGA, wherein: comprise fpga chip, the integrated transceiving chip of the 1553B that links to each other with fpga chip, clock source, power reset chip, FPGA program load chip; The integrated transceiving chip of 1553B is through two transformers and outside switching bus data-signal; Said fpga chip comprises bus interface module, shared storage, state of a control register management module, 1553B protocol process module, the 1553B message processing module that links to each other with the 1553B protocol process module, the system clock module that links to each other with the clock source.

Aforesaid a kind of low-cost 1553B bus interface circuit based on FPGA, wherein: said 1553B protocol process module comprises system control module, interrupt management module, BC functional module, RT functional module, MT functional module and RTMT functional module.

Aforesaid a kind of low-cost 1553B bus interface circuit based on FPGA, wherein: said BC functional module comprises BC control state machine, BC transmit status machine, BC accepting state machine, BC message queue management state machine, BC type of message state machine, BC interrupt management state machine, BC mismanage state machine.

Aforesaid a kind of low-cost 1553B bus interface circuit based on FPGA, wherein: said clock source is 12M/24M clock source.

The beneficial effect of the utility model is:

1. the utility model hardware is simple, and high integration is arranged, universal height, and the bus that can be applicable to the various control system connects; Greatly reduced cost, with respect to the BU-61580 of DDC company series interfaces chip, the cost of the utility model only is equivalent to 1/4 of such interface chip.

2. the compatible DDC BU-61580 of the company series of the utility model function 1553B interface chip can be realized the seamless replacement to this series products; And improved portability;

3. it is little to the utlity model has volume, and the characteristics of flexible operation have reduced scrappage and economic loss, have greatly saved production cost.

Description of drawings

A kind of low-cost 1553B bus interface circuit structural representation that Fig. 1 provides for the utility model based on FPGA;

Fig. 2 is a logic function module diagram in the FPGA.

Embodiment

Below in conjunction with accompanying drawing and embodiment a kind of low-cost 1553B bus interface circuit based on FPGA that the utility model provides is introduced:

As shown in Figure 1, a kind of low-cost 1553B bus interface circuit based on FPGA comprises fpga chip, and the integrated transceiving chip of the 1553B that links to each other with fpga chip, clock source, power reset chip, FPGA program load chip.The integrated transceiving chip of 1553B is through two transformers and outside switching bus data-signal.The 1553B bus interface circuit adopts 16 bit data asynchronous buss to realize and the communicating by letter of ppu in the present embodiment.The clock source is that fpga chip provides clock signal; The power reset chip is that fpga chip provides systematic reset signal; The integrated transceiving chip of fpga chip and 1553B can be realized the mutual of 1553B logical signal, and system is provided by fpga chip the bus signals and the control signal of ppu.

Wherein FPGA is the core devices of this circuit; Its logic function module diagram is as shown in Figure 2, comprises bus interface module, shared storage, state of a control register management module, 1553B protocol process module, the 1553B message processing module that links to each other with the 1553B protocol process module, the system clock module that links to each other with the clock source.

State of a control register management module receiving processor and storer control signal, bus interface module realize the visit of external bus to register and shared store under the control of state of a control register management module; Bus interface module is provided with the nWAIT signal, to satisfy the unmatched problem of the inner shared store read or write speed of ppu and FPGA.

The 1553B protocol process module mainly comprises system control module, interrupt management module, BC functional module, RT functional module, MT functional module and RTMT functional module.Wherein system control module is provided with all state machines of initialization 1553B protocol process module according to state of a control register management module, the configuration-system mode of operation, and produce look-at-me according to work state information control interrupt management module under each pattern.The BC functional module realizes the bus controller function, is responsible for initiating response to the RT remote terminal; The BC functional module comprises BC control state machine, BC transmit status machine, BC accepting state machine, BC message queue management state machine, BC type of message state machine, BC interrupt management state machine, BC mismanage state machine.The affairs that the RT functional module is initiated bus according to self RT address as remote terminal respond; The MT functional module is responsible for realizing that any message on the bus monitors; The RTMT functional module is according to self RT address response bus transaction the time, the message on can also monitor bus.

In sum, the compatible BU-81580 family chip of FPGA internal logic function function; Satisfying on the general basis, greatly reduced production cost to 1553B bus functionality demand.

Through adopting the field programmable logic array (FPLA) device,, realize 1553B bus B C/RT/RTMT/MT function in conjunction with circuit such as the integrated transceiving chip of 1553B, power reset chip, transformer, clock sources.The clock source can be 12M/24M clock source, can select through the fpga chip internal register.

Claims

1. the low-cost 1553B bus interface circuit based on FPGA is characterized in that: comprise fpga chip, the integrated transceiving chip of the 1553B that links to each other with fpga chip, clock source, power reset chip, FPGA program loading chip; The integrated transceiving chip of 1553B is through two transformers and outside switching bus data-signal; Said fpga chip comprises bus interface module, shared storage, state of a control register management module, 1553B protocol process module, the 1553B message processing module that links to each other with the 1553B protocol process module, the system clock module that links to each other with the clock source.

2. a kind of low-cost 1553B bus interface circuit based on FPGA according to claim 1, it is characterized in that: said 1553B protocol process module comprises system control module, interrupt management module, BC functional module, RT functional module, MT functional module and RTMT functional module.

3. a kind of low-cost 1553B bus interface circuit based on FPGA according to claim 2, it is characterized in that: said BC functional module comprises BC control state machine, BC transmit status machine, BC accepting state machine, BC message queue management state machine, BC type of message state machine, BC interrupt management state machine, BC mismanage state machine.

4. a kind of low-cost 1553B bus interface circuit based on FPGA according to claim 1, it is characterized in that: said clock source is 12M/24M clock source.