CN116055425B

CN116055425B - Internet of things hardware platform

Info

Publication number: CN116055425B
Application number: CN202310341961.8A
Authority: CN
Inventors: 陈先良; 杨彬; 周玲
Original assignee: Beijing Leyan Technology Co ltd
Current assignee: Beijing Leyan Technology Co ltd
Priority date: 2023-04-03
Filing date: 2023-04-03
Publication date: 2023-06-20
Anticipated expiration: 2043-04-03
Also published as: CN116055425A

Abstract

The invention relates to an Internet of things hardware platform, which comprises a processor chip and an exchange chip, wherein the processor chip is a C3000 chip, and the interface supported by a ten-thousand-megaphone network controller of the C3000 chip is used for connecting and matching with the exchange chip to expand function rows; the C3000 chip is connected to the exchange chip through the SFI signal line and is connected to the exchange chip through the mdio bus for management. The hardware platform of the Internet of things has obvious advantages in cost; under the condition of the same CPU performance, the new architecture of the invention can realize more network port resources by utilizing limited cost without externally plugging other expansion cards, thereby really realizing lower cost, more functional technical requirements and higher competitiveness.

Description

Internet of things hardware platform

Technical Field

The invention relates to the technical field of the Internet of things, in particular to an Internet of things hardware platform for realizing high-density ports based on a high-performance processor chip and an exchange chip.

Background

At present, the security equipment in the network security industry related to the Internet of things technology is biased to a digital communication product, just like a traditional routing switch, a large number of interfaces are arranged on the equipment, so that a large number of network card chips are required in the traditional design, the cost of the network card chips is high, and the product has no competitiveness.

Because the main resource of the digital communication product used in the traditional Internet of things industry is PCIE bus, network card chips are needed, and a large number of network card chips are needed to support a plurality of ports; if the exchange chip is needed, a specific bus is needed to be connected to the exchange chip, so the exchange chip cannot be directly used; the difference between the network card chip and the exchange chip is that the connection mode is different from the CPU, the network throughput is inconsistent, and the number of support ports is different.

Disclosure of Invention

The invention aims to provide an Internet of things hardware platform for realizing a high-density port based on a high-performance processor chip and an exchange chip, and aims to solve the technical problems of at least expanding an interface by using the exchange chip instead of a network card chip.

In order to achieve the above purpose, the invention provides an internet of things hardware platform for realizing high-density ports based on a high-performance processor chip and an exchange chip, which comprises a processor chip and an exchange chip, wherein the processor chip is a C3000 chip, and the interface supported by a ten-thousand-meganetwork controller of the C3000 chip is used for connecting and matching with the exchange chip to expand function rows; the C3000 chip is connected to the exchange chip through the SFI signal line and is connected to the exchange chip through the mdio bus for management.

Preferably, the hardware platform of the internet of things utilizes the switching chip to divide vlan of different network data streams, and the switching data streams are directly forwarded through the switching chip, and data needing to be reported to be processed by the CPU are sent to the CPU for processing through an uplink port and then are issued.

Preferably, in the hardware platform of the internet of things, the two-layer data packet is directly forwarded, and the three-layer and upper-layer data packet is processed and forwarded by the CPU.

Preferably, the processor chip is a DENVERTONSC 3758 chip.

Preferably, the exchange chip is an 88E6193 bridge chip.

Preferably, the tera-network controller is 10 GbE LAN Controller.

Preferably, the C3758 chip is connected to the switch chip through the SFI signal line to process network data.

Preferably, the C3758 chip is connected to the switch chip for management through an SMI signal line.

Preferably, the C3000 chip can be connected to 4 switch chips through four SFI signal lines.

Preferably, each switching chip is capable of outputting 8 electrical ports and 2 tera ports, so that 4 switching chips can output 32 electrical ports and 8 tera ports in total.

Advantageous effects

Compared with the prior art, the invention has the beneficial effects that:

the hardware platform of the Internet of things fully uses the software and hardware resources of the C3000 chip, utilizes the high-speed interface supported by the self 10 GbE LAN Controller and is matched with the 88E6193 bridge chip to build a complete architecture system, fully plays the self functions of the C3000 chip, and truly meets the design requirements of low-cost and high-density network ports. The architecture system is as follows: by utilizing the characteristics of the exchange chip, vlan division is carried out on different network data streams, the exchange data streams can be directly forwarded through the exchange chip, and the data needing to be reported and processed by the CPU are sent to the CPU for processing through the uplink port and then issued; the data packets of two layers are directly forwarded, and the data packets of three layers and upper layer are forwarded through cpu processing.

The reason why the present invention can directly use the switching chip is that: the CPU selected by the product of the invention has SFI signal lines supporting the uplink of the exchange chip, so the exchange chip can be used; four SFI signal lines of the CPU can be connected with 4 exchange chips, and each exchange chip can output 8 electric ports and 2 tera ports, so that the total number of the four SFI signal lines is 32 electric ports and 8 tera ports.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate and do not limit the invention.

Fig. 1 is a schematic architecture diagram of a network port high-density internet of things hardware platform according to the invention.

Detailed Description

The present invention is described in more detail below to facilitate an understanding of the present invention.

As shown in fig. 1, the internet of things hardware platform for realizing high-density ports based on the high-performance processor chip and the exchange chip comprises a processor chip and an exchange chip, wherein the processor chip is a C3000 chip, and is connected with and matched with the exchange chip by using an interface supported by a ten-thousand mega network controller (10 GbE LAN Controller) of the C3000 chip to expand functional rows; the C3000 chip is connected to the exchange chip through the SFI signal line and is connected to the exchange chip through the mdio bus for management.

Preferably, the processor chip is a DENVERTONSC 3758 chip.

Preferably, the exchange chip is an 88E6193 bridge chip.

Preferably, the tera-network controller is 10 GbE LAN Controller.

Preferably, the CPU (C3758) is connected to the switching chip (88E 6193) through the SFI signal line to perform processing of network data.

Preferably, the CPU (C3758) is managed by connecting to the switch chip (88E 6193) through the SMI signal line.

In this application, 88E6193 is a switch chip, and since the CPU supports SFI signal lines, it can be connected to the 88E6193 chip.

The hardware platform of the Internet of things utilizes the interface supported by 10 GbE LAN Controller of C3000 to connect and cooperate with 88E6193 bridge pieces to expand the function line, thereby truly achieving the design requirements of low cost, high density network port and performance satisfaction.

The novel framework has obvious advantages in cost as can be seen from the table; under the condition of the same CPU performance, the new architecture of the invention can realize more network port resources by utilizing limited cost without externally plugging other expansion cards, thereby really realizing lower cost and moreThe technical requirement of the function and higher competitiveness.

The invention has the technical advantages that:

(1) fully utilizing the resources of the C3000 chip and the exchange chip;

(2) the multi-port and low cost is truly realized.

The key technical point of the invention is that the C3000 series CPU is matched with 88E6193 to realize the expansion of the number of network ports and the functionality, so that the cost performance of the product is more powerful.

The foregoing describes preferred embodiments of the present invention, but is not intended to limit the invention thereto. Modifications and variations to the embodiments disclosed herein may be made by those skilled in the art without departing from the scope and spirit of the invention.

Claims

1. The Internet of things hardware platform is characterized by comprising a processor chip and an exchange chip, wherein the processor chip is a C3000 chip, and the interface supported by a ten-thousand-meganetwork controller of the C3000 chip is used for connecting and matching with the exchange chip to perform functional expansion; the C3000 chip is connected to the exchange chip through an SFI signal line and is connected to the exchange chip through an mdio bus for management;

the hardware platform of the Internet of things utilizes the exchange chip to carry out vlan division on different network data streams, the exchange data streams are directly forwarded through the exchange chip, and data needing to be reported to be processed by the CPU are sent to the CPU for processing through an uplink port and then are issued;

in the hardware platform of the Internet of things, two-layer data packets are directly forwarded, and three-layer and upper-layer data packets are processed and forwarded by a CPU.

2. The internet of things hardware platform of claim 1, wherein the processor chip is a denvoltonsoc C3758 chip.

3. The hardware platform of claim 1, wherein the switch chip is an 88E6193 bridge chip.

4. The internet of things hardware platform of claim 1, wherein the tera-network controller is 10 GbE LAN Controller.

5. The hardware platform of claim 2, wherein the C3758 chip is connected to the switch chip through an SFI signal line for processing network data.

6. The hardware platform of claim 5, wherein the C3758 chip is connected to the switch chip for management via an SMI signal line.

7. The hardware platform of claim 1, wherein the C3000 chip is capable of connecting 4 switch chips through four SFI signal lines.

8. The internet of things hardware platform of claim 7, wherein each switch chip can output 8 electrical ports and 2 tera ports, so that 4 switch chips can output 32 electrical ports and 8 tera ports in total.