CN115225589A - CrossPoint switching method based on virtual packet switching - Google Patents
CrossPoint switching method based on virtual packet switching Download PDFInfo
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- CN115225589A CN115225589A CN202210838070.9A CN202210838070A CN115225589A CN 115225589 A CN115225589 A CN 115225589A CN 202210838070 A CN202210838070 A CN 202210838070A CN 115225589 A CN115225589 A CN 115225589A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/70—Virtual switches
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
Abstract
A cross point exchange method based on virtual packet exchange relates to the technical field of large-scale circuit exchange. The invention aims to solve the problems that the design flexibility of the existing CrossPoint chip is poor, the exchange chip can only exchange link data, cannot extract data from the link or insert data into the link, and can only complete simple port data exchange. The invention comprises the following steps: the method comprises the following steps: step 1, on the FPGA layer, decomposing large-scale data exchange into a plurality of virtual small-scale data exchanges, wherein the plurality of small-scale exchanges have a specific incidence relation and can be controlled by a register; step 2, determining which FPGA registers and configuration values are configured on the drive software level through specific algorithm operation; and 3, establishing the relation between a plurality of virtual small-scale data and the register to realize equivalent large-scale full exchange. The method is mainly used in data switching networks.
Description
Technical Field
The invention belongs to the technical field of large-scale circuit switching, and particularly relates to a CrossPoint switching method based on virtual packet switching.
Background
The circuit switching technology based on the cross point chip is used for the mainstream video switching matrix at present, and the cross point chip is also used for part of the switches. For example, the CrossPoint chip from Macom corporation has been adopted by many video matrix manufacturers. The switching scale is limited, and the largest-scale switching chip specification provided by MACOM corporation is that 288 pairs of input and output, namely a single CrossPoint chip can make a video matrix of 288 IO ports; if a 576-port fully-switched video matrix is to be realized, 9 288 CrossPoint chips are needed to form a matrix to complete the back plate switching function; if a larger-scale video matrix is to be constructed, the hardware design based on the CrossPoint chip is very difficult. The scheme based on the CrossPoint chip has poor design flexibility, and the exchange chip can only exchange link data, cannot extract data from the link or insert data into the link, and can only complete simple port data exchange. For the design of large-scale exchange host hardware, more data channels must be designed to complete the communication of related management data, which also brings more workload for hardware debugging.
The existing cross point chip scheme has poor design flexibility, and the exchange chip can only exchange link data, cannot extract data from the link or insert data into the link, and can only complete simple port data exchange.
Disclosure of Invention
The invention aims to solve the problems that the design flexibility of the existing CrossPoint chip is poor, the exchange chip can only exchange link data, cannot extract data from a link or insert data into the link, and only can complete simple port data exchange.
A CrossPoint exchange method based on virtual packet exchange, the method comprising the steps of: step 1, on the FPGA layer, decomposing large-scale data exchange into a plurality of virtual small-scale data exchanges, wherein the plurality of small-scale exchanges have a specific incidence relation and can be controlled by a register; step 2, determining which registers and configuration values of the FPGA are configured through specific algorithm operation on a driving software layer; and 3, establishing the relation between a plurality of virtual small-scale data and the register to realize equivalent large-scale full exchange.
Preferably, in step 1, the plurality of pieces of virtual small-scale data include Leaf nodes, spine nodes, and MSpine nodes, and any one path of data of any Leaf node may be fully exchanged with any Spine node; for one path of data of any Leaf node, sometimes multiple Spine nodes can be reached at the same time, sometimes only one Spine node can be reached at a specific time, the Leaf node and the Spine node are exchanged through software configuration, and the Spine node and the MSping node are exchanged.
Preferably, the step 2 includes:
2.1, the configuration register selects a Leaf node to exchange with any Spine node;
2.2, internal exchange configuration of Spine nodes;
and 2.3, selecting one Spine node output end as a final output end.
Preferably, in step 3, the association between the plurality of virtual small-scale data and the register is established through a software algorithm.
Preferably, the hardware fabric backplane of the switch host uses Arria10 1150 and the IO board uses 2 Arria10 480.
The patent provides a crossbar switching method based on virtual packet switching, which utilizes a large amount of SERDES resources and logic resources carried by an FPGA chip to realize the port data switching of a super-large port scale, such as the switching of 816 port 1 Gbps. Meanwhile, the end-to-end exchange delay can be guaranteed to be nanosecond. Besides the exchange of the video link, the exchange of other data with small bandwidth can be realized in the exchange of the backboard; the method is used for equipment management, firmware upgrading and related communication protocol packet forwarding among equipment, and solves the problems that the design flexibility of the existing crossbar chip is poor, the exchange chip can only exchange link data, can not extract data from a link or insert data into the link, and can only complete simple port data exchange.
Drawings
Fig. 1 is a schematic diagram of a CrossPoint switching method based on virtual packet switching;
FIG. 2 is a schematic diagram of a 384 port switch of the present invention;
FIG. 3 is a diagram of port 816 swapping in the present invention.
Detailed Description
The first embodiment is as follows: referring to the drawings for describing the present embodiment in detail, as shown in fig. 1 to 3, the CrossPoint exchange method based on virtual packet exchange according to the present embodiment includes the following steps: step 1, on the FPGA level, decomposing large-scale data exchange into a plurality of virtual small-scale data exchanges, wherein the plurality of small-scale exchanges have a specific incidence relation and can be controlled by a register; step 2, determining which registers and configuration values of the FPGA are configured through specific algorithm operation on a driving software layer; and 3, establishing the relation between a plurality of virtual small-scale data and the register to realize equivalent large-scale full exchange.
In the step 1, the plurality of virtual small-scale data includes Leaf nodes, spine nodes and MSping nodes, and any path of data of any Leaf node can be completely exchanged with any Spine node; for one path of data of any Leaf node, sometimes multiple Spine nodes can be reached at the same time, sometimes only one Spine node can be reached at a specific time, the Leaf node and the Spine node exchange through software configuration, and the Spine node and the MSping node exchange.
The step 2 comprises the following steps:
2.1, the configuration register selects a Leaf node to exchange with any Spine node;
2.2, internal exchange configuration of Spine nodes;
and 2.3, selecting one Spine node output end as a final output end.
In step 3, a software algorithm is used to establish a relationship between a plurality of virtual small-scale data and registers. The hardware fabric backplane of the switching host uses Arria10 1150 and the IO board uses 2 Arria10 480.
In this embodiment, one extra-large scale exchange, for example 576x576, is decomposed into a plurality of virtual small scale exchanges (Spine), for example 10 80x80 exchanges; for FPGA/ASIC design, any input to any output data exchange means that the fan-out for each input signal is very large, in this example 576 for 576 lanes of data. For FPGA/ASIC, the layout and wiring are super complex; meanwhile, the system safety working clock frequency of FPGA/ASIC design will be reduced, resulting in that high-speed exchange cannot be completed. The ability to break up a large-scale data exchange into multiple smaller-scale exchanges takes full advantage of the properties of port byte stream-based exchanges: 1. data is only transmitted from one port to one port or a plurality of ports, and the condition that the data input by a plurality of ports is transmitted to one port after being collected does not exist; 2. the data exchange relationship between the ports is controlled by software configuration, and the exchange relationship is fixed after the configuration, which is different from the packet exchange based on MAC address/IP address in the Ethernet; 3. the delay from port to port is fixed regardless of which path any port data travels through. Thus, the final product implementation of this solution also requires a set of software algorithms for allocating/reclaiming data exchange paths. A link is distributed relative to the CrossPoint chip, and only one register needs to be simply configured; in this scheme, software needs to allocate a port to a port switching path, and needs to configure a plurality of registers, which mainly includes: and selecting which Spine is switched by the link on the Leaf, configuring internal Spine switching, and selecting one Spine output as the final output. In short, this solution is equivalent to a way of adding a software algorithm to implement infinite-approximation large-scale full switching, which is full switching for users.
As shown in fig. 1, this is a network structure similar to the conventional three-layer switching: access layer-client device; leaf layer-local exchange/interaction with backplane; spine layer-backbone exchange (MSpine is used for exchange between spines). In addition, in the switching structure, all the switching is based on byte stream switching, which is different from the packet-based switching of the switch; thus, with this configuration, the port-to-port delay is substantially fixed, up to a few clock cycles, regardless of which path any port data is routed through. Any path of data of any Leaf node can be completely exchanged to any SPINE node; however, because the number of Spine exchanges is limited, for a path of data of any Leaf node, sometimes multiple Spine nodes can be reached at the same time, sometimes only one Spine node can be reached at a specific time, and a path of data of a specific Leaf node is exchanged to which Spine node and configured by software.
As shown in fig. 2, the scheme implements a 384-port switching example, the backplane (backbone) switch is based on one ariia 10 1150FPGA chip, and 2 ariia 10480 chips are used on each IO board (branch); each FPGA on the IO board has 4 Serdes of 10G which are interconnected with the FPGA on the backboard, and each IO board panel has 48 interfaces of 1Gbps (the whole host can theoretically have 576 IO ports, and here, only 384 port exchange is realized due to the logic resource of Arria 10).
As shown in fig. 3, the scheme implements a 816 port switching example, the backplane switching is based on 2 ariia 10 1150fpga chips, and 2 ariia 10480 chips are used on each IO board; each FPGA on the IO board has 4 Serdes of 10G interconnected with the FPGA on the backplane, and each panel of the IO board has 48 interfaces of 1Gbps (here, only the 816 port exchange is realized considering the reason of the logic resource of Arria10 1150).
The invention has the advantages of solving the problems of exchange scale: an Arria10 1150FPGA chip is used as a switching chip, and the maximum video switching matrix can reach 384 IO ports; 2 Arria10 1150FPGA chips are used as switching chips, and the maximum video switching matrix can reach 816 IO ports. The flexibility is better: besides the exchange of the video link, the exchange of other data with small bandwidth can be realized in the exchange of the backboard; the hardware structure is simplified: the FPGA used as the back board for exchange can be used as a switching center for controlling data/an uplink bus and a downlink bus for controlling data, and hardware interconnection of bus communication of the control board card and the IO board card is simplified. That is, a special control bus for management design between the control board card and the plurality of IO board cards is not required on hardware.
The software algorithm that establishes the association between the plurality of virtual small-scale data and the registers is as follows:
Claims (5)
1. a CrossPoint switching method based on virtual packet switching, characterized in that the method comprises the following steps:
step 1, on the FPGA level, decomposing large-scale data exchange into a plurality of virtual small-scale data exchanges, wherein the plurality of small-scale exchanges have a specific incidence relation and can be controlled by a register;
step 2, determining which registers and configuration values of the FPGA are configured through specific algorithm operation on a driving software layer;
and 3, establishing the relation between a plurality of virtual small-scale data and the register to realize equivalent large-scale full exchange.
2. The CrossPoint exchange method based on virtual packet switching according to claim 1, wherein in step 1, the plurality of virtual small-scale data includes Leaf nodes, spine nodes and MSpine nodes, and any path of data of any Leaf node can be fully exchanged with any Spine node; for one path of data of any Leaf node, sometimes multiple Spine nodes can be reached at the same time, sometimes only one Spine node can be reached at a specific time, the Leaf node and the Spine node exchange through software configuration, and the Spine node and the MSping node exchange.
3. The CrossPoint switching method based on virtual packet switching according to claim 1, wherein said step 2 comprises:
2.1, the configuration register selects a Leaf node to exchange with any Spine node;
2.2, internal exchange configuration of Spine nodes;
and 2.3, selecting one Spine node output end as a final output end.
4. The CrossPoint switching method based on virtual packet switching according to claim 1, wherein in step 3, the association between the plurality of virtual small-scale data and the register is established through a software algorithm.
5. The CrossPoint exchange method based on virtual packet exchange of claim 3, wherein the hardware architecture backplane of the exchange host uses Arria10 1150, and the IO board uses 2 Arria10 480.
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Cited By (1)
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| CN116193056A (en) * | 2023-04-06 | 2023-05-30 | 广州美凯信息技术股份有限公司 | Multi-rate circuit switching method and switching system |
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