CN116193056B

CN116193056B - Multi-rate circuit switching method and switching system

Info

Publication number: CN116193056B
Application number: CN202310359088.5A
Authority: CN
Inventors: 于志军; 黄兆锦
Original assignee: Guangzhou Mediacomm Information Technology Co ltd
Current assignee: Guangdong Meikai Technology Co ltd
Priority date: 2023-04-06
Filing date: 2023-04-06
Publication date: 2023-09-29
Anticipated expiration: 2043-04-06
Also published as: CN116193056A

Abstract

The embodiment of the invention relates to the technical field of communication, and discloses a multi-rate circuit switching method and a switching system, wherein the method comprises the following steps: if the branch FPGA port is in the first rate mode, controlling the second rate processing link to perform transmission channel two-to-one processing; wherein one of the second rate processing links occupies two transmission channels; performing rate switching processing on a second rate signal output by the second rate processing link so that the second rate signal enters the branch FPGA port; if the branch FPGA port is in the second rate mode, controlling the first rate processing link to process the first transmission channel into the second transmission channel; wherein one of said first rate processing links occupies one transmission channel; and directly transmitting the first rate signal output by the first rate processing link to the branch FPGA port. By implementing the embodiment of the invention, a plurality of exchange modes among different rates can be supported.

Description

Multi-rate circuit switching method and switching system

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a multi-rate circuit switching method and a switching system.

Background

The main video switching matrix in the market at present can be divided into two types, the first type is a circuit switching technology based on a cross point chip, and the second type is a packet switching technology based on a TCP/IP protocol.

However, in practice, it has been found that the following problems exist in most of the CrossPoint-based chips: 1) The exchange scale is difficult to expand, and the maximum-scale cross point exchange chip on the market can only realize 288 pairs of input and output ports. If the switching size is to be further increased, for example, the ports are doubled, then the cross point chip used is doubled. The number of chips increases exponentially, the stacking connection is extremely complex, and continuous scale up is not possible at all; 2) The switching mode is single, the switching chip can only realize port-to-port point-to-point switching, and cannot realize multipoint-to-single-point and point-to-multipoint switching. Meanwhile, the input and output of the port cannot be self-adaptive, the input can only be connected with the signal sending equipment, and the output can only be connected with the signal receiving equipment, so that the engineering implementation is extremely inconvenient; 3) The path cannot be managed, moved, copied and deleted.

For the packet switching technology based on IP, the method has stronger switching flexibility and can easily enlarge the switching scale in a multistage cascade mode, but the blocking exists, and the method is not really full switching. And the exchange based on the IP message can not realize the management of the path, and the universal IP message faces the security problems of being stolen, deciphered and the like.

Disclosure of Invention

The embodiment of the invention discloses a multi-rate circuit switching method and a switching system, which can support switching modes among a plurality of different rates.

An embodiment of the present invention in a first aspect discloses a multi-rate circuit switching method, the method comprising:

if the branch FPGA port is in the first rate mode, controlling the second rate processing link to perform transmission channel two-to-one processing; wherein one of the second rate processing links occupies two transmission channels;

performing rate switching processing on a second rate signal output by the second rate processing link so that the second rate signal enters the branch FPGA port;

if the branch FPGA port is in the second rate mode, controlling the first rate processing link to process the first transmission channel into the second transmission channel; wherein one of said first rate processing links occupies one transmission channel;

and directly transmitting the first rate signal output by the first rate processing link to the branch FPGA port.

As another optional implementation manner, in the first aspect of the embodiment of the present invention, if a branch FPGA port is in a third rate mode, the first rate signals output by any N first rate processing links are transmitted together to the branch FPGA port; wherein N is a natural number not less than 1.

Transmitting the second rate signals output by any M second rate processing links to the branch FPGA ports together; wherein M is a natural number not less than 1.

As another optional implementation manner, in the first aspect of the embodiment of the present invention, the method further includes:

if the branch FPGA port is in the first rate mode, directly transmitting the first rate signal to the branch FPGA port through the first rate processing link;

and if the branch FPGA port is in the second rate mode, directly transmitting the second rate signal to the branch FPGA port through the second rate processing link.

when the branch FPGA port receives message data information sent by a certain device, a device type identification field in the message data information is identified to determine whether the certain device is a signal receiving device or a signal sending device.

When a signal instruction of path shifting is received, deleting an initial channel used for establishing a link between a certain branch FPGA port and another branch FPGA port, and starting a redundant channel used for establishing a link between the certain branch FPGA port and the another branch FPGA port.

when a signal instruction for starting the redundant channel is received, configuring a redundant vertical channel of a signal sending port, a vertical channel and a redundant horizontal channel of a signal receiving port, a transmission channel from a branch FPGA to a trunk FPGA and a transmission channel from the trunk FPGA to the branch FPGA respectively;

and controlling a transmission channel from the trunk FPGA to the branch FPGA to enable.

when a signal instruction for not starting the redundant channel is received, configuring a vertical channel and a horizontal channel of the trunk FPGA, a transmission channel from the branch FPGA to the trunk FPGA and a transmission channel from the trunk FPGA to the branch FPGA respectively;

at least X branch FPGAs are included on one trunk FPGA, and at least Y branch FPGA ports are included on one branch FPGA; wherein the X and the Y are natural numbers not less than 1, respectively.

A second aspect of an embodiment of the present invention discloses a switching system, including:

the first control unit is used for controlling the second rate processing link to perform transmission channel two-to-one processing if the branch FPGA port is in the first rate mode; wherein one of the second rate processing links occupies two transmission channels;

the processing unit is used for carrying out rate switching processing on the second rate signal output by the second rate processing link so as to enable the second rate signal to enter the branch FPGA port;

the second control unit is used for controlling the first rate processing link to perform transmission channel I-II processing if the branch FPGA port is in the second rate mode; wherein one of said first rate processing links occupies one transmission channel;

And the transmission unit is used for directly transmitting the first rate signal output by the first rate processing link to the branch FPGA port.

A third aspect of an embodiment of the present invention discloses a switching system, including:

a memory storing executable program code;

a processor coupled to the memory;

the processor invokes the executable program code stored in the memory to perform a multi-rate circuit-switched method as disclosed in the first aspect of the embodiment of the present invention.

A fourth aspect of the embodiments of the present invention discloses a computer-readable storage medium storing a computer program, wherein the computer program causes a computer to execute a multi-rate circuit switching method disclosed in the first aspect of the embodiments of the present invention.

A fifth aspect of an embodiment of the invention discloses a computer program product which, when run on a computer, causes the computer to perform part or all of the steps of any of the multi-rate circuit-switched methods of the first aspect.

A sixth aspect of the embodiments of the present invention discloses an application publishing platform for publishing a computer program product, wherein the computer program product, when run on a computer, causes the computer to perform part or all of the steps of any of the multi-rate circuit switched methods of the first aspect.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

in the embodiment of the invention, if the branch FPGA port is in the first rate mode, the second rate processing link is controlled to perform the second-to-first transmission channel processing; wherein one of the second rate processing links occupies two transmission channels; performing rate switching processing on a second rate signal output by the second rate processing link so that the second rate signal enters the branch FPGA port; if the branch FPGA port is in the second rate mode, controlling the first rate processing link to process the first transmission channel into the second transmission channel; wherein one of said first rate processing links occupies one transmission channel; and directly transmitting the first rate signal output by the first rate processing link to the branch FPGA port. Therefore, the embodiment of the invention can support the exchange mode among a plurality of different rates.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow diagram of a multi-rate circuit-switched method according to an embodiment of the present invention;

fig. 2 is a flow chart of another multi-rate circuit-switched method disclosed in an embodiment of the present invention;

FIG. 3 is a schematic diagram of a switching system according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another switching system according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another switching system according to an embodiment of the present invention;

FIG. 6 is a switch fabric architecture as disclosed in an embodiment of the present invention;

fig. 7 is a branch uplink and downlink switching process according to an embodiment of the present invention;

FIG. 8 is a backbone switching process disclosed in an embodiment of the present invention;

fig. 9 is a diagram showing a switching relationship between a downlink channel and a 1G port according to an embodiment of the present invention;

fig. 10 is a diagram showing a switching relationship between a downstream channel and a 2.5G port according to an embodiment of the present invention;

fig. 11 shows a switching relationship between a downstream channel and a 10G port according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that the terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present invention are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.

The following detailed description refers to the accompanying drawings.

Example 1

Referring to fig. 1, fig. 1 is a flow chart of a multi-rate circuit switching method according to an embodiment of the invention. As in fig. 1, the multi-rate circuit-switched method may include the following steps.

101. If the branch FPGA port is in the first rate mode, the switching system controls the second rate processing link to process the second transmission channel; wherein one of the second rate processing links occupies two transmission channels.

102. And the switching system performs rate switching processing on the second rate signal output by the second rate processing link so as to enable the second rate signal to enter the branch FPGA port.

103. If the branch FPGA port is in the second rate mode, the switching system controls the first rate processing link to process the first transmission channel into the second transmission channel; wherein one of the first rate processing links occupies one transmission channel.

In the embodiment of the present application, when the first rate is 1G rate and the second rate is 2.5G rate, if the 1G port occupies one channel, the 2.5G port may occupy two channels similarly. The scheme supports two rate modes, a single finger can be configured into a 1G rate mode (assuming a finger of 24 ports), a 2.5G rate mode (where only 12 ports are active), and each finger rate mode is completely independent.

For example, as shown in fig. 9, the switching relationship between the downstream channel and the 1G port is described (when the second rate is in the 2.5G rate mode). If the downlink channel is the signal from the 1G device, the signal will go through 1G downlink processing link (occupying 1 channel); if the downlink channel is a signal from a 2.5G device, the signal will go through the 2G downlink processing link (2 channels). For a 2.5G to 1G exchange, the 2G downlink processing link needs to complete channel two to one, then enter the 12X24 exchange, and the final link can enter the 1G port.

Also for example, as shown in fig. 10, the downstream channel is depicted in a switching relationship with the 2.5G port (2.5G rate mode). If the downlink channel is the signal from the 1G device, the signal will go through 1G downlink processing link (occupying 1 channel); if the downlink channel is a signal from a 2.5G device, the signal will go through the 2G downlink processing link (2 channels). For a 1G to 2.5G exchange, the 1G downlink processing link needs to complete channel one to two, and the final link can only enter the 2.5G port.

104. And the switching system directly transmits the first rate signal output by the first rate processing link to the branch FPGA port.

As an alternative implementation manner, in the embodiment of the present invention, the entire exchange procedure is mainly divided into three steps:

step 1 is a branch uplink switch, for example, in fig. 7, 24 ports are respectively corresponding to one channel one by one (the last 8 channels have no ports to be reserved), and then the branch uplink is a 32X32 switch;

step 2 is a backbone switch, as shown in fig. 8, where the backbone has 64 paths of 10G services, with 8 channels in each 10G service. We call 10G services horizontal channels and 8 channels in 10G services vertical channels. Then, for horizontal channels, one can understand a 64 in 64 out, 64X64 exchange; for vertical channels, one can understand an 8 in 8 out, 8X8 exchange. After the trunk exchange is completed, entering a branch downlink exchange;

Step 3 is a downstream switch of the branch, as shown in the right side of fig. 7, the trunk arrives at the branch with 32 channels, and the branch has 32 channels corresponding to ports (the channels not corresponding to the branches are reserved). The downstream switch of the branch can also be regarded as a 32 in 32 out, 32X32 switch.

As an optional implementation manner, in the embodiment of the present application, the present application may have flexible and diverse switching modes, and the present application supports not only a port-to-point switching mode, but also a point-to-multipoint, and a multipoint-to-point switching mode. The port of the present application supports three rates: the three rates of 1G, 2.5G and 10G are flexible and configurable, so that cross exchange between 1G and 1G, between 2.5G and between 1G and 2.5G can be realized, and aggregation from 1G port and 2.5G port to 10G optical port is supported.

In the multi-rate circuit switching method of fig. 1, a switching system is described as an example of an execution body. It should be noted that, the execution body of the multi-rate circuit switching method of fig. 1 may also be a stand-alone device associated with the switching system, which is not limited by the embodiment of the present application.

It can be seen that implementing a multi-rate circuit-switched approach as described in fig. 1 is capable of supporting a plurality of switching modes between different rates.

In addition, implementing a multi-rate circuit switching method described in fig. 1 not only supports switching at the same rate, but also switching between different rates, so that switching modes are flexible and various.

Example two

Referring to fig. 2, fig. 2 is a flow chart illustrating another multi-rate circuit switching method according to an embodiment of the invention. As in fig. 2, the multi-rate circuit-switched method may include the steps of:

201. if the branch FPGA port is in the first rate mode, the switching system controls the second rate processing link to process the second transmission channel; wherein one of the second rate processing links occupies two transmission channels.

202. And the switching system performs rate switching processing on the second rate signal output by the second rate processing link so as to enable the second rate signal to enter the branch FPGA port.

203. And the switching system directly transmits the first rate signal to the branch FPGA port through the first rate processing link.

204. If the branch FPGA port is in the second rate mode, the switching system controls the first rate processing link to process the first transmission channel into the second transmission channel; wherein one of the first rate processing links occupies one transmission channel.

205. And the switching system directly transmits the first rate signal output by the first rate processing link to the branch FPGA port.

206. And the switching system directly transmits the second rate signal to the branch FPGA port through the second rate processing link.

207. If the branch FPGA port is in the third rate mode, the switching system transmits the first rate signals output by any N first rate processing links to the branch FPGA port together; wherein N is a natural number not less than 1.

208. The switching system transmits the second rate signals output by any M second rate processing links to the branch FPGA ports together; wherein M is a natural number not less than 1.

In the embodiment of the present application, when the first rate is 1G rate and the second rate is 2.5G rate, if the 1G port occupies one channel, the 2.5G port may occupy two channels similarly. The scheme supports two rate modes, a single branch can be configured into a 1G rate mode (assuming that the branch is 24 ports), a 2.5G rate mode (only 12 ports are active at this time) and a 10G rate mode (only 3 ports are active at this time), and each branch rate mode is completely independent.

For example, as shown in fig. 11, the aggregate relationship between the downstream channel and the 10G port is described (when the third rate is in the 10G rate mode). The switching system can arbitrarily select the aggregation of 8 channels from 1G downlink processing link or 2G downlink processing link to the 10G optical port.

209. When the branch FPGA port receives message data information sent by a certain device, the switching system identifies a device type identification field in the message data information to determine whether the certain device is a signal receiving device or a signal sending device.

As an alternative implementation, in an embodiment of the present application, the switching host of the present application uses a specific communication protocol with the transmitting device (TX) and the receiving device (RX). When the TX and RX are accessed to the exchange host, the equipment type identification field is arranged in the data message, and the exchange host can automatically identify whether the data message is TX or RX through the equipment type identification field, and meanwhile, when the uplink and downlink are processed, the two conditions are respectively distinguished and considered, so that the same port of the exchange host can be self-adaptive to TX/RX equipment.

210. When a signal instruction of path shifting is received, the switching system deletes an initial channel used for establishing a link between a certain branch FPGA port and another branch FPGA port, and starts a redundant channel used for establishing a link between the certain branch FPGA port and the another branch FPGA port.

As an optional implementation manner, in the embodiment of the application, the path can be effectively managed through software, and the path can be copied, moved and deleted. For example, the copying process of the present application is as follows: for example, the branch 0 port 5 and the branch 4 port 3 are linked by using the path 0, and the branch 0 port 5 can also be linked by using the path 0 and other ports, so that the copying process from the path one to the path two is realized.

As an alternative implementation manner, in the embodiment of the present application, the moving process of the present application is as follows:

1) For example, branch 0 port 5 establishes a link with branch 4 port 3 using path 0;

2) Branch 0 port 5 may also establish a link with branch 4 port 3 using redundant path 3;

3) Deleting the path 0 of the original established link only keeps the redundant path 3, which is equivalent to realizing the moving from the path 0 to the redundant path 3, and the whole moving process can ensure the link to be continuous. The deletion process is included in the move process.

211. When a signal instruction for starting the redundant channel is received, the switching system configures the redundant vertical channel of the signal sending port, the vertical channel and the redundant horizontal channel of the signal receiving port, the transmission channel from the branch FPGA to the trunk FPGA and the transmission channel from the trunk FPGA to the branch FPGA respectively.

212. And the switching system controls the transmission channel from the trunk FPGA to the branch FPGA to enable.

213. When a signal instruction for not starting the redundant channel is received, the switching system configures a vertical channel and a horizontal channel of the trunk FPGA, a transmission channel from the branch FPGA to the trunk FPGA and a transmission channel from the trunk FPGA to the branch FPGA respectively.

214. And the switching system controls the transmission channel from the trunk FPGA to the branch FPGA to enable.

As an alternative implementation manner, in the embodiment of the present invention, the entire exchange process is configured and managed by software, and the flow is shown in step 211 to step 214:

1. if redundant channels are not used, the method comprises the following steps: 1) Configuring a horizontal channel; 2) Configuring a vertical channel; 3) Configuring a channel branching to a backbone; 4) Configuring a trunk to branch channels; 5) Enabling trunk to branch channels.

2. If redundant channels are used, this includes: 1) Configuring a TX end redundant vertical channel; 2) Configuring an RX end redundancy horizontal channel; 3) Configuring an RX end vertical channel; 4) Configuring a channel branching to a backbone; 5) Configuring a trunk to branch channels; 6) Enabling trunk to branch channels.

In the embodiment of the invention, the data format adopts a private customized protocol, is not an IP architecture, and the traditional IP type equipment cannot access the exchange host. Meanwhile, when the data enters the port, a scrambling technology is adopted, and when the data exits the port, descrambling is needed to recover correct data. The implementation process of the scrambling technology is as follows: and carrying out logic operation on the normal data by adopting a specific polynomial to obtain scrambling data. At the receiving end, it is necessary to know what this specific polynomial is in particular to correctly descramble, so as to prevent data from being stolen and decoded.

In the embodiment of the present application, as shown in fig. 6, one of the trunk FPGAs includes at least X branch FPGAs, and one of the branch FPGAs includes at least Y branch FPGA ports; wherein the X and the Y are natural numbers not less than 1, respectively.

As an alternative implementation, in an embodiment of the present application, as shown in fig. 6, a switch fabric architecture using a single backbone chip, the architecture of the present application using multiple backbone chips is substantially the same as that of a single backbone. In fig. 6, a single trunk may be connected to a maximum of 16 branches, each branch may support 24-32 ports, each branch is connected to the trunk by using 4 pairs of 10G services, and each pair of 10G services may include 8 channels, for a total of 32 channels. Through the exchange configuration of software, the exchange of any port in a single branch can be realized, and the exchange of any port between branches can also be realized.

As an optional implementation manner, in the embodiment of the present application, the present application can effectively solve the problems faced by the video and circuit switching matrices of the current mainstream, and is highlighted in the following aspects:

1) The application adopts FPGA chip to independently develop switching logic, for example, adopts one trunk FPGA to realize the full switching of 512 ports, and adopts two trunk FPGAs to realize the full switching of 1024 ports. The increase of the number of the chips is in direct proportion to the increase of the port scale, and the exchange scale can be infinitely increased theoretically;

2) The invention not only supports the port point-to-point switching mode, but also supports the point-to-multipoint and multipoint-to-point switching mode. The port of the present invention supports three rates: the three rates of 1G, 2.5G and 10G are flexible and configurable, so that the cross exchange between 1G and 1G, between 2.5G and between 1G and 2.5G can be realized, and meanwhile, the aggregation from 1G ports and 2.5G ports to 10G optical ports can be supported;

3) The port is adaptive, and the port can automatically identify whether a transmitting end (TX) or a receiving end (RX) is accessed, so that the port is greatly convenient for engineering implementation and layout and wiring in large-scale application.

4) The method solves the problem of path management, supports redundant paths and can move, copy and delete the paths;

5) The security problem is solved, a non-IP architecture is adopted, and meanwhile, the port data is scrambled.

It can be seen that implementing the alternative multi-rate circuit-switched approach described in fig. 2 is capable of supporting a plurality of switching modes between different rates.

In addition, the implementation of the other multi-rate circuit switching method described in fig. 2 can effectively solve the problem that the switching scale is difficult to expand.

Example III

Referring to fig. 3, fig. 3 is a schematic diagram of a switching system according to an embodiment of the invention. As shown in fig. 3, the switching system 300 may comprise a first control unit 301, a processing unit 302, a second control unit 303, and a transmission unit 304, wherein:

The first control unit 301 is configured to control the second rate processing link to perform a transmission channel two-to-one process if the branch FPGA port is in the first rate mode; wherein one of the second rate processing links occupies two transmission channels.

And the processing unit 302 is configured to perform rate switching processing on the second rate signal output by the second rate processing link, so that the second rate signal enters the branch FPGA port.

A second control unit 303, configured to control, if the branch FPGA port is in the second rate mode, the first rate processing link to perform processing of changing the transmission channel one to two; wherein one of the first rate processing links occupies one transmission channel.

And the transmission unit 304 is configured to directly transmit the first rate signal output by the first rate processing link to the branch FPGA port.

It can be seen that implementing the switching system depicted in fig. 3 is capable of supporting a plurality of switching modes between different rates.

In addition, the switching system described in fig. 3 is implemented to support not only the switching of the same rate but also the switching between different rates, so that the switching modes are flexible and various.

Example IV

Referring to fig. 4, fig. 4 is a schematic structural diagram of another switching system according to an embodiment of the present invention. The switching system of fig. 4 is optimized by the switching system of fig. 3. In comparison with the switching system of fig. 3, the switching system of fig. 4 further includes:

as an optional implementation manner, in an embodiment of the present invention, the transmitting unit 304 is further configured to transmit, when the port of the branch FPGA is in the third rate mode, the first rate signals output by any N first rate processing links to the branch FPGA together; wherein N is a natural number not less than 1.

As an optional implementation manner, in an embodiment of the present invention, the transmitting unit 304 is further configured to transmit the second rate signals output by any M second rate processing links together onto the branch FPGA ports; wherein M is a natural number not less than 1.

For example, as shown in fig. 11, the aggregate relationship between the downstream channel and the 10G port is described (when the third rate is in the 10G rate mode). The transmission unit 304 may arbitrarily select the aggregation of 8 channels from 1G downlink processing link or 2G downlink processing link to the 10G optical port.

In comparison with the switching system of fig. 3, the switching system of fig. 4 further includes:

as an optional implementation manner, in an embodiment of the present application, the transmitting unit 304 is further configured to directly transmit the first rate signal to the branch FPGA port through the first rate processing link when the branch FPGA port is in the first rate mode.

As an optional implementation manner, in an embodiment of the present application, the transmitting unit 304 is further configured to directly transmit, when the branch FPGA port is in the second rate mode, the second rate signal to the branch FPGA port through the second rate processing link.

and the identifying unit 305 is configured to identify, when the branch FPGA port receives the message data information sent by a certain device, a device type identification field in the message data information, so as to determine whether the certain device is a signal receiving device or a signal sending device.

As an alternative implementation, in an embodiment of the present invention, the switching host of the present invention uses a specific communication protocol with the transmitting device (TX) and the receiving device (RX). When TX, RX and the switching host are accessed, the data message has a device type identification field, through which the identification unit 305 can automatically identify whether TX or RX is performed, and when uplink and downlink are processed, the two cases are respectively considered, so that the same port of the switching host can adapt to TX/RX devices.

and the deleting unit 306 is configured to delete an initial channel for establishing a link between a certain branch FPGA port and another branch FPGA port when a signal instruction for path movement is received, and start a redundant channel for establishing a link between the certain branch FPGA port and the another branch FPGA port.

3) The deleting unit 306 may delete the path 0 of the original link, only the redundant path 3 is reserved, which is equivalent to realizing the moving from the path 0 to the redundant path 3, and the whole moving process can ensure the link to be continuous. The deletion process is included in the move process.

and the configuration unit 307 is configured to configure the redundant vertical channel of the signal sending port, the vertical channel and the redundant horizontal channel of the signal receiving port, the transmission channel from the branch FPGA to the trunk FPGA, and the transmission channel from the trunk FPGA to the branch FPGA, respectively, when receiving the signal instruction for starting the redundant channel.

And a third control unit 308, configured to control a transmission channel from the trunk FPGA to the branch FPGA to enable.

as an optional implementation manner, in this embodiment of the present invention, the configuration unit 307 is further configured to configure, when a signal instruction that does not activate the redundant channel is received, a vertical channel and a horizontal channel of the trunk FPGA, a transmission channel from the branch FPGA to the trunk FPGA, and a transmission channel from the trunk FPGA to the branch FPGA, respectively.

As an optional implementation manner, in an embodiment of the present invention, the third control unit 308 is further configured to control a transmission channel from the trunk FPGA to the branch FPGA to enable.

In the embodiment of the application, the data format adopts a private customized protocol, is not an IP architecture, and the traditional IP type equipment cannot access the exchange host. Meanwhile, when the data enters the port, a scrambling technology is adopted, and when the data exits the port, descrambling is needed to recover correct data. The implementation process of the scrambling technology is as follows: and carrying out logic operation on the normal data by adopting a specific polynomial to obtain scrambling data. At the receiving end, it is necessary to know what this specific polynomial is in particular to correctly descramble, so as to prevent data from being stolen and decoded.

2) The application not only supports the port point-to-point switching mode, but also supports the point-to-multipoint and multipoint-to-point switching mode. The port of the present application supports three rates: the three rates of 1G, 2.5G and 10G are flexible and configurable, so that the cross exchange between 1G and 1G, between 2.5G and between 1G and 2.5G can be realized, and meanwhile, the aggregation from 1G ports and 2.5G ports to 10G optical ports can be supported;

It can be seen that implementing another switching system as depicted in fig. 4 is capable of supporting a plurality of switching modes between different rates.

In addition, the implementation of the alternative switching system described in fig. 4 can effectively solve the problem that the switching scale is difficult to expand.

Example five

Referring to fig. 5, fig. 5 is a schematic diagram illustrating a structure of another switching system according to an embodiment of the present invention. As shown in fig. 5, the switching system may include:

a memory 501 in which executable program codes are stored;

a processor 502 coupled to the memory 501;

the processor 502 invokes executable program codes stored in the memory 501 to execute any of the multi-rate circuit switching methods of fig. 1-2.

The embodiment of the invention discloses a computer readable storage medium which stores a computer program, wherein the computer program enables a computer to execute any one of multi-rate circuit switching methods shown in fig. 1-2.

The embodiments of the present invention also disclose a computer program product, wherein the computer program product, when run on a computer, causes the computer to perform some or all of the steps of the method as in the method embodiments above.

Those of ordinary skill in the art will appreciate that all or part of the steps of the various methods of the above embodiments may be implemented by hardware associated with a program that may be stored in a computer-readable storage medium, including Read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), programmable Read-Only Memory (Programmable Read-Only Memory, PROM), erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), one-time programmable Read-Only Memory (OTPROM), electrically erasable programmable Read-Only Memory (EEPROM), compact disc Read-Only Memory (Compact Disc Read-Only Memory, CD-ROM), or other optical disk Memory, magnetic disk Memory, tape Memory, or any other medium that can be used to carry or store data that is readable by a computer.

The above describes in detail a multi-rate circuit switching method and a switching system disclosed in the embodiments of the present invention, and specific examples are applied to illustrate the principles and embodiments of the present invention, where the above description of the embodiments is only for helping to understand the method and core ideas of the present invention; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the idea of the present invention, the present disclosure should not be construed as limiting the present invention in summary.

Claims

1. A multi-rate circuit-switched method, comprising:

2. The method according to claim 1, wherein the method further comprises:

if the branch FPGA port is in the third rate mode, transmitting the first rate signals output by any N first rate processing links to the branch FPGA port together; wherein, N is a natural number not less than 1;

3. The method according to claim 1, wherein the method further comprises:

4. The method according to claim 1, wherein the method further comprises:

5. The method according to claim 1, wherein the method further comprises:

6. The method of claim 5, wherein one backbone FPGA comprises at least X branched FPGAs, and one branched FPGA comprises at least Y branched FPGA ports; wherein the X and the Y are natural numbers not less than 1, respectively.

7. A switching system, the switching system comprising:

8. A switching system, the switching system comprising:

a memory storing executable program code;

a processor coupled to the memory;

the processor invokes the executable program code stored in the memory to perform the multi-rate circuit switched method of any of claims 1-6.