JPS5814105B2 - Half-duplex transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a half-duplex transmission system that directly connects devices with different data processing speeds and performs half-duplex data communication using only transmitting and receiving data lines. .

In a conventional half-duplex transmission device, switching between transmission and reception is performed by detecting the presence or absence of a carrier signal of the other station, detecting that the other station changes from a transmitting state to a receiving state, and then switching to the transmitting state.

There is no particular problem when performing mutual communication using a modem in this way, but when performing mutual communication by directly connecting terminals over a short distance without using a modem, a large number of timing signals are transmitted in a straight line. This created the problem of a large number of communication lines.

In consideration of the above points, the present invention directly connects devices with different data processing speeds without using conventional modulation/demodulation equipment, and transfers data so that mutual communication is performed only through communication lines of the transmitting and receiving data lines. Afterwards, a signal level indicating that the next data cannot be transmitted or received is transmitted to control the transmission and reception timing.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information transmission control section of a line connection device used in the half-duplex transmission system of the present invention.
As shown in FIG. 2, the information transmission control section 1 is connected to the central processing unit CPU1 of one terminal device through various signal lines on the left side of the figure, and further includes a receiving driver 2 and a transmitting driver 3 of the signal lines. It is connected to transmission lines SD and RD via the transmission lines SD and RD.

As shown in FIG. 2, the transmission lines SD and RD are connected to an information transmission control section 4 (same configuration as in FIG. 1) connected to the central processing unit CPU2 of the other terminal device as the transmission destination. The transmission destination line RD' is connected to the transmission destination line SD'.

Through the connections shown in FIG. 2, information transmission between the CPUs 1 and 2 is executed via the transmission control circuits 1 and 4.

In FIG. 1, reference numeral 11 denotes a parallel/serial conversion circuit, which converts received data into parallel signals and transmitted data into serial signals. For example, TR1602 manufactured by Western Digital Co., Ltd. is commercially available.

The outline is that a parallel buffer and a serial buffer for one character are provided inside the conversion circuit 11.
Parallel data from a central processing unit (hereinafter referred to as CPU) of the terminal device is stored in parallel buffers, the contents of the parallel buffers are transferred and stored in a serial buffer,
It is output from the serial buffer in the form of serial data.

In addition, the transmitted serial data is temporarily stored in a serial buffer, and then transferred and stored in a parallel buffer.
The parallel buffer outputs the data to the CPU in the form of parallel data.

When the transmission control circuit 1 is in the receiving state, data transmitted from the RD transmission line is stored in the serial buffer of the conversion circuit 11 in synchronization with the data clock (DATACLOCK) signal.

The data stored in this serial buffer is transferred to the parallel or sofa, and when the transfer is completed, the reception flag (R
When the EC FLG) signal is output to the CPU and the data read (DATA READ) signal is supplied from the CPU, the data in the parallel buffer is transferred to the data bus (DATA
BUS) and transferred to the CPU.

In addition, in the case of transmission, data load (DAT) is performed from the CPU.
When the A LOAD) signal is output and supplied to the conversion circuit 11, the parallel data on the data path is transferred to parallel buffers and stored. The data in the parallel buffers is transferred to the serial buffer, and when this transfer is completed, the transmission flag is (SEND FLG) signal is sent to gate 11
is output at one end.

Clock counter (CLOCK COUNTER) 1
3 is a character cycle generation circuit that counts data clocks and generates a pulse signal of one character period.

The reception end (REC END) detection circuit 14 is a circuit that enters the data reception state and detects that data of two or more consecutive characters has not been received. The determination is made by comparing the contents of 3 bits.

The reception control (REC CONTROL) flip-flop 15 is a gate control flip-flop for preventing a timing control signal sent after the end of data from being transmitted to the conversion circuit 11 during data reception.

After receiving the timing control signal, the reception control (REC CONTROL) circuit 16 detects that six characters have not been continuously received, and generates a trigger signal for the reception control flip-flop 15 that controls the gate of the reception data line RD. This circuit is composed of a multi-bit register, and a trigger signal is derived from the 6th bit.

The TIMING CONTROL flip-flop 17 is a flip-flop that generates a timing control signal after the end of the transmission data and performs control until reception preparation or retransmission preparation is completed.

Transmission/reception control (R/S TIMING CONTROL)
The circuit 18 is a circuit that forcibly puts the transmission line SD into a space state after the end of the transmission data and stops the transmission of the other station for a period of time until reception preparation is completed after transmission, and is composed of a plurality of bit shift registers. has been done.

A transmission control (S END CONTROL) flip-flop 19 is a flip-flop for controlling the input gate of a register 20 for timing control from the time transmission preparation is established until the receiving station is ready for reception.

The send control (SEND CONTROL) circuit 20 controls the send flag (SEND FLG) based on the fact that the other station is ready to receive (8 or more characters are in the marked state) and that the send preparation is established. A circuit consisting of shift registers.

The data output gate 21 is composed of an AND gate, and is a gate that operates to force the transmission line SD into a space for timing control.

Further, the data input gate 22 is composed of an OR gate, and is a gate that operates to separate a timing control signal from a partner station from a data signal.

Next, the operation of the block diagram of FIG. 1 will be explained together with the signal waveform diagram of FIG. 3.

Assuming that the transmission control circuit 1 is now in the receiving state, the signal shown in FIG. 3 is received from the RD transmission line via the reception driver 2.

The shaded portion in the MARIO signal is the transmission data, and the subsequent low (L) level signal is the timing control signal related to the present invention.

The data received through the gate 22 is input to the serial-to-parallel conversion circuit 11 and stored in a serial buffer within the conversion circuit 11.

Further, the received data is supplied to the respective reset terminals of a reception control circuit 16 and a transmission control circuit 20, which are constituted by shift registers, and the registers 16 and 20 are reset by a low (L) level signal of the data signal.

The data stored in the serial buffer of the serial/parallel conversion circuit 11 is transferred to parallel buffers,
When the transfer is completed, the reception flag (REC FLG)
The signal is output as a low level signal from the conversion circuit 11 via the inverter 23, and the reception end (REC END) detection circuit 14, which is made up of a register, is reset.

Read data (DATAREAD) from the CPU in response to the reception flag (RECFLG) signal sent to the CPU
When a signal is sent, one character of data is transferred from the parallel buffer to the CPU via the data bus.

By repeating the above operations, the transmitted data of a plurality of characters are sequentially received and transferred to the CPU, and the reception end detection circuit 14 is reset every time one character of data is transferred.

When the above data reception is completed, the reception flag (REC FLG) signal is no longer output from the conversion circuit 11.
The reset operation of the detection circuit 14 is stopped, and the detection circuit 1
4 is set to 1 by the clock signal from the clock counter 13.
The characters are counted and shifted sequentially.

When the shift operation of the detection circuit 14 composed of a register is performed for a predetermined number of digits (for example, 2 digits), the output of the mismatch gate 24 changes to a high level, and the signal shown in FIG. A state in which the above data have not been received is detected.

This ■ signal is supplied to the reset terminal of the flip-flop 15 via the inverter 25, and the flip-flop 1
5 is reset.

Therefore, the reset output of the flip-flop 15 is high (H
) level (signal C in Figure 3), the signal ■ is supplied to the OR gate 22, and the reception input terminal of the conversion circuit 11 becomes high (H signal).
) level and no longer receives data.

As shown in Fig. 3 (■signal), a low (L) level signal B2 is transferred after a certain period of time following the received data B1, and this signal is a signal indicating that the transmission destination station is not ready for transmission/reception. , this low (L) level signal period varies under the control of the CPU.

Further, the generation of the B2 signal will be explained in detail in the explanation of the transmission state.

As mentioned above, the reception control (REC CONTROL) circuit 16 repeats the reset operation while the reception data is being transmitted, but when the transmission of the reception data is completed, the reset operation is stopped and the clock counter 13 is reset. A shift operation is executed sequentially using the supplied clock signal in units of one character, and when a predetermined number of digits have been shifted, a high level signal is output and the flip-flop 15 is set via the inverter 26, and the reset output of the flip-flop 15 is set to low ( L) level.

Therefore, the conversion circuit 11 can take in the received data.

It should be noted that the time it takes for the signal to be output from the reception control circuit 16 is determined by the low (L) output after the data of the reception signal is transferred.
) is set longer than the level signal time.

Therefore, if this low (L) level signal B2 is not output from the partner station, in other words, if the partner station immediately becomes capable of transmitting and receiving, it will be able to receive within the predetermined time set in the control circuit 16. When the low level signal B2 is transferred from the other station, the reception control circuit 16 is reset, so the shift operation starts again from the moment the signal B2 changes from the low level to the high level, and the signal B2 changes to the high level. It becomes possible to receive the data within a predetermined period of time.

The above-mentioned reception completion detection signal outputted via the inverter 25 sets the flip-flop 27 to make its reset output low level, indicating the completion of reception to the CPU, and also indicating the completion of reception (in order to receive the next transmission/reception instruction). R.E.
C END) signal to the CPU.

Next, the case of the transmitting state will be explained.

When performing transmission following reception, the CPU performs CPU processing after receiving a reception end (REC END) signal, and transfers a transmission instruction (SEND) signal to the transmission control circuit 1 after a predetermined period of time.

When a transmission (SEND) signal is input to the transmission control circuit 1, the flip-flop 27 is reset, and the flip-flop 17 is also reset via the gate 28.

When the flip-flop 17 is reset, its set output changes to a low level to perform timing control (TIMING).
CONTROL) circuit 18 is reset and the reset state output (low level) of the control circuit 18 is sent to the inverter 2.
9 to the AND gate 21 to open the AND gate 21.

In addition, the send signal resets the flip-flop 19, and the reset output enables the send control circuit 20, which is composed of a shift register, to perform a shift operation, and a predetermined period of time (the same time as the receive control circuit 16) elapses. Afterwards, the high level signal shown in FIG. 3 is outputted from the control circuit 20, and the gate 12 is opened.

A signal from the conversion circuit 11 is supplied to the other input of the gate 12, and this signal is always at a high level when the serial buffer is empty.

Therefore, a transmission flag (FLG) signal is outputted to the CPU via the gate 12.

In response to this send flag (SEND FLG) signal, a data load (DATA LOAD) signal is transferred from the CPU to the parallel buffer of the conversion circuit 11.
The contents of the parallel buffers are transferred to the serial buffer, and the data is transferred to the other station via the gate 21 and driver 3.

When the serial buffer becomes empty, a high level signal is output from the conversion circuit 11 to the gate 12, a send flag (SEND FLG) signal is output to the CPU, and data load (DATA LOAD) from the CPU is performed.
The next data is taken into the conversion circuit 11 in response to the signal, and the same operation is repeated thereafter to transfer data of multiple characters.

When the data transfer is completed, the transmission ends (SE
ND END) signal is transferred from the CPU, flip-flop 19 is set, and its reset output becomes low (L
) level and send control (SEND CONTROL)
The input to the circuit 20 becomes low (L) level.

Therefore, the output from the transmission control circuit 20 will become low (
L) level, and the gate 12 is closed.

Furthermore, the flip-flop 17 is set by the SEND END signal, and the set output becomes a high level, and the timing control leg (TIMINGCON) is set.
The reset operation of the TROL circuit 18 is stopped, and after a predetermined period of time, its output signal (G signal in FIG. 3) becomes high (H) level, and a low (L) level signal is introduced to the gate 21 via the inverter 19. to close the gate 21 and close the gate 21.
] A low (L) level signal F2 following the data signal F1 is output onto the transmission line SD.

After that, when the CPU becomes capable of transmitting or receiving, a send (SEND) or receive (RFC) signal is transferred from the CPU to the transmission control circuit 11, the flip-flop 17 is reset, and its set output is set to low (L) level. Next timing control (TIMING CONTROL) circuit 18
is reset, the output of the control circuit 18 changes to a low (L) level signal as shown in Fig. 3 ◎ signal, and the inverter 2
9, a high (H) level signal is applied to the gate 21 to open the gate 21, and the level of the transmission line SD changes to high level as shown in FIG. 3 [F], indicating that transmission and reception are impossible. Transmission of the signal level indicated is stopped.

Thereafter, on the receiving station side, after a certain period of time, the outputs of the receiving control circuit 16 and the transmitting control circuit 20 become high (H) level, making it possible to transmit and receive.

As described above, half-duplex transmission is possible by coupling only the transmitting and receiving lines.

As described above, according to the present invention, in a half-duplex transmission device that performs mutual transmission using two lines, a transmitting line and a receiving line, in response to a signal (SEND END) indicating the end of data transfer from a processing unit (CPU). a timing control means 18 which is set to a set state and brought to a recent state in response to a signal (SEND or RFC) indicating a state in which the CPU is ready for transmission or reception; The control means (gate 21) causes the line to transmit a signal level indicating a state in which data cannot be transmitted or received, and the timing control means controls the control means for a certain period of time by this set operation to transmit or receive data on the transmission line. transmit a signal level indicating an impossible state,
Since the transmission and reception timing is controlled by the signal, the transmission and reception timing can be controlled using the data line with a simple control configuration including the timing control means and the control means. There is no need for wiring between devices, and half-duplex transmission can be performed by directly connecting two lines, the transmitting line and the receiving line. In addition, by using a data line with a fast processing time, status information indicating a status that cannot be transmitted or received can be transmitted at high speed. data can be sent and received, and measures can be taken according to high-speed data processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the information transmission control unit used in the present invention, FIG. 2 is a diagram showing the connection state of the transmission device according to the present invention, and FIG. 3 is a signal waveform used to explain the present invention. It is a diagram. SD...Transmission line, RD...Reception line, 16...Reception control circuit, 18...
- Timing control circuit, 20... Transmission control circuit.

Claims (1)

[Claims] 1. In a half-duplex transmission device that performs mutual transmission using two lines, a transmission line and a reception line, the device is set to a set state in response to a signal indicating the end of data transfer from a processing unit CPU, and the CPU a timing control means that is set to a reset state in response to a signal indicating a state in which data can be transmitted or received; and a timing control means controlled by the timing control means and causing a transmission line to transmit a signal level indicating a state in which data cannot be transmitted or received. and a control means, and the timing control means controls the control means for a certain period of time by this set operation to cause the transmission line to transmit a signal level indicating a state in which data transmission and reception is impossible, and controls the transmission and reception timing by the signal. A half-duplex transmission method consisting of