JPS626362A - Buffer circuit for inter-microprocessor serial communication - Google Patents

Abstract

PURPOSE:To improve both the efficiency and the speed of transmission of data by setting a buffer using a shift register between microprocessors and detecting the transmission mode and the reception mode for control of the buffer access. CONSTITUTION:A buffer circuit 13 is set between the data transmission lines of microprocessors 11 and 12. The circuit 13 contains a shift register 16, an R-S flip-flop 18 for state detection of both processors 11 and 12 and an access control circuit 23. The circuit 23 performs the control of the data written to and read out of the register 16 based on the output of the flip-flop 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a buffer circuit for serial communication of a microprocessor with improved transmission speed.

[Technical Background of the Invention] In recent years, the progress of information-related industries has been remarkable, and the range of information handled has also tended to expand. In addition, data communication is used to transmit data between microprocessors, such as sharing and using various information data among multiple microprocessors, or importing required data from the host computer by operating a terminal computer. There is also a tendency to expand.

When data communication is performed between multiprocessors, as shown in FIG. There is a conventional example in which signals are sent in parallel and data is sequentially transmitted on the data line 3 in units of bytes or words.

Furthermore, as shown in FIG. 4, there is a conventional example in which microprocessors 5 and 6 are connected by a data line 7, and a synchronization signal is sent by a line 8 to sequentially transmit data bit by bit.

[Problems in the background art] Among the above two data communication means, the first parallel data communication method has high transmission efficiency or transmission speed, but on the other hand, it requires a large number of data transmission lines and requires a large number of parallel The downside is that you will need a boat.

On the other hand, the second serial data communication method requires fewer data lines and fewer I10 ports than the parallel data communication method, but has the disadvantage that the transmission speed is significantly lower than that of the parallel method. .

[Object of the Invention] The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide an 877 circuit for serial communication between microprocessors that can improve transmission efficiency with a small number of transmission lines.

[Summary of the Invention] The present invention interposes a buffer consisting of a multi-stage shift register between a transmitting and receiving microprocessor, and forms a state detecting means for determining whether transmission and reception are possible. A control circuit is provided to control writing of data to the buffer and reading of old data based on the signal, thereby substantially improving data transmission efficiency and transmission speed.

[Embodiments of the invention] Hereinafter, the present invention will be specifically described with reference to the drawings.

FIG. 1 shows a buffer circuit according to one embodiment of the present invention;
The figure shows a timing chart for explaining the operation.

A buffer circuit 13 according to one embodiment is interposed between data transmission lines of two microprocessors (CPLI) 11 and 12.

That is, in the two microprocessors 11 and 12, the I10 port serves as the data output terminal 14 of the transmitting microprocessor 11, and the I10 port serves as the serial data input terminal 15.
10 between the output terminal 14 and the data terminal 10
15 and the data output terminal tlT D IN are respectively connected to the n-stage shift register 1.
6 is interposed.

Also, the data strobe signal output from the terminal 17 of the microprocessor 11 is transmitted to both microprocessors 11.1.
The microprocessor 12
The data acknowledge signal output from terminal 19 of R
- applied to the input end of the S flip-flop 18;
The output Q of the 8 flip 70 tube 18 is applied to the terminal 20 to which the data ready signal of the microprocessor 12 is input, and the output ready signal is applied to the terminal 21 to which the data accept signal of the microprocessor 11 is input. .12 Data can be written or read in a state where it can be confirmed whether transmission (writing) or reception (reading) is possible in both devices.

That is, the microprocessor 11 on the sending side detects that the data accept signal applied to the terminal 21 has become high level based on the output of the data acknowledge signal when the microprocessor 12 on the receiving side has completed reading and (taking) data. After confirming this, data can be written to the shift register 16. Furthermore, when this data has been sent for the amount that the shift register 16 can handle, the microprocessor 11 outputs a data strobe signal as a data transmission end signal, so that the output Q of the flip-flop 18 becomes high level. , this high level signal causes the data ready signal at the terminal 20 of the receiving microprocessor 12 to go high, confirming that data can be taken in, and then the receiving microprocessor 12 starts receiving the data. It can be performed.

The write clock (CLKz) output from the terminal 22 of the microprocessor 11 and the flip-flop 1
The output Q of 8 is the access control circuit 2 of the shift register 16.
AND circuit 2 via two-person OR circuit 24 forming 3
A read clock (CL) applied to one input terminal of the microprocessor 12
K2) and the output of the flip-flop 18 are applied to the other input terminal of the AND circuit 25 via a two-man OR circuit 27. Both of the above microprocessors 11.1
By passing the clock signals of 2 through the OR circuits 24 and 27, the transmitting side can output the clock when the data ready signal is at low level and can be transmitted, and the receiving side can also output the clock when the data accept signal is at low level. This allows the clock to be output in a state where it can be received. By applying the outputs of these OR circuits 24 and 27 to the clock terminal (CLK) 28 of the shift register 16 through the AND circuit 25, the transmitting side microprocessor 11 inputs the shift register 1 only when it is in a normal state where writing is possible.
Data can be written by applying a clock to 6. Further, the receiving microprocessor 12 is configured to apply a clock to the shift register 16 and read the written data only when the data can be read. In this way, data transmission can be performed in a highly reliable state.

The operation of the embodiment configured as described above will be explained below with reference to diagram M2.

The sending microprocessor 11 confirms that the data accept signal at the terminal 21 is at a high level, as shown by reference numeral 31 in FIG. 2(a), and then writes from the terminal 22 as shown in FIG. Figure 2 (C
) The transmission data Do, Dl, D2, ・[)n
-1 is output sequentially and the transmitted data is written into the shift register 16.

When the writing of data corresponding to the capacity of the shift register 16, for example n bits, is completed, based on this completion, the transmitting microprocessor 11 transfers the data from the terminal 17 to the data shown in FIG. The strobe signal is outputted and passed through the R-S flip 70 knob 18 as shown in Figure 2 (
As shown in e), the data ready signal applied to the terminal 20 is set to high level. In this case, the data accept signal to the terminal 21 is reset to low level.

This is because the data ready signal above has become high level.
The receiving microprocessor 12 knows that the data can be read (as indicated by reference numeral 33).
The data Do and Dt shown in (g) of the same figure are written into the shift register 16 by outputting a read clock as shown in (f) of the same figure.

. . . [)nt is sequentially read out, and after n bits of data are read out, the data acknowledge signal shown in FIG. This data acknowledge signal informs the transmitting microprocessor 11 that the data can be output via the R-S flip 70 knob 18, that is, the data accept signal is set to O-level, and data reception has been completed. Also, this data acknowledge signal causes the data ready signal to be sent to the terminal 20 to go to the a-level. In this way, the transmission of data for D bits is completed, and by subsequently performing the same operation, data transmission of the required capacity can be performed.

According to the above-mentioned embodiment that operates in this manner, between the sending and receiving microprocessors 11 and 12, the sending side writes n bits as one packet (n bits as one packet) to the shift register 16, and then , outputs a data strobe signal to set the data ready signal to high level, making it possible to read data to the receiving microprocessor 12, and in this state, the receiving microprocessor 1
2 takes in the written n-bit data, and when this reading is completed, it outputs a data acronym signal to inform the sending side that the data has been accepted, and then sends and receives the next packet of data. Therefore, data writing and reading speeds can be higher than when data is directly transmitted bit by bit between both microbe processors 11 and 12 without the need for synchronization signals, and therefore data can be transferred at high speed. transmission can be carried out.

Furthermore, by increasing the capacity of the shift register 16, the transmission speed can be increased.

In the timing chart shown in FIG. 2 above, for example, the transmitting side microprocessor 11 outputs a data strobe signal immediately after data transmission is completed, and sets the receiving side's data ready signal to a high level to continue data reading. I'm letting it go.

While the transmitting side is writing data to the shift register 16, the receiving side is disconnected from the data transmission system and performs other processing, and after the data ready signal becomes high level and the processing of the above functions is finished, the data is transferred. The microprocessor 12 can also be effectively operated by reading. The same thing can be said about the sending side.

This is effective when there is a large difference in the operating speeds of the microprocessors 11, 12 on the transmitting side and the receiving side.

Incidentally, the buffer circuit formed by the shift register 16 can be placed at any position on the line between the two microb O processors 11 and 12. Also, both microprocessors 11.1
By replacing the two connection terminals to form a pair of buffer 7 circuits, it is possible to transmit and receive data to and from each other.

In addition, when the buffer circuit 13 of the above embodiment is provided on one microprocessor side, the data for the switching signal is sent from the microprocessor 11 on the sending side, and then the input/output of the shift register 16 is controlled (via an analog switch, etc.). )
By switching the terminals 17, 21 and 19.20 of both microprocessors 11.12 (via analog switches, etc.), mutual transmission is possible without increasing the line between both microprocessors 11.12. It is also possible to switch between the mode and reception mode. The above terminals 17 and the like can be switched, for example, on the microprocessor 11 side, by switching the data strobe signal terminal 17 to the data ready terminal and the data accept signal terminal 21 to the data acknowledge terminal in reception mode. becomes the microprocessor of
The other microprocessor 12 becomes the microprocessor in transmit mode.

In the above embodiment, there is one transmitting side and one receiving side, but it is also possible to transmit data from one transmitting side microprocessor to a plurality of receiving side microprocessors.

[Effects of the Invention] As described above, according to the present invention, a buffer using a shift register having a capacity of multiple bits is interposed between microprocessors for data transmission, and a transmission mode and a reception mode can be detected. Since a buffer access control circuit using a method is provided, data can be efficiently transmitted at high speed by writing and reading data into and from the buffer in units of its capacity.

[Brief explanation of the drawing]

1 and 2 relate to an embodiment of the present invention; FIG. 1 is a configuration diagram showing a buffer circuit of the embodiment, FIG. 2 is a timing chart for explaining the operation of the embodiment, and FIG. 3 is a conventional A configuration diagram showing an example, FIG. 4, is a configuration showing another conventional example. 11.12... Microprocessor 13... Buffer circuit 14... (Data) output terminal 15... (Data) input terminal 16... Shift register 18... R-8 flip 70 tube 23... ...Control circuit agent Patent attorney Kensuke Norichika (and one other person) Figure 2 Figure 3 Figure 4

Claims (1)

[Scope of Claim] An inter-microprocessor serial communication device that communicates serial data between a plurality of microprocessors, comprising: a shift register having a buffer function between a data sending microprocessor and a data receiving microprocessor; control means for transmitting the end of transmission and data reception to the other party's microprocessor by a control signal, and writing a predetermined amount of data to the shift register and reading the predetermined amount of written data; A buffer circuit for serial communication between microprocessors.