JPH07152683A - Buffer memory circuit - Google Patents

Abstract

PURPOSE:To connect a transmission side with a reception side even they are different in data bus width by writing data from a receive data bus in plural buffer memories in order and outputting them to a transmission data bus at the same time. CONSTITUTION:This buffer memory circuit is equipped with plural beer memories 1 and 2 which are provided between the receive, data bu DB1 and transmission data bus DB2 and a writing control circuit 3 which controls the writing of those buffer memories 1 and 2. This writing control circuit 3 writes the data from the receive data bus DB1 in the buffer memories 1 and 2 in order and outputs the data, written in the buffer memories 1 and 2, to the transmission data bus DB2 at the same time. Consequently, the difference in data bus width between transmission-side equipment and reception-side equipment is absorbed. Consequently, even when the reception-side equipment and transmission-side equipment are different in data bus width, they can easily be connected without considering their data bus widths.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory circuit used in data transfer between devices, and more particularly to a buffer memory circuit for data transfer used when input / output data bus widths are different. Is about.

[0002]

2. Description of the Related Art A conventional buffer memory for data transfer will be described with reference to FIG. FIG. 5 illustrates the connection between devices. 4 is a device on the data transmission side, 5 is a device on the data reception side, and a buffer memory 6 for data transfer is arranged between these devices 4 and 5. To be done. The devices 4 and 5 may be the receiving side or the transmitting side, respectively. Here, when the data communication speeds of the devices 4 and 5 are different, the data communication speed between the devices 4 and 5 is the speed of the device having the slow communication speed, and therefore, the device having the fast communication speed is the speed of these communication speeds. As a result of waiting for the time corresponding to the difference of, the operation speed of the device becomes slow.

In order to eliminate such problems and increase the operation speed, a structure is generally adopted in which a buffer memory for data transfer is connected between devices to absorb the difference in communication speed between the devices. . A FIFO memory (first-in first-out memory) is generally used as such a buffer memory for data transfer. In the example of FIG. 5, the device 4 uses the buffer memory 6 for data transfer.
To the device 5 and then the device 5 receives this data from the buffer memory 6 for data transfer. Further, in such data transmission and reception, direct memory access transfer (DMA transfer) for directly transferring data without using the CPU is used, whereby high-speed transfer is realized.

[0004]

By the way, conventionally, when data transfer between devices is performed using the buffer memory for data transfer as described above, the data bus width of the data transmitting side and the data receiving side are the same. There was a need. For this reason, the receiving side device and the transmitting side device must have the same data bus width, and devices with different data bus widths cannot be connected via a buffer for data transfer.

It is an object of the present invention to provide a buffer memory circuit for data transfer, which can connect the transmitting side device and the receiving side device even if the data bus widths thereof are different.

[0006]

In order to achieve this object, the present invention controls a plurality of buffer memories provided between a reception data bus and a transmission data bus, and controls writing to the plurality of buffer memories. A write control circuit is provided, and the write control circuit sequentially writes the data from the reception data bus into the plurality of buffer memories, and the data written in the plurality of buffer memories is simultaneously output to the transmission data bus.

[0007]

According to the present invention, the data from the reception data bus is sequentially written into the plurality of buffer memories, and the written data is simultaneously output from the plurality of buffer memories to the transmission data bus, whereby the transmission side and the reception side are connected. The difference in the data bus width of the equipment is absorbed. Therefore, even if the data bus widths of the receiving side device and the transmitting side device are different, these can be easily connected without considering the data bus width.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a buffer memory circuit for data transfer according to the present invention will be described with reference to FIG. The buffer memory circuit of this embodiment includes buffer memories 1 and 2,
It is composed of these write control circuits 3. For the buffer memories 1 and 2, for example, a FIFO memory is used,
The width of these data input bits matches the width of the reception data bus DB1. The data output bit width of the buffer memory circuit is equal to the sum of the data output bit widths of the buffer memory 1 and the buffer memory 2. Here, when the data bus widths of the input side and the output side are different, the wider data bus width is generally 2 ⁿ times (2 times, 4 times, ...) The narrower data bus width. In the example,
The data bus width on the input side is narrow, and the output side is 2 on the input side.
Although the description will be given assuming that the data bus width is double, when the data bus width of the transmission data bus DB2 is four times or more than the data bus width of the reception data bus DB1, the number of buffer memories also becomes four or more. .

The buffer memories 1 and 2 are the reception data bus D.
Input the data from B1. And the write control circuit 3
This data is written in these buffer memories 1 and 2 by the signal from the buffer. Write control circuit 3
Receives the reception clock signal CS and the reception DMA transfer mode signal DS, and inputs the write signal 3A or the write signal 3B to the buffer memory 1 or the buffer memory 2.
Is output.

In the buffer memory circuit of this embodiment, when receiving data, the receive DMA transfer mode signal DS first input to the write control circuit 3 is validated. Next, data is input from the reception data bus DB1 to the buffer memories 1 and 2, and at the same time, the reception clock signal CS is input to the write control circuit 3. Here, the write control circuit 3 identifies how many times the reception clock of the reception clock signal CS has been received since the reception DMA transfer mode signal DS was input, and if the reception clock signal CS is the first time, the write signal 3A to the buffer memory 1 is sent, A write signal 3B is output to the buffer memory 2 for the second time, and a write signal 3A is output to the buffer memory 1 for the third time. That is, when the reception clock is the nth time, and when n is an odd number, the write signal 3A is output to the buffer memory 1,
If it is an even number, a write signal 3B is output to the buffer memory 2, and the data write processing in the buffer memories 1 and 2 is thereby performed.

When the data reception is completed, the reception DMA transfer mode signal DS becomes invalid. Then, the write control circuit 3 outputs the write signal 3B to the buffer memory 2 if the reception clock n at this end is an odd number and the above-mentioned write process is an odd number, and similarly ends at an even number. If so, the process ends. This operation is to make the data amounts written in the buffer memory 1 and the buffer memory 2 match.
That is, at the time when the reception DMA transfer mode signal DS becomes invalid, the last written buffer memory is
If it is not the buffer memory 2 in which the writing process is performed last, the buffer memory 2 not written is pseudo so that the capacity of the buffer memory 1 written last and the capacity of the buffer memory 2 not written match. That is, the operation of outputting a specific write signal is performed. By this operation, the capacities of all the buffer memories 1 and 2 are always the same when the reception DMA transfer is completed.

On the other hand, when transmitting data, the transmission data 1A which is the output of the buffer memory 1 and the transmission data 2A which is the output of the buffer memory 2 are simultaneously output. As a result, data can be transmitted with a data width twice the received data width, that is, data with different received data width and transmitted data width can be transferred.

Next, the operation of the embodiment, particularly the operation of the write control circuit 3 will be described in more detail with reference to FIGS. Here, FIG. 2 more specifically shows the circuit of the embodiment, and FIG. 3 is a time chart of the received data. Then, as shown in FIG. 2, the case where the reception data width of the buffer memories 1 and 2 for data transfer is 8 bits and the transmission data width is 16 bits is taken as an example. Further, in the configuration of FIG. 2, 8-bit reception data input from the reception data bus DB1 is connected to the buffer memory 1 and the buffer memory 2, respectively. The outputs of buffer memories 1 and 2 are also used in parallel to form the 16 bits of transmit data output. Further, the write signals 3A and 3B from the write control circuit 3 are connected to the write signal inputs W bar of the buffer memories 1 and 2, respectively.

The write control circuit 3 is composed of a JK flip-flop 31, a D-type flip-flop 32, and another logic element which plays a role of a delay element, and outputs the receive DMA transfer mode signal DS and the receive clock signal CS. It also serves as an input and outputs the above-mentioned write control signals 3A and 3B to the buffer memories 1 and 2.

The write control circuit 3 configured as above
In the initial state, the JK flip-flop 31 and the D-type flip-flop 32 are in the reset state. In this reset state, the receive DMA transfer mode signal DS becomes valid, and the receive data is input via the receive data bus DB1. Furthermore, the reception clock signal CS
Comes in. Then, the write signal 3 is input by the output Q of the JK flip-flop 31 and the input of the reception clock.
A becomes valid, and the received data is written in the buffer memory 1. Further, the reception clock signal CS is connected to the clock input C of the JK flip-flop 31 via the inverting logic element, so that when the reception clock signal CS falls, the clock input C of the JK flip-flop 31 rises. At this time, the output Q · Q bar of the JK flip-flop 31 is inverted.

When the next received data and the received clock signal CS come in, the write signal 3B becomes valid by the input Q of the JK flip-flop 31 and the received clock signal CS, and the received data is written in the buffer memory 2. . Further, at this time, similarly to when the reception clock signal CS falls, the outputs Q and Q of the JK flip-flop are inverted and become the same as the initial state. The same operation as above is repeated every time the received data arrives.

When the last received data is written in the buffer 1 by the write signal 3A, the amount of data written in the buffer memory 1 at this time becomes one word larger than the amount of data written in the buffer memory 2.

Next, the reception DMA transfer mode signal DS becomes invalid. At this time, since the clock input C of the D-type flip-flop 32 is input, the output Q of the D-type flip-flop 32 is output. Further, a gate element (two inverting logic elements) connected to the output Q bar of the D-type flip-flop 32
As a result, after the delay time of this element has elapsed, it is input to the reset terminal of the D-type flip-flop 32. Therefore, the output Q of the D flip-flop 32 becomes invalid after the lapse of the delay time. And the D-type flip-flop 3 at this time
2 output Q and J after the last received data is written
A pseudo write signal 3B is output by the output Q of the K flip-flop 31, and the data amounts written in the buffer memories 1 and 2 by this operation match.

The reset terminal R of the JK flip-flop 31 is connected to the reception DMA transfer mode signal DS via a gate element (three inverting logic elements). This is because the state of the JK flip-flop 31 is held until the pseudo write signal 3B is output.
This is for delaying a signal from entering the reset terminal R of the JK flip-flop 31.

FIG. 4 is a block diagram showing another embodiment in which the data bus width on the transmission side is four times as large as the data bus width on the reception side. Basically the same configuration as the example, buffer memory 1
The writing control circuit 3 controls the writing of data to 2.7.8. Note that, for example, when the data bus width on the transmission side is 8 times or 16 times the data bus width on the receiving side, it is sufficient to similarly use 8 or 16 buffer memories.

In the buffer memory circuit of FIG. 4, when data is received, the received data from the transmission data bus DB1 is sent by the write control signals 3A, 3B, 3C and 3D from the write control circuit 3 to the buffer memory 1. Two
-It is written repeatedly in sequence on 7/8. Also receive DM
If the last write is made to the buffer memory 2 when the A transfer mode signal DS ends and the data reception ends, the pseudo writing similar to the above is performed to the buffer memories 7 and 8, and The data amount of 2.7.8 is matched.

When data is to be transmitted, the transmission data 1A.2 which is the output of the buffer memories 1..2.7.8.
A, 7A and 8A are simultaneously output to the transmission data bus DB2. As a result, data is transmitted from the reception data bus DB1 to the transmission data bus DB2 with a data width four times the reception data width.

[0023]

According to the buffer memory circuit of the present invention, the buffer memory circuit can be used even when the input and output data bus widths are different, and these are connected even when the transmitting side device and the receiving side device have different data bus widths. can do. For this reason,
Even if a device having a data bus width different from that of the transmitting side is connected to the receiving side, these can be connected without changing the transmitting side device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a buffer memory circuit of the present invention.

FIG. 2 is a circuit diagram showing a more specific circuit configuration of the embodiment of FIG.

FIG. 3 is a timing chart of the circuit of FIG.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. .

FIG. 5 is a block diagram illustrating a buffer memory in the related art.

[Explanation of symbols]

 1 ・ 2 ・ 7 ・ 8 Buffer memory 3 Writing control circuit 4 Equipment 5 Equipment

Claims (1)

[Claims] 1. Receive data bus (DB1) and transmit data bus
Multiple buffer memories (1, 2) provided between (DB2)
And a write control circuit (3) that controls writing to multiple buffer memories (1, 2), and the write control circuit (3) allows the data from the receive data bus (DB1) to ) Are sequentially written to multiple buffer memories (1, 2), and the data are written to the transmit data bus (DB2).
A buffer memory circuit characterized by being simultaneously output to.