JPS63231566A - Inter-processor information transfer system - Google Patents

Abstract

PURPOSE:To omit the increment of the number of terminals for an LSI processor by adding an information transfer circuit to control connection between many I/O lines and the I/O lines of the LSI processor. CONSTITUTION:At the time of recognizing the transmission of a transfer request signal from a block to an information transfer request input signal terminal Ti2, a processor body 2 sends data to be transmitted and a control signal respectively to a writing information line 301 and a control line 302 and stores data in a register 13. Then, the processor body 9 sets up a flip flop (FF) 19 through a transfer data receiving line 600. Said status is sent to an information transfer request output signal terminal T02, an AND circuit 10 and a tray state buffer 15 are driven and the transmission data are sent only to a data output terminal D02. After the end of transmission, the processor body 2 resets the FF 19 through a reset control line 601 and informs said reset to the opposite processor through the terminal T02.

Description

Detailed Description of the Invention (Technical field to which the invention pertains) The present invention relates to a system that operates a multiprocessor using a plurality of LSI processors (processors realized by one LSI element). The present invention relates to a circuit that realizes information transfer between processors without increasing the number of signal terminals.

(Prior Art and its Problems) When one processor attempts to transfer information with a plurality of processors, the processors require input/output data lines and control lines corresponding to each processor.

When implementing a processor that is intended to transfer information with a plurality of processors into an LSI, it becomes impossible to provide all the input/output data lines in one LSI element because the number of terminals increases.

(Objective of the Invention) In order to solve this problem, the present invention provides an LSI processor with only one pair of data input/output terminals, and only controls the control signal terminal to which the total number of processors to which information is transferred (for example, two Install several pairs of adjacent processors in a time-limited space,
An information transfer circuit for transmitting and receiving data to and from a corresponding processor external to each LSI processor is added.

This information transfer circuit controls the connections between a large number of input/output lines and the input/output lines of the LSI processor.
The purpose is to eliminate the need to increase the number of terminals of the SI processor.

The drawings will be described in detail below.

(Configuration of the Invention) FIG. 1 is a block diagram of an embodiment showing the configuration of the present invention.

Reference numeral 1 denotes an LSI processor, which includes a processor main body 2 consisting of an arithmetic system and a control system, AND circuits 3 to 8, a register 13 for storing information to be transferred to other processors, and flip-flops 18 to 21.

Here, flip-flops 18 to 21 are installed to correspond to the transfer destination, and display a message indicating that information is to be transferred.

Reference numeral 30 denotes an information transfer circuit, which includes AND circuits 9-12, tri-state buffers 14-17, output buffers 22-25.degree. input buffers 26-29.

301 is a write information line to the register 13, 302 is a write control line to the register 13, 400 is a transfer data reception line from another processor, 500, 600, 700,
800 is a flip-flop set control line, 501,6
01゜701.801 is a flip-flop reset control line, D01 to DO4 are data output terminals installed corresponding to the processor to which information is transferred, and Dil to Di4 are data input terminals installed to correspond to the processor to which information is transferred. , TOI to TO4, and Ti1 to Ti4 are information transfer request output signal terminals installed corresponding to the information transfer destination processor and information transfer request input signal terminals from the information transfer destination processor.

FIG. 2 shows a wiring diagram of a multiprocessor system configured based on the present invention.
12 is a block including the LSI processor 1 and the information transfer circuit shown in FIG.

Only one pair of data input/output terminals are provided for each LSI processor, and information transfer request input/output signal terminals are provided for all pairs of processors to which information is to be transferred.

When the LSI processor of block 1111 wants to transfer information with another block, for example, the LSI processor of block 1011, it first confirms that there is no information transfer request from other LSI processors by connecting the terminals Til to Ti4 to the input buffers 26 to 26.
9 and is read into the processor body 2 and recognized.

If there is no request, the processor body 2 continues to send the data to be transmitted to the write information line 301 and a set control signal to the write control line 302, and set the data to be transferred to the register 13.

Next, the processor main body 2 turns on the flip-flop 18 through the flip-flop set control line 500.

The signal of the flip-flop 18 is passed through the information transfer request output signal terminal TOI of the output buffer 22 to the block 101.
1 LSI processor.

When the other LSI processor (block 1011) is ready for information transfer, a signal is sent back to the information transfer request input signal terminal Til.

The contents of the information transfer request input signal terminal Tit are read into the processor main body 2 through the input buffer 26, and the other party's LSI processor knows that transfer is now possible.

At the same time, the AND circuit 9 operates, operating the tri-state buffer 14 and sending the contents of the register 13 only to the data output terminal Dot.

AND circuits 9 to 12 and tristate buffers 14 to
17, the data is sent only to the LSI processor requested by the user, so the received data is sent to the data input terminal Dil.
~ Just do a wired-or of Di4.

The received data is wired-ORed and then read into the processor body 2 through the transfer data reception line 400.

When the other party's LSI processor completes the transfer, the transfer request signal sent to the information transfer request input signal terminal Til becomes '0'.

When the processor main body 2 detects this state, the processor main body 2 resets the flip-flop 18 through the reset control line 501 and ends the operation.

Next, when the processor body 2 recognizes that a transfer request signal has been sent to the information transfer request input signal terminal Ti2 from another block, for example, the block 1112, the processor body 2 writes the data to be transmitted to the information line 301. , a control signal is sent to the write control line 302, and the data is stored in the register 13.

Next, the processor body 2 sets the flip-flop 19 through the transfer data receiving line 600. This state is transmitted through the output buffer 23 to the information transfer request output signal terminal TO2.
At the same time, the AND circuit 10° tri-state buffer 15 is operated, and the transmission data is sent only to the data output terminal 002.

When the transmission is completed, the processor main body 2 resets the reset control line 6.
01 to reset the flip-flop 19, and notify the other processor through the information transfer request output signal terminal TO2.

Data is transmitted and received between LSI processors as described above.

(Effects of the Invention) As explained above, according to the present invention, an LSI processor does not need to provide data input/output signal terminals corresponding to all the processors to which information is transferred, and the LSI processor
By adding a small-scale information transfer circuit outside the processor, information transfer between the processor and other LSI processors can be sufficiently increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment showing the configuration of the present invention, and FIG. 2 is a wiring diagram of a multiprocessor system constructed based on the present invention. 1...LSI processor, 2...processor body. 3-8.9-12...AND circuit. 13... Register, 14-17... Tri-state buffer, 18-2
1... Flip-flop. 22-25...Output buffer, 25-29...Input buffer. 30... Information transfer circuit, 301... Write information line, 302... Write control line, 400... Transfer data reception line, 500, 600, 700, 800... Set control line, 501.601 , 701, 801... Reset control line, 001-DO4... Data output terminal. Dil~Di4...Data input terminal, TOI-TO4
...Information transfer request output signal terminal, Til to Ti4...
・Information transfer request input signal terminal.

Claims (1)

[Claims] In a system for transferring information between a plurality of LSI processors, means for storing data to be transmitted in each LSI processor, a pair of transmitting/receiving data input/output terminals, and an LS to be transferred.
means for displaying the I processor; and detection means for detecting whether or not there is a transfer request from the partner LSI processor; The information transfer circuit connected to the plurality of LSs to be transferred is connected to the information transfer circuit.
A plurality of pairs of transmitting/receiving data input/output terminals corresponding to the number of I processors, means for selecting an LSI processor having an information transfer request output signal on the display means and having an information transfer request input signal on the detecting means and transmitting data. An inter-processor information transfer system comprising: the LSI processor and the information transfer circuit as constituent units.