JPS58111546A - Communication controller - Google Patents

Communication controller

Info

Publication number
JPS58111546A
JPS58111546A JP56215275A JP21527581A JPS58111546A JP S58111546 A JPS58111546 A JP S58111546A JP 56215275 A JP56215275 A JP 56215275A JP 21527581 A JP21527581 A JP 21527581A JP S58111546 A JPS58111546 A JP S58111546A
Authority
JP
Japan
Prior art keywords
character
character processing
reception
transmission
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56215275A
Other languages
Japanese (ja)
Inventor
Kiichiro Ito
伊藤 喜一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56215275A priority Critical patent/JPS58111546A/en
Publication of JPS58111546A publication Critical patent/JPS58111546A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To provide a margin for the limit of processing time of a character processing section and to mitigate the design condition of the character processing section, by taking transmission and reception buffers as one and two characters, respectively and providing a circuit masking a reception processing request signal. CONSTITUTION:A character decomposing section 2b reads data for one character's share from a transmission register 4, transmits a serial data for one character's share to a line 1b and also a transmission character processing request 10 to a character processing section 3, which transmits the next data to the transmission buffer 4. The serial data of the section 2 from the line 1a is reconstituted into the parallel data and transferred to a reception register 5, and when a reception register 6 is vacant, a reception character processing request 12 is given and transferred to the register 6. The request 12 is masked at a mask circuit 7 for a prescribed time before the generation of the request 10.

Description

【発明の詳細な説明】 本発明は通信制御装置に関する。[Detailed description of the invention] The present invention relates to a communication control device.

オンライン情報処理システムにおいて、中央処理装置系
と通信回線の間に存在し、中央処理装置と遠隔地にある
多種多様の端末装置間のデータ送受信を制御する通信制
御装置の基本機能は、伝送文字の分解と組立て1通信回
線の接続制御と状態監視、g49制御およびあらかじめ
定めらnた手順に従った伝送制御などの処理である。一
般に1この種の通信制御装置は前記中央制御装置へのプ
ログラム割込みを減らして処理能力を向上させるために
バッファリング機能をもち、データを最低1文字に組み
立て、前記中央処理装置との間のデータ授受を制御する
In an online information processing system, the basic function of the communication control device, which exists between the central processing unit system and the communication line and controls the transmission and reception of data between the central processing unit and a wide variety of terminal devices located in remote locations, is to Disassembly and Assembly 1 Processes include connection control and status monitoring of communication lines, G49 control, and transmission control according to predetermined procedures. In general, 1. This type of communication control device has a buffering function in order to reduce program interruptions to the central control unit and improve processing capacity, and assembles data into at least one character, and transfers data between it and the central processing unit. Control giving and receiving.

従来の通信制御装置は、通信回線へ/からの送受信デー
タ(シリアルデータ)t−1文字単位に分解を組立てを
行う文字分解組立部と、該文字分解組立部へ/から1文
字単位でキャラクタデータ(パラレルデータ)を送受し
且つ伝送制御手屓に従った制御などの処理を行う文字処
理部を有し、前記文字分解組立部の送信側および受信、
側にはそnぞn前記文字処理部から/への1文字分のパ
ラレルデータ(通常8ビツト)を保持する送信キャラク
タバッファおよび受信キャラクタバッファを備え構成さ
nる。この通信制御装置から通信回線ヘシリアルデータ
を送信する場合、文字分解組立部Fi1文字分のデータ
をシリアルデータに分解して通信回線へ送出し、この送
出全完了すると次の送出データを送信キャラクタバッフ
ァから読み出して(このとき送信キャラクタバッファは
1空き”になる)このデータ送出を継続するとともに2
文字処理部へ送信文字処理要求を送出する。文字処理部
はこの送信文字処理要求を処理してさらに次の送出文字
を送信キャラクタバッファへ転送/る。
A conventional communication control device includes a character disassembly and assembling unit that disassembles and assembles transmitted and received data (serial data) to/from a communication line in units of t-1 characters, and a character disassembly and assembly unit that disassembles and assembles data sent and received (serial data) to/from a communication line in character units. It has a character processing unit that transmits and receives (parallel data) and performs processing such as control according to transmission control specifications, and the transmitting side and receiving side of the character disassembly and assembly unit,
On the side, there is a transmitting character buffer and a receiving character buffer for holding one character's worth of parallel data (usually 8 bits) from/to the character processing section. When transmitting serial data from this communication control device to a communication line, the character disassembly/assembly unit Fi decomposes data for one character into serial data and sends it to the communication line, and when this transmission is completely completed, the next sending data is sent to the transmission character buffer. (At this time, the transmission character buffer becomes 1 free space.) This data transmission continues, and 2
Sends a transmission character processing request to the character processing section. The character processing section processes this transmission character processing request and further transfers the next transmission character to the transmission character buffer.

通信Mlへの文字送出は一定時間Tの間に1文字の速さ
で行わnるので送信文字処理要求はこの一定時間Tの間
隔で行わnることになる。一方、通信回線からシリアル
データを受信する場合は、文字分解組立部は前記受信ク
リアルデータをパラレルデータに組立てて受信キャラク
タバッファへ転送するとともに文字処理部へ受信文字処
理要求を送出する。文字処理部はこの受信キャラクタバ
ッファに保持さnた前記パラレルデータtgみ取って処
理を行う。こnによって受信キセラクタバッファは″空
き”となる。文字処理要求は、前記一定時間′1゛の間
隔で発生するので文字処理部はこn全1幀次受1gして
処理7行う。
Since characters are sent to the communication M1 at a rate of one character during a fixed time T, transmission character processing requests are sent at intervals of this fixed time T. On the other hand, when serial data is received from a communication line, the character disassembly and assembling section assembles the received clear data into parallel data, transfers it to the reception character buffer, and sends a reception character processing request to the character processing section. The character processing section reads and processes the parallel data tg held in the received character buffer. This makes the receive xelector buffer "empty". Since character processing requests are generated at intervals of the predetermined time '1', the character processing section receives all of these requests once and performs processing 7.

以上の説明によジ明らかなように5文字処理部が1つの
送信文字処理要求または受信文字処理要求をそtぞn前
記−足時間T以内に処理を終了しないと、アングラ/ま
たはオーバランが発生する。
As is clear from the above explanation, if the 5 character processing unit does not finish processing one transmission character processing request or one reception character processing request within the above-mentioned time T, an underground/overrun will occur. do.

すなわち、送信側では送信キャラクタバッファがパ空き
”になるとともに次の送信文字処理要求か発生し一定時
間T以内に″′空f!!ζダ塞がv″にする必要がある
が、こnができずに@空き”のま1のとき4アンダラン
が発生し、一方受信側では受信キャラクタバッファが0
空き”にならないうちに次の受信文字処理要求が発生す
るのでオーバランの状態となる。
That is, on the sending side, as soon as the transmission character buffer becomes empty, the next transmission character processing request is generated, and within a certain time T, the transmission character buffer becomes empty. ! It is necessary for ζ data to be set to v'', but when this is not possible and @empty remains at 1, a 4 underrun occurs, and on the other hand, on the receiving side, the receive character buffer is 0.
Since the next received character processing request occurs before the space is filled, an overrun state occurs.

上記の送信文字処理要求と受信文字処理要求は。The above sending character processing request and receiving character processing request are.

前述したように、千n−t’n、 1文字間隔すなわち
一定時間Tの間隔で発生するが、両者の発生のタイミン
グは互いに独立であるため、第1図に示すような場合が
現出する。第1図は一般的送信文字処理要求と受信文字
処理要求の発生タイミングの一例を示すタイムチャート
である。同図は受信文字処理要求が一定時間Tの間隔で
順次発生し、また送信文字処理要求が前記受信文字処理
要求より時間Δtだけ遅nて且つ前記一定時間Tの間隔
で順次帖生する場合を示す。
As mentioned above, 1,000n-t'n occurs at one-character intervals, that is, at intervals of a certain time T, but since the timing of both occurrences is independent of each other, a case like the one shown in Figure 1 appears. . FIG. 1 is a time chart showing an example of the generation timing of a general transmission character processing request and a reception character processing request. The figure shows a case where received character processing requests are generated sequentially at intervals of a fixed time T, and transmission character processing requests are delayed by a time Δt than the received character processing requests and are issued sequentially at intervals of the fixed time T. show.

この場合、従来の通信制御装置では時間′1゛+Δtの
間に1つの送信文字処理要求と1つの受信文字処理要求
を処理しないと、アンダランまたはオーバランの状態と
なることが明らかである。文字処理部での文字処理に要
する時間は伝送制御手順上の処理を行う際や文字格納処
理を行う際の条件によp文字ごとに異なるが1文字の中
には特別に長い処理時間を要するものがある。従って前
記時間T+Δtの間に上記の両文字処理要求を処理でき
る文字処理部は、設計条件が厳しいため極めて高価にな
るという欠点があった。
In this case, it is clear that if the conventional communication control device does not process one transmission character processing request and one reception character processing request during the time '1'+Δt, an underrun or overrun state will occur. The time required for character processing in the character processing unit differs for each character depending on the conditions when performing transmission control procedure processing and character storage processing, but some characters require a particularly long processing time. There is something. Therefore, a character processing section capable of processing both of the above character processing requests during the time T+Δt has a disadvantage in that it is extremely expensive due to severe design conditions.

本発明の目的は、文字処理部での処理時間リミットに余
裕をもたせ文字処理部の設計条件を緩和した通信制御装
v1kを提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a communication control device v1k in which the processing time limit of the character processing section is relaxed and the design conditions of the character processing section are relaxed.

本発明による通信6J1」御装置は1通信回線に対して
送受するデータ全文字単位に分解および組立てを行う文
字分解組立部と、該文字分解組立部を介して前記通信回
線へ送受する文字単位のデータの処理を行う文字処理部
を含み構成さγしる通信制御装置において、1文字分の
送信キャラクタバッファと、そnぞn1文字分の第1お
よび第2の受信キャラクタバッファと、前記文字分解組
立部からのマスク指示により定めらnた部間前記文字処
理部への受信文字処理要求の送出リードの信号を切断す
るマスク回路を前記文字分!Is組立部と前記文字処理
部との開に有することを特徴とする。
The "communication 6J1" control device according to the present invention includes a character disassembly and assembling section that disassembles and assembles all data sent and received to and from one communication line into character units, and a character disassembly and assembling section that disassembles and assembles all data transmitted and received to and from one communication line in character units, and a character disassembly and assembly section that disassembles and assembles all data transmitted and received to and from one communication line in character units. In a communication control device configured to include a character processing unit that processes data, a transmission character buffer for one character, first and second reception character buffers for each one character, and the character decomposition A mask circuit that cuts off the signal for sending out a received character processing request to the character processing section between the n sections determined by the mask instruction from the assembly section for the number of characters! The Is assembling section is located between the character processing section and the character processing section.

次に第2図および第3図を参照【7て本発明について説
明する。
Next, the present invention will be explained with reference to FIGS. 2 and 3.

第2図は本発明の通信制御装置の一実施例を示すブロッ
ク図である。本実施例は1文字単位のバラレルデータを
シリアルデータに分解して送信側通信回、*ibへ送信
する文字分解部2bと、受信n通信回線1.aから受信
したシリアルデータを1文字単位にパラレルデータに組
立てる斐字組立部2aとから成る文字分解組立部2と、
送信文字処理要求10または受信文字処理要求11によ
り文字単位の前記パラレルデータの処理を行う文字処理
部3を備え、該文字処理部3と前記文字分解部2bとの
間には前記文字処理部3からの1文字分のパラレルデー
タを保持する送信レジスタ4を接続し、また前記文字組
立部2aと前記文字処理部3との間には前記文字組立部
2aからのそnぞn1’を手分のパラレルデータを保持
する受信レジスタA5および受信レジスタl’6を直列
に接続し。
FIG. 2 is a block diagram showing an embodiment of the communication control device of the present invention. This embodiment includes a character decomposition unit 2b that decomposes parallel data in units of characters into serial data and transmits it to the transmitting side communication line *ib, and a receiving n communication line 1. a character disassembly and assembling section 2, which assembles the serial data received from a into parallel data character by character;
A character processing unit 3 is provided which processes the parallel data in units of characters in response to a transmission character processing request 10 or a reception character processing request 11, and the character processing unit 3 is provided between the character processing unit 3 and the character decomposition unit 2b. A transmitting register 4 that holds parallel data for one character from the character assembling section 2a is connected between the character assembling section 2a and the character processing section 3. A reception register A5 and a reception register l'6 holding parallel data are connected in series.

ざらに前記文字組立部2aと前記文字処理部3との間に
前記文字分解部2bからのマスク指示11によV前記受
信文字処理要求12の前記文字処理部3への送出を所定
の期間禁止するマスク回路7を接続して構成さnる。
Roughly, between the character assembly section 2a and the character processing section 3, a mask instruction 11 from the character disassembly section 2b prohibits sending of the received character processing request 12 to the character processing section 3 for a predetermined period. It is configured by connecting a mask circuit 7 to

次に本実施例の動作について説明する。文字分解部2b
は1文字分のパラレルデータをシリアルデータに分解し
て送悟側通信回線1bへ送信し、この送出を死重すると
次の送出データを送信レジスタ4から読み取って(この
とき送信レジスタ41文字単位の7リアルデータを送信
側通信回#1jへ順次送信する。また、文字分解部2b
は前記送信文字処理要求が発生する所定時間前の時点で
マ発 スクメ示litマスク回路7へ与える。マスク回路7は
この指示に従って受信文字処理要求12の文字処理部3
への割込みをマスクする。一方、文字組立部2aは受信
側通信回@laからのシリアルデータを受信してパラレ
ルデータに組立て1文字分のキャラクタデータC)11
を受信レジスタA5へ転送し、受信レジスタB6が6空
き”であnは続いて受信レジスタA5の内容(前記キャ
ラクタデータU)il )?受信レジスタB6へ転送す
る〆とともに、受信文字処理要求12を発する。但し発
生タイミングによっては前記マスク指示11によってマ
スク回路7によp文字処理部3への割込みをマスクさn
る。文字組立部2aが次の1文字分のキャラクタデータ
CH鵞を受信したときは”空き”になった受信レジスタ
A5へ転送する。上記のマスクが解除さnたとき受信文
字処理要求12の割込みが行わn、受信レジスタB6の
内容(前記キャラクタデータCH,)が文字処理部3へ
読み取らn受信処理が行わnる。また受信レジスタA5
に保持さnている内容(前記キャラクタデータCH,)
は”空き“になった受信レジスタB6へ転送さnる。受
信側通信回1i!laからのシリアルデータの次の1文
字分のキャラクタデータCH3以降のキャラクタデータ
も同様に順次受信レジスタA5−受信レジスタB6−文
字処理部3へと転送さn受信処理が行わ扛る。
Next, the operation of this embodiment will be explained. Character decomposition unit 2b
decomposes one character's worth of parallel data into serial data and sends it to the sending side communication line 1b, and when this transmission is dead, reads the next sending data from the sending register 4 (at this time, the sending register 41 character unit) 7. Sequentially transmit the real data to the transmission side communication circuit #1j. Also, the character decomposition unit 2b
is given to the mask circuit 7 at a predetermined time before the transmission character processing request is generated. In accordance with this instruction, the mask circuit 7 processes the character processing unit 3 of the received character processing request 12.
Mask interrupts to. On the other hand, the character assembling unit 2a receives serial data from the receiving side communication circuit @la and assembles it into parallel data, character data for one character C) 11
is transferred to the reception register A5, and the reception register B6 is 6 free. Then, the content of the reception register A5 (the character data U) is transferred to the reception register B6, and the received character processing request 12 is sent. However, depending on the timing of occurrence, the interrupt to the p character processing section 3 may be masked by the mask circuit 7 according to the mask instruction 11.
Ru. When the character assembling unit 2a receives character data CH for the next character, it transfers it to the reception register A5 which is now "empty". When the above-mentioned mask is released, an interrupt of a received character processing request 12 is made, and the contents of the reception register B6 (the character data CH,) are read into the character processing section 3, and reception processing is performed. Also, receive register A5
The contents held in (the character data CH,)
is transferred to the reception register B6 which is now "empty". Receiving side communication time 1i! Character data CH3 and subsequent character data for the next character of the serial data from la are similarly transferred sequentially to reception register A5 - reception register B6 - character processing section 3, where n reception processing is performed.

次に第3図は第2図における受信文字処理要求の割込み
マスク時間および文字処理部での処理リミットタイミン
グなどの関係の一例を示すタイムチャートである。同図
において、受信文字処理要求と送信文字処理要求の発生
の関係は第1図に示したものと同一としている。すなわ
ち、受信文字処理要求lR□は時点t01c発生し、以
後一定時間Il+の間隔で受信文字処理要求lR211
01〜が順次発生する。また送信文字処理要求”81は
紡記受信文字処理資求工、□より時間Δtだけ遅rt、
fc時点t1に発生し、以後前記一定時間Tの間隔で送
信文字処理要求”821 ”83 ’〜が順次発生する
ものとする。前記受信文字処理要求lR□は、その発生
時点10が受信文字処理要求割込みマスク時間−内にあ
るため、直ちに文字処理部3へ1Illり込むことがで
きず、前記マスク時間Tmが経過した時点t1で割込み
金行う(lR′□で図示した)。受信文字処理要求IR
2・lR31〜についても同様である。
Next, FIG. 3 is a time chart showing an example of the relationship between the interrupt mask time of the received character processing request and the processing limit timing in the character processing section in FIG. 2. In the figure, the relationship between the generation of received character processing requests and transmitted character processing requests is the same as that shown in FIG. That is, the received character processing request lR□ occurs at time t01c, and thereafter, the received character processing request lR211 is made at intervals of a certain time Il+.
01~ occur sequentially. In addition, the sending character processing request 81 is a request for processing received characters, rt delayed by time Δt from □,
It is assumed that the transmission character processing requests ``821'', ``83'', etc. occur in sequence at fc time t1, and thereafter at intervals of the predetermined time T. Since the received character processing request lR□ occurs at the time 10 within the received character processing request interrupt mask time, it cannot immediately enter the character processing unit 3, and the time t1 when the mask time Tm has elapsed. An interrupt fee is paid at (indicated by lR'□). Received character processing request IR
The same applies to 2.lR31~.

なお前記割込み受信文字処理要求IRI l〜はそnぞ
n前記送信文字処理要求’81’〜と同一時点tl+り
時間Tmは文字分解部からの禁止時間信号により所望の
値に設定することができ゛る。
Note that the interrupt reception character processing request IRI l~ is the same time point tl + time Tm as the transmission character processing request '81'~ can be set to a desired value by the inhibit time signal from the character decomposition unit. It's ringing.

以上説明したように1本実施例の通信制御ife!tは
1文字分の送信レジスタと2文字分の受信レジスタを備
えているので1文字処理部3は送信文字処理要求”81
tその発生時点t1から次の送信文字処理要求”siが
発生するまでの間、すなわち時り解除の時点tlから受
信文字処理要求lR3が発生するまでの間、すなわち時
点t3と時点t1との差の時間2T−Δを以内に処理す
nはよい。ここでΔt=T/2とすnば1文字処理部3
は1つの受信文字処理要求について1時間2T−Δt=
1.5T以内に処理すnばよいことになり、従来のもの
に比し処理リミットタイミングに余裕が生じる。また前
記時間Δtが前記マスク時間Tmよジ長い場合は受信文
字処理要求”R1l IR21”R31〜がマスクさn
ずに文字処理部3への要求となるのでこ扛ら受信文字処
理要求”R1’ ”R211R31〜がそnぞn送信文
字処理要求”81 t ”8□11931〜より前に処
理さnることになり受信文字処理要求lR1の発生時点
からみnは時間Δt+T以内にか生じる。
As explained above, the communication control ife! of this embodiment! Since t is equipped with a transmission register for one character and a reception register for two characters, the single character processing unit 3 sends a transmission character processing request "81".
tThe period from the time t1 when the next transmission character processing request ``si'' occurs, that is, from the time tl when the clock is released until the reception character processing request IR3 occurs, that is, the difference between the time t3 and the time t1. It is good to process n within the time 2T-Δ.Here, if Δt=T/2, n means that one character processing unit 3
is 1 hour for one received character processing request 2T-Δt=
This means that it is only necessary to process within 1.5T, and there is a margin in the processing limit timing compared to the conventional method. Further, if the time Δt is longer than the mask time Tm, the received character processing request "R1l IR21" R31~ is masked.
Therefore, the received character processing requests ``R1'' and ``R211R31~ will be processed before the transmitted character processing requests ``81t'' and ``8□11931~. Therefore, n occurs within time Δt+T from the time when the received character processing request IR1 is generated.

受信文字処理要求工、□と送信文字処理要求18□を処
理すnばよい。丁なわち、前記時間Δt+1゛以内にお
のおの〆1つの受信文字処理要求と送信文字処理要Xを
処理すnばよい。ここで前記時間′1m=T/2とTn
rJ:前Ae4間Δt + T〉i、 s Tとなり。
It is sufficient to process the received character processing request □ and the transmitted character processing request 18□. In other words, it is only necessary to process one received character processing request and one transmitted character processing request X within the above-mentioned time Δt+1. Here, the time '1m=T/2 and Tn
rJ: Before Ae4 Δt + T〉i, s T.

従来のものに比し処理リミットタイミングに余裕が生じ
る。
There is more margin in the processing limit timing than in the conventional system.

なお本実施例は本発明を制限するものではない。Note that this example does not limit the present invention.

すなわち、送信レジスタと受信レジスタAI文手分解組
立部に含めて溝成してもよいし、また1つの全2重回線
(1@の送信および受信通信回線)用を示したが複数の
全2重回線の場合は本実施例の通信制御装置を所要数設
けnばよいことはいうまでもない。
In other words, the transmitting register and receiving register may be included in the AI manual disassembly and assembly section to form a groove, or one full-duplex line (one @ transmitting and receiving communication line) is shown, but multiple full-duplex lines may be used. Needless to say, in the case of multiple lines, it is sufficient to provide the required number of communication control devices of this embodiment.

以上の説明により明らかなように本発明の通信制御装置
によ扛ば、文字処理時間+7 ミツトに余裕を持念せる
ことにより文字処理部の設計条件を大嘔に曖和すること
ができるので、特別に長い処理時間を要する文字があっ
てもそrに対する設計が容易となり、経済性が著しく向
上するという効果
As is clear from the above explanation, by using the communication control device of the present invention, the design conditions of the character processing section can be made extremely vague by giving a margin to the character processing time +7. The effect is that even if there are characters that require a particularly long processing time, it is easier to design for them, and the economy is significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は一般的送信文字処理要求と受信文字処理要求の
発生タイミングの一例を示すタイムチャート、gXZ図
は本発明の通信制御装置の一実施例を示すブロック図お
よび第3図は第2図における受信文字処理要求の割込み
マスク時間および文字処理部での処理リミットタイミン
グなどの関係の一例を示すタイムチャートである。 1aνlb−゛・°・・通信回線、2・・・・・・文字
分解組立部、3・・・・・・文字処理部、4・・・・・
・送信レジスタ、5゜6・・・・・・受信レジスタA、
B、7・旧・・マスク回路、10・・・・・・送信文字
処理要求、11・・・・・・マスク指示。 12・・・・・・受信文字処理要求。 第1 酷 41し 第 2 閉 h 第3図 @1    t2   t3
FIG. 1 is a time chart showing an example of the generation timing of a general transmission character processing request and a reception character processing request, gXZ is a block diagram showing an embodiment of the communication control device of the present invention, and FIG. 12 is a time chart showing an example of the relationship between the interrupt mask time of a received character processing request and the processing limit timing in a character processing section in FIG. 1aνlb-゛・°・・・Communication line, 2...Character disassembly and assembly section, 3...Character processing section, 4...
・Transmission register, 5゜6...Reception register A,
B, 7. Old mask circuit, 10... Transmission character processing request, 11... Mask instruction. 12... Received character processing request. 1st cruel 41st 2nd closed h Figure 3 @1 t2 t3

Claims (1)

【特許請求の範囲】[Claims] 通信回線に対して送受するデータを文字単位に分解およ
び組立てを行う文字分解組立部と、該文字分解組立部を
介して前記通信回線へ送受する文字単位のデータの処理
を行う文字処理部を含み構成さnる通信制御装置におい
て、1文字分の送信キャラクタバッファと、そnぞ2′
L1文字分の第1および第2の受信キャラクタバッファ
と、前記文字分解組立部からのマスク指示により定めら
nた期間前記文字処理部への受信文字処理要求送出リー
ドの信号を切断するマスク回路を前記文字分解組立部会
尭囃と前記文字処理部との間に有することt−特徴とす
る通信制御装置。
A character disassembly and assembling unit that disassembles and assembles data to be transmitted and received over a communication line into character units, and a character processing unit that processes data transmitted and received in character units to and from the communication line via the character disassembly and assembly unit. In the communication control device consisting of n, there is a transmission character buffer for one character, and two
a first and second reception character buffer for L1 characters, and a mask circuit that disconnects a read signal for sending a reception character processing request to the character processing section for a period of n determined by a mask instruction from the character disassembly and assembly section. A communication control device characterized in that the communication control device is provided between the character disassembly and assembly section group and the character processing section.
JP56215275A 1981-12-25 1981-12-25 Communication controller Pending JPS58111546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56215275A JPS58111546A (en) 1981-12-25 1981-12-25 Communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56215275A JPS58111546A (en) 1981-12-25 1981-12-25 Communication controller

Publications (1)

Publication Number Publication Date
JPS58111546A true JPS58111546A (en) 1983-07-02

Family

ID=16669608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56215275A Pending JPS58111546A (en) 1981-12-25 1981-12-25 Communication controller

Country Status (1)

Country Link
JP (1) JPS58111546A (en)

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