JP3192009B2 - Transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention is used for transferring communication data between two communication circuits. In particular, it relates to prevention of underrun and overrun of communication data.

[0002]

2. Description of the Related Art As a method of transferring communication data between two communication circuits, there are the following methods.
K (acknowledge signal) is returned to notify that data can be received and the next data can be received. (2) One response confirmation for a plurality of received data as represented by the HDLC procedure Are returned to the transmission source to notify that the next data can be received.

[0003]

However, in the above-mentioned method (1), since one response confirmation is returned for one data, the transfer overhead is large and the throughput cannot be increased. Further, since a response confirmation is generally returned by software control, there is a drawback that it is not suitable for increasing the communication speed.

In the method (2), a communication control LSI and a processor for performing the HDLC procedure between the two communication circuits are required, so that the structure is complicated and special software for communication control is required. thing,
There is a disadvantage that communication of about several Mb / s is the limit due to the performance limit of the communication control LSI and the like.

[0005] It is an object of the present invention to solve such a problem and to provide a transfer control method capable of high-speed data transfer with a relatively simple configuration.

[0006]

According to the transfer control method of the present invention, a transmitting communication circuit for sending data to a data communication line, a receiving communication circuit for receiving data from the data communication line, and a receiving communication circuit A higher-level processor for processing data received by the circuit; a receiving-side communication circuit configured to output a processing request to the higher-level processor each time a predetermined amount of data is received; In a transfer control method including a timing matching unit that temporarily stores the generated processing request and matches the request reception timing of the upper processor and a reception buffer memory that temporarily stores received data and transfers the received data to the upper processor. When the number of processing requests stored in the timing adjustment means reaches the first reference value, the communication circuit Ordered transmission stop for, after which the number of processing requests when it reaches the second reference value smaller than the first reference value, characterized in that it comprises a transmission control means for commanding the resumption transmitted to the transmission side communication circuit.

The transmission-side communication circuit includes a transmission buffer memory for storing transmission data, a clock generation circuit for determining transmission timing, and transmission means for transmitting data in accordance with a clock generated by the clock generation circuit. The circuit preferably has a configuration in which the generation of the clock is stopped by a transmission stop instruction from the transmission control means, and the generation of the clock is restarted by a transmission restart instruction.

[0008]

In the transfer of communication data between communication circuits, the remaining number of processing requests to the upper processor in the communication circuit on the receiving side is monitored, and the transfer is automatically controlled based on the number. Therefore, the transfer control by the host processor is unnecessary, and the data can be transferred in accordance with the processing of the host processor without requiring any special software.

[0009]

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, a master communication circuit 1 is provided as a transmitting communication circuit for transmitting data to a data communication line 4, and a slave communication circuit 2 is provided as a receiving communication circuit for receiving data from the data communication line 4. The slave communication circuit 2 includes an upper processor 3 that processes data received.

The master communication circuit 1 includes a transmission buffer memory 11 for storing transmission data, a clock generation circuit 13 for determining transmission timing, and data as transmission means for transmitting data in accordance with a clock generated by the clock generation circuit 13. And a transfer circuit 12.

The slave communication circuit 2 includes a data communication line 4
A data transfer circuit 21 for receiving data from the data transfer circuit 21. The data transfer circuit 21 operates as a processing request unit for outputting a processing request to the host processor 3 every time a predetermined amount of data is received. The slave communication circuit 2 also temporarily stores the processing request generated by the data transfer circuit 21 and matches the request reception timing by the upper processor 3 with a FIFO circuit 23 as a timing matching unit. A reception buffer memory 22 for transferring the data to a processor.

The upper processor 3 includes a processing unit 31 and a memory 3
2 is provided.

A feature of the present embodiment is that the slave communication circuit 2 transmits a request to the master communication circuit 1 when the number of processing requests stored in the FIFO circuit 23 reaches the first reference value. When the number of processing requests reaches a second reference value smaller than the first reference value, the comparison circuit 24 and the reference value memories 25 and 26 are used as transmission control means for instructing the master communication circuit 1 to restart transmission. Have prepared. The output of the comparison circuit 24 is the master communication circuit 1
The clock generation circuit 13 can stop the clock generation by the transmission stop instruction and restart the clock generation by the transmission restart instruction.

Transmission buffer memory 1 of master communication circuit 1
The communication data stored in 1 is edited in units of transfer by the data transfer circuit 12 and transferred to the data transfer circuit 21 in the slave communication circuit 2 via the data communication line 4. At this time, the data transfer circuit 12 sends communication data to the data communication line 4 in synchronization with the clock generated by the clock generation circuit 13. The clock generated by the clock generation circuit 13 is also transmitted to the slave communication circuit 2 via the clock line 5.

Here, the transfer unit edited by the data transfer circuit 12 is a bit unit transmitted to the data communication line 4, and is 1 bit or 8 when performing serial transfer.
One unit is 8 bits when performing bit parallel transfer, and 32 bits when performing 32 bit parallel transfer.

Data transfer circuit 21 of slave communication circuit 2
Receives data from the data communication line 4 according to the clock from the clock line 5 and stores the data in the reception buffer memory 22 for each predetermined unit. At the same time as the data is stored in the reception buffer memory 22, the data transfer circuit 21 issues an interrupt processing request to the host processor 3 so as to pick up the communication data stored in the reception buffer memory 22. However, upper processor 3
May be unable to accept an interrupt processing request in protocol processing or other processing. Therefore, the processing request is temporarily stored in the FIFO circuit 23, and is transmitted to the interrupt line 8 after waiting until the processing unit 31 can receive the processing request.

The processing unit 31 of the host processor 3 addresses the communication data stored in the reception buffer memory 22 according to an interrupt processing request from the slave communication circuit 2.
The data is taken out via the data bus 7 and stored in the memory 32, and is further processed in a predetermined protocol processing, for example, X.50. 25 or TCP / IP or the like.

In the slave communication circuit 2, the comparison circuit 2
4, the number of processing requests stored in the FIFO circuit 23;
That is, the number of queues is monitored. When the number of queues reaches the first reference value stored in the reference value memory 25, the comparison circuit 24 stops the clock to the clock generation circuit 13 of the master communication circuit 1 via the clock stop line 6. Request. Upon receiving this request, the clock generation circuit 13
The operation of the data transfer circuit 12 is stopped, and the transmission of the clock to the slave communication circuit 2 is stopped. As a result, the data transfer to the slave communication circuit 2 is stopped, the flow of traffic that can be processed by the host processor 3 is stopped, and the overflow of the reception buffer memory 22 can be prevented. When the number of queues reaches the second reference value stored in the reference value memory 26 after the stop of the data transfer, the comparison circuit 24 resets the stop of the clock. As a result, communication from the master communication circuit 1 to the slave communication circuit 2 resumes.

[0020]

As described above, according to the transfer control method of the present invention, the remaining number of processing requests to the upper processor is monitored, and the transfer is automatically controlled based on the number. Therefore, there is no need to confirm the response by the host processor, and it is possible to prevent a reduction in throughput. Further, high-speed data transfer can be realized without requiring a complicated configuration such as a dedicated processor or software for transfer control.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 master communication circuit 2 slave communication circuit 3 host processor 4 data communication line 5 clock line 6 clock stop line 7 address / data bus 8 interrupt line 11 transmission buffer memory 12, 21 data transfer circuit 13 clock generation circuit 21 data transfer circuit 22 reception Buffer memory 23 FIFO circuit 24 Comparison circuit 25, 26 Reference value memory

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-3-15941 (JP, A) JP-A-2-149152 (JP, A) JP-A-6-37855 (JP, A) JP-A-5-37855 282144 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 13/08 G06F 13/00 353 H04L 29/08

Claims (1)

(57) [Claims] 1. A transmission for transmitting data to a data communication line.
Communication circuit and a receiving communication circuit for receiving data from the data communication line.
And a higher-level processor that processes data received by the receiving communication circuit.
And a receiver, wherein the receiving side communication circuit has a predetermined amount of data.
Each time a data request is received, a processing request is issued to the host processor.
Processing request means to be executed and the processing in which the processing request means has occurred.
Request temporarily stored by the host processor
Timing matching means for matching with the reception timing;
Temporarily store communication data and transfer it to the host processor.
Transfer control system including a receiving buffer memoryThe transmission side communication circuit includes a transmission buffer for storing transmission data.
Generates memory and clock to determine transmission timing
And supplies the clock to the communication circuit on the receiving side.
Clock generation circuit and the clock generation circuit
Transmission means for transmitting data in accordance with the set clock.
Including  The receiving side communication circuit,The data from the transmitter communication circuit
Clock received from the clock generation circuit
According toStored in the timing adjustment means
Above when the number of processing requests
Transmission side communication circuitClock to the above clock generation circuit.
Order to stop generatingAfter that, the number of processing requests
When reaching the second reference value smaller than one reference value
Transmission side communication circuitClock generation circuit
Generates a lockIncluding transmission control means for instructing resumption
Transfer control method.