JPS59205855A - Line adaptor - Google Patents

Abstract

PURPOSE:To relieve the load on a communication controller by using an FIFO used as a data buffer to relieve a temporary peak of a character processing time in the communication controller. CONSTITUTION:A received data bit of start-stop type inputted from data communication line is stored in he timing being n-times of the bit transmission speed of the data communication line by an FIFO memory 4. A receiving control circuit 6 checks the state of a universal receiver transmitter (UART)5 in the timing higher in speed than the speed of the n-times the bit transmission speed of the data communication line and when this UART5 does not request the reception of receiving character to the comunication controller 8, the receiving data bit stored in the FIFO memory 4 is transferred to the UART5 together with the timing signal in the timing higher in speed than the n-times speed of the bit transmission speed of the data communication line.

Description

Detailed Description of the Invention [Field of the Invention] The present invention relates to a line adapter, and particularly to a communication control system that transmits predetermined received data from a data communication line to a data processing device or the like via a communication control device. The present invention relates to a line adapter that makes it possible to appropriately capture the received data in response to increasing bit rates in communication lines.

[Prior art]

Conventionally, as shown in FIG. 1, start-stop type received data from a data communication line is configured into predetermined characters in a line adapter 1, and the output received data is input into a communication control device 2 character by character. , communication control device 2
A communication control device configured to input the received data to the data processing device 3 via a communication control function is often used.

In this conventional communication control device, when the communication control device 2 receives data of a special received character, the processing time for that received character may temporarily take longer than a predetermined value. Even when dealing with such special received characters, there are well-known devices that shorten the received character processing time in the communication control device 2 so that subsequent received data can be received normally without overflowing. There is. However, when the bit transmission speed in the data communication line becomes faster, it becomes difficult to shorten the character processing time mentioned above in the communication control device 2, and the advanced communication control that connects the data communication line and the data processing device 3 becomes difficult. The disadvantage is that the implementation of the function is hindered.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a line adapter that eliminates the above-mentioned drawbacks, alleviates the temporary peak value of character processing time in a communication control device, and maintains all advanced communication control functions.

[Structure of the invention]

The line adapter of the present invention is used in a communication control system that configures asynchronous received data input as a time-series signal from a data communication line into characters of a predetermined bit length and transmits the data to a data processing device. a first-in first-out shift memory that sequentially stores data at a bit rate n (an integer greater than 1) times the bit rate of the data communication line; and inputting the received data stored in this shift memory. A universal receiver transmitter configured into a character of a predetermined bit length and transmitted to a communication control device, when there is no request from this universal receiver transmitter to the communication control device to take over the received data. Sequentially reading out data stored in the first-in first-out φ shift memory at a bit rate higher than the n-times bit rate and transmitting the data to the universal receiver transmitter; When a request is made to the communication control device to take over the received data, the controller also controls temporarily stopping transmission of the received data to the first-in/first-out shift memory and the universal receiver/transmitter. and a reception control circuit.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing an example of a communication control system including the main parts of an embodiment of the present invention, and related communication control devices and data processing devices. As shown in FIG. 2, the line adapter 7 of the present invention has a first-in first-out shift memory 4. ! :, includes a universal receiver transmitter 5 and a reception control circuit 6, and includes a universal receiver transmitter 5ff,
A communication control device 8 and a data processing device 9 are connected through it.

In FIG. 2, start-stop type received data bits input from a data communication line are stored in a first-in/first-out shift memory 4 provided in a line adapter 7 at a bit transmission rate n of the bit transmission rate of the data communication line.
(an integer greater than 1) times the timing. The reception control circuit 6 checks the state of the universal receiver/transmitter 5 at a timing faster than n times the bit transmission speed of the data communication line, and the universal receiver/transmitter 5 performs communication (i1 control). When no request is made to the device [8 to take over the received character, the received data bits stored in the first-in-first-out-door shift memory 4 are transferred to the data communication line via the above-mentioned data communication line. The timing signal is transferred to the universal receiver-transmitter 5 at a speed higher than n times the transmission speed, and at the same time, the timing signal is also transmitted manually. 1. When the universal receiver transmitter 5 requests the communication control device 8 to retrieve the received character, the communication control fi+ device 8
The transfer of received data bits from the first-in, first-out shift memory 4 to the universal receiver-transmitter 5 is continued until the universal receiver-transmitter 5 has finished acquiring the received characters stored in the universal receiver-transmitter 5. , is prohibited under the control of the reception control circuit 6. That is, through the control action of the reception control circuit 6, the first-in/first-out shift memory 4 and the universal e-receiver/transmitter 5
The start-stop type received data bits from the data communication line can reduce the character processing time in the communication control device 8 even when the bit transmission speed on the data communication line becomes faster. The above-mentioned troubles that occur due to data processing are completely eliminated, and the data is smoothly transmitted to the data processing device 9 via the communication control device 8fc.

〔Effect of the invention〕

As described above in detail, the present invention enables the data communication line and the data processing device to be connected to each other without being hindered by the functional limitations of the communication control device even when the bit transmission speed in the data communication line becomes high. This has the effect of realizing an advanced communication control function that connects the

[Brief explanation of the drawing]

Fig. 1 is a conceptual block diagram of a communication control system that fully connects a conventional data communication line and a data processing device, and Fig. 2 is a block diagram of a trace control system to which an embodiment of the present invention is applied. . In the figure, 1.7...Line adapter, 2
．． 8...Communication control device, 3,9...Data processing device, 4...First-in/first-out shift memory, 5...Universal receiver - Transmitter, 6... Communication control circuit. Figure Z

Claims (1)

[Claims] In a communication control system that configures start-stop synchronized received data input as a time-series signal from a data communication line into characters with a predetermined bit length and transmits the converted data to a data processing device, the received data is converted into bit-length characters on the data communication line. A first-in first-out shift memory that sequentially stores data at a bit rate n (an integer greater than 1) times the rate; A universal receiver that configures characters and transmits them to a communication control device.
Transmitter, this universal receiver transmitter receives the received data from the communication control device! If there is no request, the data stored in the first-in/first-out shift memory is sequentially read out at a bit rate higher than the n-times bit rate and transmitted to the universal receiver/transmitter. , and the universal receiver.
When there is a request from the transmitter to the communication control device to take over the received data, the first-in, first-out, shift memo! a reception control circuit that also controls temporarily stopping transmission of the received data from the universal receiver transmitter to the universal receiver transmitter.