JPS6364435A - Multi-slot access annular transmitter - Google Patents

Abstract

PURPOSE:To attain the efficient transmission by displaying a slot number used at the head to a slot other than the head so as to reduce slot header information. CONSTITUTION:A transmission packet from information processing units 21, 32 is stored in a transmission data buffer section 113 via a device adaptor 115 under the control of a transmission controller 114, The buffer section 113 sends a transmission start SREQ to a transmission access control section 4. The control section 4 receiving it detects a transmission enable slit and sends the packet by using it. Moreover, a reception access control section 6 detecting the slot addressed thereto from a received data RD informs the start of data reception by using the reception start RREQ to a reception data buffer section 112. A reception timing RTIM and a final command RLST are fed to the buffer section 112. The received packet in the buffer section 112 is transferred to the corresponding connection device via the adaptor 115 under the control of the control section 114.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ring transmission device, and particularly to a ring transmission device in which the transmission format is formed of time-division slots of a fixed length, and an arbitrary number of these slots are used to transmit data. The present invention relates to a ring transmission device that performs transmission.

[Conventional technology]

Regarding transmission equipment for conventional slot access local area networks, see Bell System Technical Journal, Volume 51, No. 6, 1972.

Pages 1133 to 1145 (THE BELLSY
STEM TECt(NICAL JOURNAL, V
ol, 51, Na6.

As discussed in 1972 (pp. 33-1145), after capturing an empty time slot, data is transferred by adding head information such as destination and source address.

[Problem that the invention seeks to solve]

The above conventional technology does not take into account the reduction of slot header information, and even when long data information is divided and transmitted at an arbitrary location and number of slots, header information is required for each slot, which is not efficient. There was a problem that transmission was not possible.

An object of the present invention is to provide a ring transmission device that can reduce the amount of ladder information to slots in the case described in item 1 and perform efficient transmission.

[Means for solving problems]

``Objective 1 is achieved by not assigning destination/source addresses as header information to slots other than the first one, and instead displaying the slot number used at the first slot.

[Effect]

When the receiving side first detects that the information is addressed to itself based on the destination address in the first slot, it operates to store this time slot number. This makes it possible to determine whether the packet is addressed to itself by checking, so there is no need to add header information such as destination and source address to the slot header for each slot.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is an example of a transmission time chart in a ring transmission system to which the present invention is applied, and illustrates the features of the present invention.

Here, a "packet" is a unit of information that a transmission device is requested to transfer from an information processing device connected to the device.

Usually, in addition to the data part DATA, this bucket 1 has information such as a destination address, a source address, or an error check as a packet header part (PH).

On the other hand, in a ring transmission system employing a slot access method, the second signal on the transmission line is a transmission unit called a frame that circulates continuously.

The transmission frame has a function synchronization unit FSYN indicating a break.
Packet transfer is performed using a plurality of time throwers 1-.

The time slot is also roughly divided into a slot header section TH containing information indicating whether it is empty or in use, and a data section, and bucket 1 to information are stored in the data section.

Let's consider a case where a packet longer than the slot length is transferred. In this case, a plurality of time slots are required, but if empty slots are used at arbitrary positions as indicated by diagonal lines in the figure, the relationship between them must be indicated by some means.

A general method to solve this problem is to add the destination and source address information contained in the bucket l-hesida part PTI of each time slot, but this does not make the use of slots efficient. becomes worse. This is because the scoot 1~length is usually short, about several 10 bytes, whereas the address information is quite long, 2~6 bytes.

In the present invention, in order to reduce this problem, the thrower I/header T H
Inside, there is an indication that the slot was used at the beginning, middle, or end, and the number of the time slot used at the beginning (second in the figure). It can be seen that the former requires only 2 bits, and the latter only a few bits (8 bits or less), which is less than having the 71~res information.

FIG. 2 shows an example of the overall configuration of a ring transmission system to which the present invention is applied. As shown in the figure, various information processing devices 21 to 3 are distributed and installed at various locations within the premises, such as factories, buildings, and university campuses.
2 join the system via transmission devices 11 to 16, respectively, and exchange information with each other. The transmission device is connected to the pin 1 in a ring shape by a serial transmission line 3, forming a ring network.

The system shown in this figure is oriented toward integrated multimedia transmission, and is designed to accommodate a mixture of traffic with different characteristics.

The slot access method is suitable for application to the above-mentioned transmission systems, such as ITV 26, monitor 28° telephones 25, 29, which require periodic transmission with long holding times.
．． FAX, 22. Computers 24 and 3 that are required to allocate slots with a certain transmission capacity to PBX 23, use them continuously, and transmit in bursts with short hold times.
2. Works John 21. PC group 27° filing device 30. via lower LA, N. Any number of empty slots 1- can be shared by printers 31 and the like. Another advantage is that the allocation of the slowers l~ to both types of traffic can be flexibly realized depending on the system.

FIG. 3 shows an example of a time slot format, in which all time slots within a frame are the same.

The header section is formed of the following three types of information.

1) Free/Busy Bit (F/B) Indication of whether this slot is empty or occupied.

2) First slot number (FSN) Indicates the time slot number used to transmit the first part of the packet.

3) Scot 1 - Type (TYP) The information entered in the data section indicates whether the head to bucket 1 is intermediate, final, or single (first and final).

In addition, the data section is 4 shown in the diagram according to the above slot type.
Becomes a seed. Each item is as follows.

1) Destination address (DA) The address of the person who should receive messages to this bucket 1.

2) Source address (SA) Address of the transmission device that sends this packet.

3) Data length (LN G) Length of this packet data part.

4) Data information (DATA) Contents of this packet data section.

5) Error check (Fe2) Transmission error check code in this packet.

As shown in this diagram, D A , S A , L N G
, FCS, etc., does not need to be added to each slot even when this packet is divided and transmitted using a plurality of time slots.

When a plurality of transmission devices are transmitting simultaneously, the uniqueness of the first slot number (F S N) is guaranteed by continuing to occupy the slot used at the beginning until the transmission is completed, as in this example. Alternatively, a reserve pin 1- bit may be further provided in the header section to prohibit other transmission devices from using the time thrower 1- used at the beginning at the beginning or only until transmission is completed.

FIG. 4 shows an example of the hardware configuration of the ring transmission device. The transmission device 11 has a line section [1] which corresponds to the transmission line 3 and includes the following functions.

1) Receiver (l l 11) This converts line signals into digital signals, and has functions such as signal amplification, bit timing generation, digital signal reproduction, and demodulation. In addition, if the transmission line is a lead wire, it also has an optical/electrical conversion function.

2) Transmitter (1112) This converts digital signals into line signals, and has functions such as reverse modulation, signal drive, and electrical/optical conversion.

3) Frame control unit (111, 3) Has functions such as generation, adjustment, and detection of transmission frames consisting of multiple time slots.

4) Slot timing generator (1), i4) Receiver 1
111, frame control unit]-113, and instructs the access control unit 1 regarding various slot timings.

5) Line multiplexer (111-5) Switches the data path output from the transmission device. The selection is instructed by the access control unit 1, and one of the received data relay, slot header information, and Scot 1 to data information is selected.

(1) In addition, an access control unit that controls data transmission and reception using time slots 1 to 1], a reception data buffer unit 112 that stores received data. A transmission data buffer section 113 for storing transmission data. The components include a transmission controller that controls the transfer of information between the transmitting/receiving data buffer section and the device correspondence section 15, and a device correspondence section 115 that controls the interface between the connected device and this transmission device. The access control section 1 is roughly divided into a transmission access control section 4 that controls time slot access during transmission, and a reception access control section 6 that controls time slot access during reception.

Next, the transmission operation of this transmission device will be explained.

Transmission packets from the connected devices (information processing devices) 2], 32 are sent to the transmission data buffer unit 1], 3 via the device support unit 115 under the control of the transmission controller 1-roller 1]-4.
is stored in

The transmission data buffer section 1-13 is the transmission access control section 4.
A transmission activation 5REQ is issued for. Upon receiving this, the transmission access control unit 4 detects a slot in which transmission is possible, and uses this to perform transmission of bucket 1-.

Slots that can be transmitted are slots that are displayed as ``empty'' and slots that have been used for self-transmission and after ring cycling.

In addition, the specific method of packet transmission is
Slot header information STH is output from the transmit data buffer section 1-13, and then transmit data SD is output from the transmit data buffer section 1-13 at the transmit timing STIM.

Sending of this information to the line is performed by controlling the line multiplexers 1 to 5 using the selection signal MSEL.

The timing information received from the slot timing generation unit 1114 includes the following.

],)]Time slot 1 number counter I-value T S N
) 2) Slot header indication timing (SHT) 3) Slot boundary indication timing (SLT) 4) Byte timing (BYT) The above functions are achieved by these.

The instruction as to whether or not this is the final slot is transmitted from the transmission data buffer (]3) section 113 to the transmission access control section 4 as a final instruction S LST.

After the transmission is completed, the transmission access control unit 4 releases the slots that have gone around the ring for self-transmission.

On the other hand, the packet reception operation is executed as follows.

The reception access control unit 6 detects the self-addressed slave 1 through reception of the reception data, and notifies the reception data buffer unit 1]2 of the start of data reception by a reception activation RREQ. Reception timing RTIM and final instruction RT, S
T is also supplied to the reception data buffer section 112.

The received packets stored in the received data buffer section 112 are transferred to the device handling section 11 under the control of the transmission controller 114.
5 to the corresponding connected device.

FIG. 5 shows a more detailed hardware configuration of the transmission access control section 4. This circuit consists of the following means.

1) Means for determining empty slots that can be used for transmission from received data RD.

2) Means for rewriting a new slot header in place of the empty time slot. Note that this slot header includes information such as a busy indication, an indication of first, intermediate, final or single type, and the slot number used first.

3) Means for supplying sending timing to the sending data buffer unit.

4) After the transmission is completed, a means for releasing the time slot corresponding to the amount of self-transmission that has completed one round of the ring.

The detailed configuration of each will be explained below.

1) The empty time slot detection means verifies the slot header part in the received data RD with the decoder 49 and searches for a free display slot header, and the comparator 6
7, it is checked whether the content of the register 45 that stores the leading slot numbers 1 to 1 matches the leading slot number in the slot header in the received data R and D, and the slot that has gone around the ring based on the self-transfer amount is searched. It has been realized.

The slot header rewriting means 2) is further comprised of the following detailed means.

a) Means for generating slot types.

b) Leading slot number generation means.

C) means for generating selection signals for the line multiplexer.

Regarding a), a counter 50, a decoder 46.47, a flip-flop 56. And gate 58°59.63,
ORGATE 65.66 is relevant.

The flip-flop 56 is for storing the presence or absence of a transmission request, and is used to store transmission activation 5R from the transmission data buffer unit 113.
It is set by EQ and reset to 1 by final instruction 5LST.

The counter 50 uses the final instruction 5LST as input data and the transmission start 5REQ as a set signal, and its output is supplied to the busy slot header pattern register 43. The value of the counter 50 is 0.0 when the transmission packet is composed of a plurality of slots, and otherwise the values of 1 and 1 are respectively input. The former indicates the beginning of the slot type, and the latter indicates single. Decoders 46 and 47 must be at the beginning (0, 0), beginning or middle (O, X,), respectively.
And gate 58, 59゜63
, orday 1 to 65.66, it operates so that +1 is added when transmitting the first slot and when transmitting the last time slot.

For b) multiplexer 41. flip flop57. It is composed of a register 45. flip flop 5
Reference numeral 7 is for distinguishing the status of whether or not the first time slot is being transmitted.The transmission activation 5REQ is used as a set input, and the output of Antogames 1 to 58 indicating that the first slot has been successfully transmitted is used as a reset input. The output of this flip-flop serves as a selection signal for the multiplexer 41, which selects the time slot number count output TSN from the slot timing generation unit 1114 as the first slot number when transmitting the first time slot, and transmits the subsequent slots. Sometimes, the first slot number storage register 45 side is selected.

The first slot number storage register 45 includes an AND gate 5 so that the number of the first time slot used is stored.
With 8 outputs, TSN is set to 1~.

Regarding C), flip-flops 53, 54, 55 and an OR gate 64 are involved.

The flip-flop 53 is used to remember that this is a time slot for transmitting data and evening data, and the output of the AND gate 63 is used as a set input, which is reset by the output of the flip-flop 55 when slot data transmission starts.

The flip-flop 54 is used to instruct the period for sending out the ivy to the slot, and is input to the output of the OR gate 64, that is, the slot header sending request cell 1, and is cleared when the sending of the ladder to the slot is completed.

The flip-flop 55 is for instructing the thrower 1 data transmission period, and is set at the time of slot data transmission when the output of the flip-flop 53 is on when the ladder transmission to the slot is completed. The reset is based on slot 1 to timing SLT indicating slot divisions.

The outputs of both flip-flops 54 and 55 become the selection signal MSEL for the line multiplexer 1115.

The sending timing 3) can be created by logically ANDing the output of the flip-flop 55 and the byte timing BYT using an AND gate 62. This is the transmission data buffer section 11
This is the transmission timing STIM for 3.

4) The occupied slot is released in register 42. Decoder 48
．． Register 44. Comparator 51. Flip-flop52. This is realized by AND gates 60 and 61.

Register 42 stores the empty slot header pattern.

The decoder 48 detects that the output of the slot type generation counter 50 is the final one.

The AND gate 60 creates a condition for sending the final slot and transmits it to the register 44.

The register 44 is used to store the slot number used for sending out the final slot.

The comparator 51 is for detecting that the slot stored in the register 44 has circulated again.

The flip-flop 52 is used to indicate the period of one round slot erasure, is set when the final slot is sent out, and is reset by the coincidence detection output from the comparator 51.

The AND gate 61 performs self-sending one round slot detection from each output of the flip-flop 52 and the comparator 67. This result is an or gate 64° flip-flop 54
via which the line multiplexer 1115 selects slot header transmission.

Multiplexer 40 combines the contents of register 42 with register 4.
This is for selectively sending out one of the contents of 3. In the case of - cycle erasure, there is no instruction from the AND gate 63, so the register 42 side is selected.

FIG. 6 shows a more detailed hardware configuration of the reception access control section 6. This circuit consists of the following means.

1) Determine the self-destination slot.

2) Supplying the reception timing to the reception data buffer section 112.

Here, 1) is further subdivided as follows.

a) busy and in the first or single type slot;
Detection that it also has its own destination address.

b) Detection of a busy slot with the same leading slot number display as memorized.

The detailed configuration of each will be explained below.

1-a) is a decoder (with latch function) 72. Comparator 74. flip flop75. Tests whether the type of AND slot is single, initial, or final.

The comparator 74 verifies whether or not the destination address of the first slot or a single type slot is addressed to itself.

The flip-flop 75 is for storing that the first slot has been received, and is set by the AND gate 79 output, that is, the signal indicating that the first slot addressed to itself has been received when it is not receiving, and the AND gate 80 output, that is, the last slot. It is reset when it is detected.

The AND gate 79 is as described above, and 81 instructs detection of a single slot.

1-b) is the buffer 71. This is realized by a comparator 73 and gates 78 and 80.

The buffer 71 is for storing the time slot number of the first slot addressed to itself, and is instructed to be fixed by the output of the AND gate 79.

) The comparator 73 is provided to verify whether there is a slot number that is the same as that stored in the buffer 71 marked with Y in the header of the received slot.

The AND gate 78 instructs to detect slots addressed to itself after the beginning.

The AND gate 80 specifically instructs reception of the final slot addressed to itself.

2) The flip-flop 76, which is composed of a flip-flop 76, an AND gate 77, OR gates 82, 83, 84, etc., is provided to indicate the period of the slot addressed to itself, and detects the output of the OR gate 84, that is, the slot addressed to itself. When this occurs, a cell is activated and this continues for one time slot.

The AND gate 77 passes the reception timing RTIM to the reception data buffer section 112.

The OR gates 83 and 82 are also the receive data buffer section 1.
12, respectively, a reception request RREQ and an end instruction RLST.
give.

〔Effect of the invention〕

According to the present invention, even when long data is divided and transmitted at arbitrary locations and number of slots, there is no need for destination/source address information, etc. in slots other than the first, resulting in efficient transmission.

[Brief explanation of drawings]

FIG. 1 is a transmission format diagram according to an embodiment of the present invention;
Figure 2 is an example of the overall configuration of a circular transmission system, Figure 3 is an example of a time slot format, Figure 4 is an example of the hardware configuration of a circular transmission device, Figure 5 is an example of the hardware configuration of the transmission access control section, and Figure 6 is The figure is a hardware configuration diagram of the reception access control section. 1.3...Transmission line, 11-16...Transmission device, 2
1 to 32... Information processing device, 111... Line section, 1
111...Receiver, 1112...Transmitter, 1113...
...Frame control unit, 1114...Slot timing generation unit, 1115...Line multiplexer, 112
... Reception data buffer section, 113 ... Transmission data buffer section, 114 ... Transmission controller, 115.
... device support section, 1 ... access control section, 4 ... transmission access control section, 7 ... reception access control section, 40
．． 41...Multiplexer, 42, 43.45...
Register, 46°47.48.49...Decoder, 50
... Counter, 51.67 ... Comparator, 52
,53,54゜55.56,57...Flip-flop, 58゜59.60,61,62,63...And gate, 64.65...Or gate, 71...Buffer, 72...・Decoder, 73.74...Comparator, 75°76...Flip-flop, 77.78,
79°80.81...and gate, 82,83,8
4...or gate.

Claims (1)

[Claims] 1. A plurality of transmission devices are connected to a ring transmission line to form a ring transmission system, and at least one transmission device transmits a transmission frame consisting of a transmission unit consisting of a plurality of time slots. Each transmission device detects any empty slot in the frame, adds header information including an address to the data transferred from the accommodated information processing equipment, transmits it, and sends it to the received slot. In a circular transmission device that determines the destination from the address in the slot, receives the data in the slot, and transfers it to the corresponding information processing device, the transmission time slot determines whether or not each transmission slot includes header information. 1. A multi-slot access circular transmission device, characterized in that the multi-slot access circular transmission device has means for giving an indication that the time slots are from the same source, and means for indicating that the time slots are from the same source, and that only specific time slots include header information. 2. The means for instructing whether header information is included or not, as set forth in claim 1, includes a busy display indicating that the time slot is in use, and the beginning and middle of the data to be sent by the time slot. , and a type indication indicating final or single type. 3. The multi-slot access circular transmission device according to claim 1, wherein the means for indicating that the time slots are from the same source is the slot number of the first time slot used. 4. The multi-slot access circular transmission device according to claim 3, wherein the time slot numbers are in the order of time slots counted from the beginning of the transmission frame. 5. A plurality of transmission devices are connected to a ring transmission path to form a ring transmission system, and at least one transmission device repeatedly generates a transmission frame consisting of a transmission unit consisting of a plurality of time slots, and each transmission The device detects any empty slot in the frame of the data transferred from the information processing equipment it accommodates, adds header information including an address to it, and sends it, and uses the address in the received slot to identify its own address. After the determination, the transmission method of the ring transmission device that receives the data in the slot and transfers it to the corresponding information processing equipment, the transmission frame information of arbitrary length is divided into multiple blocks of fixed length each with a slot header added. It is divided and transmitted, and each slot header has the beginning, middle, and final indications of the block and the slot number used when transmitting the first block, and the transmission device that should receive the transmitted frame information has the beginning indication and the slot number. The start of reception is determined from the address in
A multi-slot access circular transmission method characterized in that subsequent reception decisions are made based on slot numbers.