JPH0567100B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ring transmission device and method, and in particular, to a ring transmission device and method in which the transmission format is formed by time-division slots of fixed length, and an arbitrary number of these slots are used to transmit data. The present invention relates to a ring transmission device and method for performing transmission.

[Conventional technology]

For information on transmission equipment for conventional slot access local area networks, see Bell System Technical Journal, Volume 51, No. 6, 1972.
Pages 1133 to 1145 (THE BELL SYSTEM
TECHNICAL JOURNAL, Vol.51, No.6,
As discussed in 1972 (pp. 1133-1145), after capturing an empty time slot, head information such as destination and source address was added and data was transferred.

[Problem that the invention seeks to solve]

The above conventional technology does not take into consideration the reduction of slot header information, and even when long data information is divided and transmitted at an arbitrary location and multiple slots, header information is required for each slot, making efficient transmission impossible. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a ring transmission device and method that can reduce the amount of slot header information and perform efficient transmission in the above-mentioned cases.

[Means for solving problems]

The present invention writes information indicating the beginning, middle, and end of multiple blocks of divided packet data and the slot number of the time slot used to transmit the first block into the slot header of each time slot in a circular transmission device. a transmission access control section having means for loading packet header information including destination and source addresses only in the time slot in which the head block is transmitted; reception start determination means for determining whether or not to start reception based on the information represented and the address included in the packet header information; means for storing the slot number included in the slot header of the time slot when reception is determined to start; A receiver having a reception determination means for comparing the slot number included in the slot header of each time slot relayed via the channel with the slot number stored in the storage means and determining whether or not to receive that time slot. It is characterized by being provided with an access control section.

[Effect]

The sending side writes the slot number of the time slot used to send the first block to the slot header, and writes the information representing the beginning, middle, and end of the divided blocks into the slot header. It operates to load and transmit packet header information including the destination address. On the other hand, when the receiving side detects that the information is addressed to itself based on the destination address in the first slot of the time slot relayed via the transmission path, it stores the slot number of this time slot and operates to start reception. As a result, when receiving subsequent time slots, it is possible to determine whether or not they are addressed to the slot header by checking the match between the slot number attached to the slot header and the stored slot number. There is no need to attach header information such as for each slot.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is an example of a transmission time chart in a ring transmission system to which the present invention is applied, and shows the features of the present invention.

Here, a "packet" is a unit of information that a transmission device is requested to transfer from an information processing device connected to the device. Normally this packet is the data part.
In addition to DATA, the packet header (PH) contains information such as destination and source addresses and error checking.

On the other hand, in a ring transmission system employing the slot access method, signals on a transmission path are arranged in units of transmission called frames that circulate continuously.
The transmission frame has a frame periodic part that indicates a break.
It consists of FSYN and a plurality of time slots TS (eight in the figure, but any number may be used). Packet transfer is performed using multiple time slots.

The time slot is also roughly divided into a slot header section TH containing information indicating whether the time slot is empty or in use, etc., and a data section, and packet information is stored in the data section.

Now consider the case where a packet longer than the slot length is transferred. In this case, a plurality of time slots are required, but if empty slots are used at arbitrary positions as indicated by diagonal lines in the figure, the relationship between them must be indicated by some means.

A temporary method to solve this problem is to add the destination and source address information included in the packet header PH of each time slot, but this reduces the efficiency of slot usage. . This is because the slot length is usually short, about a few 10 bytes, whereas one address information has two to two
This is because it is required to be quite long at 6 bytes.

In the present invention, in order to reduce this problem, the slot header
The TH includes an indication that the slot was used at the beginning, middle, or end, and the number of the time slot used at the beginning (second in the figure). The former is 2 bits, the latter is several bits (8
(bits or less) is required, which means that it requires less than address information.

FIG. 2 shows an example of the overall configuration of a ring transmission system to which the present invention is applied. As shown in the figure, various information processing devices 21 to 32 distributed throughout the campus, such as factories, buildings, and university campuses, are connected to transmission devices 11 to 1, respectively.
6 to the system and mutually exchange information. The transmission devices are connected in a ring by a bit-serial transmission line 3, forming a ring network.

The system shown in this figure is oriented toward integrated multimedia transmission, and is designed to accommodate a mixture of traffic with different characteristics.

The slot access method is suitable for application to the above-mentioned transmission systems, such as ITV 26, monitor 28, etc., which require periodic transmission with long hold times.
Telephones 25, 29, FAX 22, PBX 23, etc. are required to be assigned slots with a certain transmission capacity and used continuously, and computers 24, 32, workstations 21 are required to transmit in bursts with short holding times. , PC group 27 via lower LAN,
Any number of empty slots can be shared by the filing device 30, printer 31, etc. There is also the advantage that slot allocation for both types of traffic can be flexibly realized depending on the system.

FIG. 3 shows an example of a time slot format, in which all time slots within a frame are the same.

The header section is formed by the following three types of information.

(1) Free/Busybit (F/B) Indication of whether this slot is empty or occupied.

(2) First slot number (FSN) Indicates the time slot number used to transmit the first part of the packet.

(3) Slot type (TYP) Indicates whether the information to be entered in the data section is at the beginning, middle, end, or single (first and last) of the packet.

Furthermore, there are four types of data sections shown in the figure depending on the slot type. Each item is as follows.

(1) Destination address (DA) Address of the party that should receive this packet.

(2) Source address (SA) Address of the transmission device that sends this packet.

(3) Data length (LNG) Length of this packet data section.

(4) Data information (DATA) Contents of this packet data section.

(5) Error check (FCS) Transmission error check code within this packet.

As shown in this figure, it is not necessary to assign packet header information PH such as DA, SA, LNG, FCS, etc. to each slot even when the packet is divided and transmitted using multiple time slots.

When multiple transmission devices are transmitting simultaneously, the uniqueness of the first slot number (FSN) is guaranteed by continuing to occupy the first slot used until the transmission is completed, as in this example. Alternatively, one additional reserve bit may be provided in the header section to prohibit other transmission devices from using the time slot used at the head or only once until transmission is completed.

FIG. 4 shows an example of the hardware configuration of the ring transmission device. The transmission device 11 has a line section 111 that corresponds to the transmission line 3 and has the following functions.

(1) Receiver (1111) Converts line signals to digital signals, and has functions such as signal amplification, bit timing generation, digital signal reproduction, and demodulation. In addition, if the transmission line is an optical system, it has an optical/electrical conversion function.

(2) Transmitter (1112) Converts digital signals to line signals, and performs inverse modulation, signal drive, electrical/
It has functions such as light conversion.

(3) Frame control unit (1113) Has functions such as generation, adjustment, and detection of transmission frames consisting of multiple time slots.

(4) Slot timing generation unit (1114) Receives timing from the receiver 1111 and frame control unit 1113, and instructs the access control unit 1 regarding various slot timings.

(5) Line multiplexer (1115) Switches the data route output from the transmission equipment. The selection is instructed by the access control unit 1, and includes relaying of received data, slot header information,
Select one of the slot data information.

In addition, there is an access control section 1 that controls data transmission and reception using time slots, a reception data buffer section 112 that stores reception data, a transmission data buffer section 113 that stores transmission data, and a section between the transmission and reception data buffer section and the device correspondence section 115. The components include a transmission controller 114 that controls the transfer of information, and a device support section 115 that controls the interface between the connected device and this transmission device. The access control section 1 is roughly divided into a transmission access control section 4 that controls time slot access during transmission, and a reception access control section 6 that controls time slot access during reception.

Next, the transmission operation of this transmission device will be explained.

Transmission packets from the connected devices (information processing devices) 21 and 32 are stored in the transmission data buffer section 113 via the device correspondence section 115 under the control of the transmission controller 114.

The transmission data buffer section 113 issues a transmission activation SREQ to the transmission access control section 4. Upon receiving this, the transmission access control section 4 detects a transmittable slot and uses this to transmit the packet.

Slots that can be sent are slots that are displayed as ``empty'' and slots that have completed one round of the ring for self-transmission.

In addition, the specific method of packet transmission is to issue a slot header status signal TSH from the transmission access control unit 4,
Subsequently, the transmission data buffer section 113 outputs transmission data SD according to the transmission timing STIM.

The selection signal is used to send this information to the line.
This is done by controlling the line multiplexer 115 using MSEL.

The timing information received from slot timing generation section 1114 includes the following.

(1) Time slot number count value (TSN) (2) Slot header instruction timing (SHT) (3) Slot boundary indication timing (SLT) (4) Byte timing (BYT) Through these, the above functions will be achieved.

An instruction as to whether or not it is the final slot is transmitted from the transmission data buffer section 113 to the transmission access control section 4 in the final instruction SLST.

After the transmission is completed, the transmission access control unit 4 releases the slots that have been sent around the ring by itself.

On the other hand, the packet receiving operation is executed as follows.

The reception access control unit 6 detects the slot addressed to itself in the reception data RD and notifies the reception data buffer unit 112 of the start of data reception by a reception activation RREQ. The reception timing RTIM and final instruction RLST are also supplied to the reception data buffer section 112.

The received packets stored in the received data buffer section 112 are processed under the control of the transmission controller 114.
The information is transferred to the corresponding connected device via the device correspondence section 115.

FIG. 5 shows a more detailed hardware configuration of the transmission access control section 4. As shown in FIG. This circuit consists of the following means.

(1) A means of determining empty slots that can be used for transmission from the received data RD.

(2) Means for rewriting the empty time slot to a new slot header. Note that this slot header includes information such as a busy indication, an initial/intermediate/final or single type indication, and the slot number used first.

(3) Means for supplying transmission timing to the transmission data buffer section.

(4) A means of releasing the time slot for self-transmission that has completed one round of the ring after transmission is completed.

The detailed configuration of each will be explained below.

The empty time slot detection means (1) is based on the received data.
The slot header part in the RD is verified by the decoder 49 to search for a free slot header, and the contents of the register 45 storing the first slot number and the received data are determined by the comparator 67.
This is achieved by checking for a match with the first slot number in the slot header during RD, and searching for slots that have made one circuit around the ring during self-sending.

The slot header rewriting means (2) is further comprised of the following detailed means.

(a) Means for generating slot types.

(b) First slot number generation means.

(c) means for generating selection signals for the line multiplexer;

For (a), the counter 50 and decoders 46, 4
7, flip-flop 56, and gate 58,
59, 63 and ORGATE 65, 66 are related.

The flip-flop 56 stores the presence or absence of a transmission request, and is set by the transmission activation SREQ from the transmission data buffer section 113, and receives the final instruction.
Reset with SLST.

The counter 50 takes the final instruction SLST as input data and uses the transmission start SREQ as a set signal.
Its output is provided to the busy slot header pattern register 43. The value of the counter 50 is 0 when the transmitted packet is composed of multiple slots;
A value of 0 is input, otherwise a value of 1 is input. The former indicates the beginning of the slot type, and the latter indicates a single slot type. The decoders 46 and 47 detect the beginning (0, 0), the beginning or the middle (0, X), and the AND gates 58, 59,
63, in combination with ORGATE 65, 66,
It operates so that it is incremented by 1 when transmitting the first slot and when transmitting the last time slot.

Regarding (b), it is composed of a multiplexer 41, a flip-flop 57, and a register 45. The flip-flop 57 is used to distinguish whether or not the first time slot is being transmitted.
is used as a set input, and the output of the AND gate 58 indicating that the first slot has been successfully sent is used as a reset input. The output of this flip-flop serves as a selection signal for the multiplexer 41, which selects the time slot number count output TSN from the slot timing generator 1114 as the leading slot number for the first time slot transmission, and then selects the time slot number count output TSN from the slot timing generator 1114 for subsequent slot transmission. Sometimes, the first slot number storage register 45 side is selected.

TSN is set in the first slot number storage register 45 by the output of the AND gate 58 so that the number of the first time slot used is stored.

For (c), flip-flops 53, 54, 5
5, or gate 64 is related.

The flip-flop 53 is for remembering that it is a time slot for sending data.
The AND gate 63 output is used as a set input, and this is input to the flip-flop 5 at the start of slot data transmission.
Reset with output 5.

The flip-flop 54 is used to instruct the slot header sending period, and is used as the output of the OR gate 64, ie, the slot header sending request set input, and is cleared when the slot header sending is completed.

The flip-flop 55 is used to instruct the slot data transmission period, and is set when slot data transmission is performed when the output of the flip-flop 53 is turned on when the slot header transmission is completed. The reset is the slot timing that indicates the slot separation.
By SLT.

The outputs of both flip-flops 54 and 55 become the selection signal MSEL for line multiplexer 1115.

The sending timing of (3) is the output of the flip-flop 55 and the byte timing BYT and the AND gate 6.
It can be created by taking the logical product in 2. This is the transmission timing for the transmission data buffer section 113.
It is STIM.

(4) Release of occupied slots is realized by register 42, decoder 48, register 44, comparator 51, flip-flop 52, and AND gates 60 and 61.

Register 42 stores an empty slot header pattern.

The decoder 48 detects that the output of the slot type generation counter 50 is the final one.

AND gate 60 creates conditions for final slot sending and transmits them to register 44.

Register 44 is used to store the slot number used for the final slot transmission.

The comparator 51 is for detecting that the slot stored in the register 44 has been circulated again.

The flip-flop 52 is for instructing the period of one round slot erasure, and is set when the final slot is sent out, and is reset by the match detection output from the comparator 51.

The AND gate 61 performs self-sending one round slot detection from each output of the flip-flop 52 and the comparator 67. This result is ORGATE 64,
The line multiplexer 1115 is caused to select the output of the slot header via the flip-flop 54.

The multiplexer 40 is for selectively sending out either the contents of the register 42 or the contents of the register 43, and in the case of one-round erasure, since there is no instruction from the AND gate 63, the register 42 side is selected.

FIG. 6 shows a more detailed hardware configuration of the reception access control section 6. This circuit consists of the following means.

(1) Determine the slot addressed to you.

(2) Supplying the reception timing to the reception data buffer section 112.

Here, (1) is further subdivided as follows.

(a) Detection of a slot that is busy, first or of a single type, and has its own destination address.

(b) Detection of a slot that is busy and has the same first slot number display as memorized.

The detailed configuration of each will be explained below.

(1)-(a) is composed of a decoder (with latch function) 72, a comparator 74, a flip-flop 75, and AND gates 79 and 81.

The decoder 72 verifies whether the type of busy slot is single, first, or last from the received data RD.

The comparator 74 tests whether the destination address of the first slot or a single type slot is its own address.

Flip-flop 75 is used to remember that the first slot has been received, and is set by the AND gate 79 output, that is, a signal indicating that the first slot addressed to itself has been received when reception is not in progress, and is set by the AND gate 80 output, that is, the last slot. It will be reset upon detection.

AND gate 79 is as described above, and 81 instructs detection of a single slot.

(1)-(b) are realized by buffer 71, comparator 73, AND gates 78, 80, etc.

The buffer 71 is for storing the time slot number of the first slot addressed to itself, and is instructed to be fixed by the output of the AND gate 79.

The comparator 73 is provided to verify whether the same slot number as that stored in the buffer 71 described above exists in the header portion of the receiving slot.

The AND gate 78 instructs to detect the slots addressed to itself after the beginning.

AND gate 80 specifically instructs reception of the final slot addressed to itself.

(2) is flip-flop 76, AND gate 7
7. Consists of OR gates 82, 83, 84, etc.

A flip-flop 76 is provided to indicate the own slot period, and is set when the OR gate 84 output, that is, the own slot is detected, so that it continues for one time slot.

AND gate 77 is the reception data buffer section 11
Pass the reception timing RTIM to 2.

The OR gates 83 and 82 also pass a reception request RREQ and a termination instruction RLST to the reception data buffer section 112, respectively.

〔Effect of the invention〕

According to the present invention, even when long data is divided and transmitted at arbitrary locations and through a plurality of slots, there is no need for destination/source address information, etc. in slots other than the first, resulting in efficient transmission.

[Brief explanation of drawings]

FIG. 1 is a transmission format diagram according to an embodiment of the present invention, FIG. 2 is an example of the overall configuration of a circular transmission system, FIG. 3 is an example of a time slot format, and FIG. 4 is an example of the hardware configuration of a circular transmission device. Fifth
The figure shows an example of the hardware configuration of the transmission access control unit.
FIG. 6 is a hardware configuration diagram of the reception access control section. 1, 3...Transmission line, 11-16...Transmission device, 21-32...Information processing device, 111...Line unit, 1111...Receiver, 1112...Transmitter, 1113...Frame control unit, 1114...
Slot timing generation section, 1115... Line multiplexer, 112... Reception data buffer section, 113... Transmission data buffer section, 114...
...Transmission controller, 115...Device support section, 1
...Access control unit, 4...Transmission access control unit, 7...Reception access control unit, 40, 41...
Multiplexer, 42, 43, 45...Register, 46, 47, 48, 49...Decoder, 50
... Counter, 51, 67 ... Comparator, 5
2, 53, 54, 55, 56, 57... flip-flop, 58, 59, 60, 61, 62, 63
...and gate, 64,65...or gate,
71...Batsuhua, 72...Decoder, 73,7
4... Comparator, 75, 76... Flip-flop, 77, 78, 79, 80, 81... AND gate, 82, 83, 84... OR gate.

Claims (1)

[Claims] 1. A plurality of transmission devices are connected to a ring transmission path to form a ring transmission system, at least one transmission device repeatedly generates a transmission frame consisting of a plurality of time slots, and each transmission device The packet data, which is transmission frame information of arbitrary length transferred from the accommodated information processing equipment, is divided into multiple blocks of fixed length, and the divided multiple blocks are loaded into multiple time slots each having a slot header attached to it and transmitted. In a ring transmission device that determines the destination of the packet based on the address included in the header information of the received packet in the slot, receives the data in the slot, and transfers it to the corresponding information processing device, the slot header of each time slot is means for writing information representing the beginning, middle, and end of the plurality of divided blocks and the slot number of the time slot used when transmitting the first block; and means for writing the packet header information only in the time slot for transmitting the first block. a transmission access control unit having means installed therein; and determining whether or not to start reception based on information representing the head of the block in the time slot relayed via the transmission path and an address included in the packet header information. means for storing the slot number included in the slot header of the time slot when the reception start determination means determines that the reception has started; The present invention is characterized in that it is provided with a reception access control section having reception determination means for comparing the slot number included in the slot header with the slot number stored in the storage means and determining whether or not the time slot concerned should be received. Multi-slot access ring transmission equipment. 2. A multi-slot access circular transmission device according to claim 1, wherein the slot number is the order of time slots counted from the beginning of a transmission frame. 3 A plurality of transmission devices are connected to a ring transmission path to form a ring transmission system, and at least one transmission device repeatedly generates a transmission frame consisting of a transmission unit consisting of a plurality of time slots, and each transmission device detects any empty slot in the frame for the data transferred from the accommodated information processing equipment, adds packet header information including the address to this, sends it, and determines the destination from the address in the received slot. In the transmission method of the ring transmission device, which then receives the data in the slot and transfers it to the corresponding information processing equipment, the transmission frame information of arbitrary length is divided into multiple blocks of fixed length each with a slot header attached. The packet header information is added to each slot header, and the slot number used when transmitting the first block is added to each slot header. A multi-slot access circular transmission method characterized in that a transmission device that is to receive transmission frame information determines the start of reception based on the header indication and the slot address, and thereafter makes reception determination based on the slot number.